Multiplier - Latchup

1 / 1

Leaderboard

#	User	Language	Latency▼ ns	Throughput MHz	Area μm²	Score
1	aej	VHDL	7.51 (1 cycles)	133.14 (100.0%)	34051	90.60
2	nuttapat tamprasert	Chisel	7.51 (1 cycles)	133.14 (100.0%)	34051	90.60
3	guilhermegog	Verilog	7.51 (1 cycles)	133.14 (100.0%)	34051	90.60
4	iN1PE	Verilog	7.51 (1 cycles)	133.14 (100.0%)	34051	90.60
5	Mantra Solanki	Verilog	7.70 (1 cycles)	129.85 (100.0%)	35651	90.14
6	Justin Eng	Verilog	10.02 (1 cycles)	—	39955	55.28
7	widlarizer	Verilog	10.53 (1 cycles)	—	21423	58.04
8	LVK-96	Verilog	10.97 (1 cycles)	91.15 (100.0%)	20280	89.45
9	Allen Appukuttan	Verilog	10.97 (1 cycles)	—	20333	58.09
10	Eric Santigosa Lepe	Verilog	11.14 (1 cycles)	—	20315	58.02

Page 1