Find the Missing Number

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Submission #1

PASSED

RankingPercentile

Latency

45.44 (11 cycles)ns

8th

top 15%

Max Frequency

242.07MHz

8th

top 15%

Area

3300μm²

9th

top 17%

Submitted Solution

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready, // sic
  input wire i_valid,
  input wire [16-1:0] i_payload_nums_fragment,
  input wire i_payload_nums_last,
  output wire [16-1:0] o_payload,
  output wire o_valid
);

// Define your design here
  // Define your design here
  // I think there's really only one algorithm for this one.
  reg [15:0] result = 0;
reg [15:0] count = 1;
  reg valid = 0;
  reg first = 1;

// version with registered output.
always@(posedge clk) begin
  if (i_valid) begin
    if (first) begin
      result <= count ^ i_payload_nums_fragment;
    end else begin
      result <= result ^ count ^ i_payload_nums_fragment;
    end
    count <= count + 1;
    first <= 0;
  end
  valid <= i_valid && i_payload_nums_last;

  if ((i_valid && i_payload_nums_last) || reset) begin
    count <= 1;
    first <= 1;
  end
  if (reset) begin
    valid <= 0;
  end
end
assign i_ready = ~reset;
assign o_payload = result;
assign o_valid = valid;

endmodule

Generated Verilog

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready, // sic
  input wire i_valid,
  input wire [16-1:0] i_payload_nums_fragment,
  input wire i_payload_nums_last,
  output wire [16-1:0] o_payload,
  output wire o_valid
);

// Define your design here
  // Define your design here
  // I think there's really only one algorithm for this one.
  reg [15:0] result = 0;
reg [15:0] count = 1;
  reg valid = 0;
  reg first = 1;

// version with registered output.
always@(posedge clk) begin
  if (i_valid) begin
    if (first) begin
      result <= count ^ i_payload_nums_fragment;
    end else begin
      result <= result ^ count ^ i_payload_nums_fragment;
    end
    count <= count + 1;
    first <= 0;
  end
  valid <= i_valid && i_payload_nums_last;

  if ((i_valid && i_payload_nums_last) || reset) begin
    count <= 1;
    first <= 1;
  end
  if (reset) begin
    valid <= 0;
  end
end
assign i_ready = ~reset;
assign o_payload = result;
assign o_valid = valid;

endmodule

Timing Analysis

Path 1-4.134 ns

From: count[0]$_SDFFE_PP1P_/Q

To: count[15]$_SDFFE_PP0P_/D

Data Arrival: 3.944 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`count[0]$_SDFFE_PP1P_/CLK`
0.751	sky130_fd_sc_hvl__dfxtp_1	`count[0]$_SDFFE_PP1P_/Q`
0.751	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$644/C`
1.307	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$644/X`
1.307	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$657/A`
1.766	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$657/X`
1.766	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$667/B`
2.229	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$667/X`
2.229	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$673/C`
2.704	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$673/X`
2.704	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$679/C`
3.178	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$679/X`
3.178	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$685/C`
3.647	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$685/X`
3.647	sky130_fd_sc_hvl__o21ai_1	`$abc$635$auto$blifparse.cc:396:parse_blif$687/A2`
3.854	sky130_fd_sc_hvl__o21ai_1	`$abc$635$auto$blifparse.cc:396:parse_blif$687/Y`
3.854	sky130_fd_sc_hvl__a21oi_1	`$abc$635$auto$blifparse.cc:396:parse_blif$688/B1`
3.944	sky130_fd_sc_hvl__a21oi_1	`$abc$635$auto$blifparse.cc:396:parse_blif$688/Y`
3.944	sky130_fd_sc_hvl__dfxtp_1	`count[15]$_SDFFE_PP0P_/D`

Path 2-4.051 ns

From: count[0]$_SDFFE_PP1P_/Q

To: count[14]$_SDFFE_PP0P_/D

Data Arrival: 3.870 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`count[0]$_SDFFE_PP1P_/CLK`
0.751	sky130_fd_sc_hvl__dfxtp_1	`count[0]$_SDFFE_PP1P_/Q`
0.751	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$644/C`
1.307	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$644/X`
1.307	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$657/A`
1.766	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$657/X`
1.766	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$667/B`
2.229	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$667/X`
2.229	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$673/C`
2.704	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$673/X`
2.704	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$679/C`
3.178	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$679/X`
3.178	sky130_fd_sc_hvl__and2_1	`$abc$635$auto$blifparse.cc:396:parse_blif$682/B`
3.566	sky130_fd_sc_hvl__and2_1	`$abc$635$auto$blifparse.cc:396:parse_blif$682/X`
3.566	sky130_fd_sc_hvl__o21ai_1	`$abc$635$auto$blifparse.cc:396:parse_blif$684/A2`
3.758	sky130_fd_sc_hvl__o21ai_1	`$abc$635$auto$blifparse.cc:396:parse_blif$684/Y`
3.758	sky130_fd_sc_hvl__nor2_1	`$abc$635$auto$blifparse.cc:396:parse_blif$686/A`
3.870	sky130_fd_sc_hvl__nor2_1	`$abc$635$auto$blifparse.cc:396:parse_blif$686/Y`
3.870	sky130_fd_sc_hvl__dfxtp_1	`count[14]$_SDFFE_PP0P_/D`

Path 3-3.822 ns

From: count[0]$_SDFFE_PP1P_/Q

To: count[13]$_SDFFE_PP0P_/D

Data Arrival: 3.681 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`count[0]$_SDFFE_PP1P_/CLK`
0.751	sky130_fd_sc_hvl__dfxtp_1	`count[0]$_SDFFE_PP1P_/Q`
0.751	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$644/C`
1.307	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$644/X`
1.307	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$657/A`
1.766	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$657/X`
1.766	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$667/B`
2.229	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$667/X`
2.229	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$673/C`
2.704	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$673/X`
2.704	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$679/C`
3.178	sky130_fd_sc_hvl__and3_1	`$abc$635$auto$blifparse.cc:396:parse_blif$679/X`
3.178	sky130_fd_sc_hvl__and2_1	`$abc$635$auto$blifparse.cc:396:parse_blif$682/B`
3.566	sky130_fd_sc_hvl__and2_1	`$abc$635$auto$blifparse.cc:396:parse_blif$682/X`
3.566	sky130_fd_sc_hvl__nor2_1	`$abc$635$auto$blifparse.cc:396:parse_blif$683/B`
3.681	sky130_fd_sc_hvl__nor2_1	`$abc$635$auto$blifparse.cc:396:parse_blif$683/Y`
3.681	sky130_fd_sc_hvl__dfxtp_1	`count[13]$_SDFFE_PP0P_/D`

Post-Synthesis Verilog

Download synth.v