Append Sort - Latchup

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Submitted Solution

// Append Sort
//
// 5-stage always-ready pipeline using XS6 decimal floating point:
//   Stage 1: Binary-to-XS6 via split LUT (lower 7b BCD + upper 7b XS6)
//   Stage 2: XS6 + BCD -> XS6
//   Stage 3: Normalize (shift leading digit to MSB, record exponent)
//   Stage 4: Compare mantissa/exponent against prev, compute added digits
//   Accumulator: sum of added digits, output on last
//
// Mantissa is 24-bit XS6 (6 nibbles, digit+6 encoding: 0-9 → 6-15).
// Increment uses one-hot addition with sequential carry chain.
// Bump detection: if increment carry touches any significant (compared) digit.

// AI Assisted.
// 
// This solution was partially assisted by agentic AI tools.  I wrote the
// original code as bcd-float and didn’t consider all corner cases.  I had the
// agent convert the code to verilog (I tend to use VHDL for problems where I
// have function-generated lookup tables) and worked with it to fix the issue,
// which added the float increment operation.  I’m still not happy about that,
// but can’t think of a way to avoid it.  There was a lot of design iterations.
// It’s possible this solution could be further optimized.  
// 
// This design is fairly esoteric, since I wanted to avoid backpressure.  My
// main focus was on the data hazard in stage 4.  In order to get this path
// short, I used base 10 float, since it aligns leading digits for the
// comparisons, and also has the number of digits (exponent) as part of the
// format.
// 
// This was later changed to xs6 encoding vs bcd encoding.  Xs6 is just bcd+6.
// It allows bcd constants to be added and make use of a normal carry chain.
// With a fixup at the end.  This removes the compare-to-10’s from the bcd carry
// chain.  It is efficient to do xs6+bcd -> bcd as well as xs6+bcd -> xs6.
// 
// Warning 
// 
// this design does assume a limited number of inputs vs a max accumulator size.
// with 5 digit inputs and only 15 inputs, there’s no need to track the 7th+
// digit.  It won’t ever be able to affect anything.  If the design changes to
// unrestricted numbers of inputs with a simple cap on internal accumulator
// width this design can fail.
// 
// Suggestions
// 
// It might be better to use concepts from carry-lookahead.  Where info about
// the increment carry chain is pre-computed at the end of stage 4.  I was
// unsure if this would make things faster or slower.  Concepts from
// carry-select are also possible.  The xs6 increment can be used to compute
// digit+1 and digit+7 in parallel, potentially allowing a small mux based on
// carry in/out of each xs6 digit.
// 
// The agentic AI used 7-series in yosys for the timing estimates.  Because I
// was too lazy to download or set up something more relevant.  So there may be
// easy optimizations that I missed, or code styles that work better.
// 
// I’m much less interested in the competitive aspects, so feel free to clone
// and own this code.  Not sure on the ethics of that in terms of competition?

module Solution (
  input  wire        clk,
  input  wire        reset,
  output wire        i_ready,
  input  wire        i_valid,
  input  wire [13:0] i_payload_x_fragment,
  input  wire        i_payload_x_last,
  output wire [31:0] o_payload,
  output wire        o_valid
);

  wire [13:0] din = i_payload_x_fragment; // alias

  // --- LUTs for binary-to-BCD conversion ---
  // (I really hope the tools know this is a LUT!)
  reg [9:0]  lower_lut [0:127];
  reg [19:0] upper_lut [0:127]; // each digit +6 biased

  integer li, lt, ld;
  initial begin
    for (li = 0; li < 128; li = li + 1) begin
      lt = li;
      lower_lut[li] = 10'd0;
      ld = lt % 10; lower_lut[li][3:0] = ld[3:0]; lt = lt / 10;
      ld = lt % 10; lower_lut[li][7:4] = ld[3:0]; lt = lt / 10;
      ld = lt % 10; lower_lut[li][9:8] = ld[1:0];
    end
    for (li = 0; li < 128; li = li + 1) begin
      lt = li * 128;
      upper_lut[li] = 20'd0;
      ld = lt % 10; upper_lut[li][3:0]   = ld[3:0] + 4'd6; lt = lt / 10;
      ld = lt % 10; upper_lut[li][7:4]   = ld[3:0] + 4'd6; lt = lt / 10;
      ld = lt % 10; upper_lut[li][11:8]  = ld[3:0] + 4'd6; lt = lt / 10;
      ld = lt % 10; upper_lut[li][15:12] = ld[3:0] + 4'd6; lt = lt / 10;
      ld = lt % 10; upper_lut[li][19:16] = ld[3:0] + 4'd6;
    end
  end

  // --- Pipeline registers ---
  reg [4:1] valid;
  reg [4:1] last;

  reg [19:0] s1_lower;
  reg [19:0] s1_upper_biased;
  reg [19:0] s2_xs6;
  reg [23:0] s3_mantissa;     // 6 XS6 digits
  reg [3:0]  s3_exponent;
  reg [19:0] s3_mask;         // applied to mantissa[23:4] (upper 5 digits)
  // Stage 4 state registers
  reg [23:0] s4_mantissa;     // 6 XS6 digits
  reg [4:0]  s4_exponent;

  reg [4:0]  s4_added;
  reg [7:0]  s5_acc;
  wire [7:0] new_acc;

  localparam IN_BIGGER        = 2'd0;
  localparam ZEROS_AT_K_SAME  = 2'd1;
  localparam BUMP             = 2'd2;
  localparam NON_ZERO         = 2'd3;

  always @(posedge clk) begin : main
    // (these should also be "automatic" but iverilog had issues)
    reg [4:0]  tmp_sum;
    reg        carry;
    reg [4:0]  not_zero;
    reg [19:0] s2_xs6_next;
    int        i;
    // Stage 4 combinationals
    reg [4:0]  sig_mask;        // 1 bit per upper digit: which are compared
    reg        bump_detect;
    reg [4:0]  k_same;
    reg [1:0]  s4_case;
    reg [23:0] new_mantissa;
    reg [4:0]  new_exponent;
    reg [4:0]  new_added;
    // Increment from registered s4_mantissa/s4_exponent (parallel with case logic)
    reg [5:0]  c4_inc_onehot;   // one-hot: which digit gets +1
    reg [23:0] c4_mantissa_inc; // incremented mantissa
    reg [5:0]  c4_inc_touched;  // which digits were modified by increment
    reg        inc_ci, inc_co;
    reg [3:0]  inc_digit;
    // --- Valid/last shift register ---
    valid <= {valid[3:1], i_valid};
    last  <= {last[3:1], i_payload_x_last};

    // --- Stage 1: LUT lookup ---
    s1_lower        <= {10'd0, lower_lut[din[6:0]]};
    s1_upper_biased <= upper_lut[din[13:7]];

    // --- Stage 2: XS6 + BCD → XS6 addition ---
    carry = 1'b0;
    for (i = 0; i < 5; i = i + 1) begin
      tmp_sum = {1'b0, s1_lower[4*i +: 4]}
              + {1'b0, s1_upper_biased[4*i +: 4]}
              + {4'd0, carry};
      carry = tmp_sum[4];
      s2_xs6_next[4*i +: 4] = carry ? (tmp_sum[3:0] + 4'd6) : tmp_sum[3:0];
    end
    s2_xs6 <= s2_xs6_next;

    // --- Stage 3: Normalize ---
    not_zero = 5'd0;
    for (i = 0; i < 5; i = i + 1)
      not_zero[i] = (s2_xs6[4*i +: 4] != 4'h6) ? 1'b1 : 1'b0;

    if (not_zero[4]) begin
      s3_mantissa <= {s2_xs6, 4'h6};
      s3_exponent <= 4'd4;
      s3_mask     <= 20'hFFFFF;
    end else if (not_zero[3]) begin
      s3_mantissa <= {s2_xs6[15:0], 8'h66};
      s3_exponent <= 4'd3;
      s3_mask     <= 20'hFFFF0;
    end else if (not_zero[2]) begin
      s3_mantissa <= {s2_xs6[11:0], 12'h666};
      s3_exponent <= 4'd2;
      s3_mask     <= 20'hFFF00;
    end else if (not_zero[1]) begin
      s3_mantissa <= {s2_xs6[7:0], 16'h6666};
      s3_exponent <= 4'd1;
      s3_mask     <= 20'hFF000;
    end else if (not_zero[0]) begin
      s3_mantissa <= {s2_xs6[3:0], 20'h66666};
      s3_exponent <= 4'd0;
      s3_mask     <= 20'hF0000;
    end else begin
      s3_mantissa <= 24'h666666;
      s3_exponent <= 4'd0;
      s3_mask     <= 20'hF0000;
    end

    // --- Parallel: XS6 increment from registered inputs (no case dependency) ---

    // One-hot increment position: digit (5 - exponent), clamped to digit 0
    c4_inc_onehot = (s4_exponent <= 5'd5) ? (6'b100000 >> s4_exponent) : 6'b000001;

    // XS6 carry-chain adder: add one-hot to mantissa, propagate carry
    inc_ci = 1'b0;
    for (i = 0; i < 6; i = i + 1) begin
      {inc_co, inc_digit} = {1'b0, s4_mantissa[4*i +: 4]} + {4'd0, inc_ci} + {4'd0, c4_inc_onehot[i]};
      c4_mantissa_inc[4*i +: 4] = inc_co ? 4'h6 : inc_digit[3:0];
      c4_inc_touched[i] = inc_ci | c4_inc_onehot[i];
      inc_ci = inc_co;
    end

    // --- Stage 4: Compare against prev, compute added digits ---

    // sig_mask: which upper digits are significant (1 bit per nibble from s3_mask)
    for (i = 0; i < 5; i = i + 1)
      sig_mask[i] = s3_mask[4*i];

    // Bump detection: does increment touch any significant digit?
    bump_detect = |(c4_inc_touched[5:1] & sig_mask);

    k_same = s4_exponent - {1'b0, s3_exponent};

    // Case determination
    if (s4_exponent < {1'b0, s3_exponent}) begin
      s4_case = IN_BIGGER;
    end else if (s4_exponent == {1'b0, s3_exponent}) begin
      if (s3_mantissa[23:4] > s4_mantissa[23:4])
        s4_case = IN_BIGGER;
      else
        s4_case = BUMP;
    end else begin
      if ((s3_mask & s4_mantissa[23:4]) < (s3_mask & s3_mantissa[23:4]))
        s4_case = ZEROS_AT_K_SAME;
      else if ((s3_mask & s4_mantissa[23:4]) == (s3_mask & s3_mantissa[23:4])) begin
        if (bump_detect)
          s4_case = BUMP;
        else
          s4_case = NON_ZERO;
      end else
        s4_case = BUMP;
    end

    // Update logic
    case (s4_case)
      IN_BIGGER: begin
        new_added    = 5'd0;
        new_mantissa = s3_mantissa;
        new_exponent = {1'b0, s3_exponent};
      end
      ZEROS_AT_K_SAME: begin
        new_added    = k_same;
        new_mantissa = s3_mantissa;
        new_exponent = s4_exponent;
      end
      BUMP: begin
        new_added    = k_same + 5'd1;
        new_mantissa = s3_mantissa;
        new_exponent = s4_exponent + 5'd1;
      end
      NON_ZERO: begin
        new_added    = k_same;
        new_exponent = s4_exponent;
        new_mantissa = c4_mantissa_inc;
      end
    endcase

    // --- Register update ---
    if (valid[3] && last[3]) begin
      s4_mantissa <= 24'h666666;
      s4_exponent <= 5'd0;
    end else if (valid[3]) begin
      s4_mantissa <= new_mantissa;
      s4_exponent <= new_exponent;
    end
    s4_added <= new_added;

    // --- Stage 5: Accumulator ---
    if (valid[4]) begin
      if (last[4])
        s5_acc <= 8'd0;
      else
        s5_acc <= new_acc;
    end

    // --- Reset ---
    if (reset) begin
      valid       <= 4'd0;
      s4_mantissa <= 24'h666666;
      s4_exponent <= 5'd0;
      s5_acc      <= 8'd0;
    end
  end

  assign new_acc   = s5_acc + {3'd0, s4_added};
  assign i_ready   = 1'b1;
  assign o_payload = {24'd0, new_acc};
  assign o_valid   = valid[4] & last[4];

endmodule

Generated Verilog

// Append Sort
//
// 5-stage always-ready pipeline using XS6 decimal floating point:
//   Stage 1: Binary-to-XS6 via split LUT (lower 7b BCD + upper 7b XS6)
//   Stage 2: XS6 + BCD -> XS6
//   Stage 3: Normalize (shift leading digit to MSB, record exponent)
//   Stage 4: Compare mantissa/exponent against prev, compute added digits
//   Accumulator: sum of added digits, output on last
//
// Mantissa is 24-bit XS6 (6 nibbles, digit+6 encoding: 0-9 → 6-15).
// Increment uses one-hot addition with sequential carry chain.
// Bump detection: if increment carry touches any significant (compared) digit.

// AI Assisted.
// 
// This solution was partially assisted by agentic AI tools.  I wrote the
// original code as bcd-float and didn’t consider all corner cases.  I had the
// agent convert the code to verilog (I tend to use VHDL for problems where I
// have function-generated lookup tables) and worked with it to fix the issue,
// which added the float increment operation.  I’m still not happy about that,
// but can’t think of a way to avoid it.  There was a lot of design iterations.
// It’s possible this solution could be further optimized.  
// 
// This design is fairly esoteric, since I wanted to avoid backpressure.  My
// main focus was on the data hazard in stage 4.  In order to get this path
// short, I used base 10 float, since it aligns leading digits for the
// comparisons, and also has the number of digits (exponent) as part of the
// format.
// 
// This was later changed to xs6 encoding vs bcd encoding.  Xs6 is just bcd+6.
// It allows bcd constants to be added and make use of a normal carry chain.
// With a fixup at the end.  This removes the compare-to-10’s from the bcd carry
// chain.  It is efficient to do xs6+bcd -> bcd as well as xs6+bcd -> xs6.
// 
// Warning 
// 
// this design does assume a limited number of inputs vs a max accumulator size.
// with 5 digit inputs and only 15 inputs, there’s no need to track the 7th+
// digit.  It won’t ever be able to affect anything.  If the design changes to
// unrestricted numbers of inputs with a simple cap on internal accumulator
// width this design can fail.
// 
// Suggestions
// 
// It might be better to use concepts from carry-lookahead.  Where info about
// the increment carry chain is pre-computed at the end of stage 4.  I was
// unsure if this would make things faster or slower.  Concepts from
// carry-select are also possible.  The xs6 increment can be used to compute
// digit+1 and digit+7 in parallel, potentially allowing a small mux based on
// carry in/out of each xs6 digit.
// 
// The agentic AI used 7-series in yosys for the timing estimates.  Because I
// was too lazy to download or set up something more relevant.  So there may be
// easy optimizations that I missed, or code styles that work better.
// 
// I’m much less interested in the competitive aspects, so feel free to clone
// and own this code.  Not sure on the ethics of that in terms of competition?

module Solution (
  input  wire        clk,
  input  wire        reset,
  output wire        i_ready,
  input  wire        i_valid,
  input  wire [13:0] i_payload_x_fragment,
  input  wire        i_payload_x_last,
  output wire [31:0] o_payload,
  output wire        o_valid
);

  wire [13:0] din = i_payload_x_fragment; // alias

  // --- LUTs for binary-to-BCD conversion ---
  // (I really hope the tools know this is a LUT!)
  reg [9:0]  lower_lut [0:127];
  reg [19:0] upper_lut [0:127]; // each digit +6 biased

  integer li, lt, ld;
  initial begin
    for (li = 0; li < 128; li = li + 1) begin
      lt = li;
      lower_lut[li] = 10'd0;
      ld = lt % 10; lower_lut[li][3:0] = ld[3:0]; lt = lt / 10;
      ld = lt % 10; lower_lut[li][7:4] = ld[3:0]; lt = lt / 10;
      ld = lt % 10; lower_lut[li][9:8] = ld[1:0];
    end
    for (li = 0; li < 128; li = li + 1) begin
      lt = li * 128;
      upper_lut[li] = 20'd0;
      ld = lt % 10; upper_lut[li][3:0]   = ld[3:0] + 4'd6; lt = lt / 10;
      ld = lt % 10; upper_lut[li][7:4]   = ld[3:0] + 4'd6; lt = lt / 10;
      ld = lt % 10; upper_lut[li][11:8]  = ld[3:0] + 4'd6; lt = lt / 10;
      ld = lt % 10; upper_lut[li][15:12] = ld[3:0] + 4'd6; lt = lt / 10;
      ld = lt % 10; upper_lut[li][19:16] = ld[3:0] + 4'd6;
    end
  end

  // --- Pipeline registers ---
  reg [4:1] valid;
  reg [4:1] last;

  reg [19:0] s1_lower;
  reg [19:0] s1_upper_biased;
  reg [19:0] s2_xs6;
  reg [23:0] s3_mantissa;     // 6 XS6 digits
  reg [3:0]  s3_exponent;
  reg [19:0] s3_mask;         // applied to mantissa[23:4] (upper 5 digits)
  // Stage 4 state registers
  reg [23:0] s4_mantissa;     // 6 XS6 digits
  reg [4:0]  s4_exponent;

  reg [4:0]  s4_added;
  reg [7:0]  s5_acc;
  wire [7:0] new_acc;

  localparam IN_BIGGER        = 2'd0;
  localparam ZEROS_AT_K_SAME  = 2'd1;
  localparam BUMP             = 2'd2;
  localparam NON_ZERO         = 2'd3;

  always @(posedge clk) begin : main
    // (these should also be "automatic" but iverilog had issues)
    reg [4:0]  tmp_sum;
    reg        carry;
    reg [4:0]  not_zero;
    reg [19:0] s2_xs6_next;
    int        i;
    // Stage 4 combinationals
    reg [4:0]  sig_mask;        // 1 bit per upper digit: which are compared
    reg        bump_detect;
    reg [4:0]  k_same;
    reg [1:0]  s4_case;
    reg [23:0] new_mantissa;
    reg [4:0]  new_exponent;
    reg [4:0]  new_added;
    // Increment from registered s4_mantissa/s4_exponent (parallel with case logic)
    reg [5:0]  c4_inc_onehot;   // one-hot: which digit gets +1
    reg [23:0] c4_mantissa_inc; // incremented mantissa
    reg [5:0]  c4_inc_touched;  // which digits were modified by increment
    reg        inc_ci, inc_co;
    reg [3:0]  inc_digit;
    // --- Valid/last shift register ---
    valid <= {valid[3:1], i_valid};
    last  <= {last[3:1], i_payload_x_last};

    // --- Stage 1: LUT lookup ---
    s1_lower        <= {10'd0, lower_lut[din[6:0]]};
    s1_upper_biased <= upper_lut[din[13:7]];

    // --- Stage 2: XS6 + BCD → XS6 addition ---
    carry = 1'b0;
    for (i = 0; i < 5; i = i + 1) begin
      tmp_sum = {1'b0, s1_lower[4*i +: 4]}
              + {1'b0, s1_upper_biased[4*i +: 4]}
              + {4'd0, carry};
      carry = tmp_sum[4];
      s2_xs6_next[4*i +: 4] = carry ? (tmp_sum[3:0] + 4'd6) : tmp_sum[3:0];
    end
    s2_xs6 <= s2_xs6_next;

    // --- Stage 3: Normalize ---
    not_zero = 5'd0;
    for (i = 0; i < 5; i = i + 1)
      not_zero[i] = (s2_xs6[4*i +: 4] != 4'h6) ? 1'b1 : 1'b0;

    if (not_zero[4]) begin
      s3_mantissa <= {s2_xs6, 4'h6};
      s3_exponent <= 4'd4;
      s3_mask     <= 20'hFFFFF;
    end else if (not_zero[3]) begin
      s3_mantissa <= {s2_xs6[15:0], 8'h66};
      s3_exponent <= 4'd3;
      s3_mask     <= 20'hFFFF0;
    end else if (not_zero[2]) begin
      s3_mantissa <= {s2_xs6[11:0], 12'h666};
      s3_exponent <= 4'd2;
      s3_mask     <= 20'hFFF00;
    end else if (not_zero[1]) begin
      s3_mantissa <= {s2_xs6[7:0], 16'h6666};
      s3_exponent <= 4'd1;
      s3_mask     <= 20'hFF000;
    end else if (not_zero[0]) begin
      s3_mantissa <= {s2_xs6[3:0], 20'h66666};
      s3_exponent <= 4'd0;
      s3_mask     <= 20'hF0000;
    end else begin
      s3_mantissa <= 24'h666666;
      s3_exponent <= 4'd0;
      s3_mask     <= 20'hF0000;
    end

    // --- Parallel: XS6 increment from registered inputs (no case dependency) ---

    // One-hot increment position: digit (5 - exponent), clamped to digit 0
    c4_inc_onehot = (s4_exponent <= 5'd5) ? (6'b100000 >> s4_exponent) : 6'b000001;

    // XS6 carry-chain adder: add one-hot to mantissa, propagate carry
    inc_ci = 1'b0;
    for (i = 0; i < 6; i = i + 1) begin
      {inc_co, inc_digit} = {1'b0, s4_mantissa[4*i +: 4]} + {4'd0, inc_ci} + {4'd0, c4_inc_onehot[i]};
      c4_mantissa_inc[4*i +: 4] = inc_co ? 4'h6 : inc_digit[3:0];
      c4_inc_touched[i] = inc_ci | c4_inc_onehot[i];
      inc_ci = inc_co;
    end

    // --- Stage 4: Compare against prev, compute added digits ---

    // sig_mask: which upper digits are significant (1 bit per nibble from s3_mask)
    for (i = 0; i < 5; i = i + 1)
      sig_mask[i] = s3_mask[4*i];

    // Bump detection: does increment touch any significant digit?
    bump_detect = |(c4_inc_touched[5:1] & sig_mask);

    k_same = s4_exponent - {1'b0, s3_exponent};

    // Case determination
    if (s4_exponent < {1'b0, s3_exponent}) begin
      s4_case = IN_BIGGER;
    end else if (s4_exponent == {1'b0, s3_exponent}) begin
      if (s3_mantissa[23:4] > s4_mantissa[23:4])
        s4_case = IN_BIGGER;
      else
        s4_case = BUMP;
    end else begin
      if ((s3_mask & s4_mantissa[23:4]) < (s3_mask & s3_mantissa[23:4]))
        s4_case = ZEROS_AT_K_SAME;
      else if ((s3_mask & s4_mantissa[23:4]) == (s3_mask & s3_mantissa[23:4])) begin
        if (bump_detect)
          s4_case = BUMP;
        else
          s4_case = NON_ZERO;
      end else
        s4_case = BUMP;
    end

    // Update logic
    case (s4_case)
      IN_BIGGER: begin
        new_added    = 5'd0;
        new_mantissa = s3_mantissa;
        new_exponent = {1'b0, s3_exponent};
      end
      ZEROS_AT_K_SAME: begin
        new_added    = k_same;
        new_mantissa = s3_mantissa;
        new_exponent = s4_exponent;
      end
      BUMP: begin
        new_added    = k_same + 5'd1;
        new_mantissa = s3_mantissa;
        new_exponent = s4_exponent + 5'd1;
      end
      NON_ZERO: begin
        new_added    = k_same;
        new_exponent = s4_exponent;
        new_mantissa = c4_mantissa_inc;
      end
    endcase

    // --- Register update ---
    if (valid[3] && last[3]) begin
      s4_mantissa <= 24'h666666;
      s4_exponent <= 5'd0;
    end else if (valid[3]) begin
      s4_mantissa <= new_mantissa;
      s4_exponent <= new_exponent;
    end
    s4_added <= new_added;

    // --- Stage 5: Accumulator ---
    if (valid[4]) begin
      if (last[4])
        s5_acc <= 8'd0;
      else
        s5_acc <= new_acc;
    end

    // --- Reset ---
    if (reset) begin
      valid       <= 4'd0;
      s4_mantissa <= 24'h666666;
      s4_exponent <= 5'd0;
      s5_acc      <= 8'd0;
    end
  end

  assign new_acc   = s5_acc + {3'd0, s4_added};
  assign i_ready   = 1'b1;
  assign o_payload = {24'd0, new_acc};
  assign o_valid   = valid[4] & last[4];

endmodule

Timing Analysis

Path 1-7.725 ns

From: s4_exponent[1]$_SDFFE_PP0P_/Q

To: s4_exponent[4]$_SDFFE_PP0P_/D

Data Arrival: 7.540 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`s4_exponent[1]$_SDFFE_PP0P_/CLK`
0.932	sky130_fd_sc_hvl__dfxtp_1	`s4_exponent[1]$_SDFFE_PP0P_/Q`
0.932	sky130_fd_sc_hvl__nor2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12792/A`
1.245	sky130_fd_sc_hvl__nor2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12792/Y`
1.245	sky130_fd_sc_hvl__and3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12793/C`
1.666	sky130_fd_sc_hvl__and3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12793/X`
1.666	sky130_fd_sc_hvl__xnor2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12801/B`
1.926	sky130_fd_sc_hvl__xnor2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12801/Y`
1.926	sky130_fd_sc_hvl__o21ai_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12802/A2`
2.318	sky130_fd_sc_hvl__o21ai_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12802/Y`
2.318	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12803/C`
2.781	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12803/Y`
2.781	sky130_fd_sc_hvl__nor3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12806/B`
3.199	sky130_fd_sc_hvl__nor3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12806/Y`
3.199	sky130_fd_sc_hvl__o21a_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12807/A2`
3.546	sky130_fd_sc_hvl__o21a_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12807/X`
3.546	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12810/C`
3.858	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12810/Y`
3.858	sky130_fd_sc_hvl__o21ai_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12813/A1`
4.189	sky130_fd_sc_hvl__o21ai_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12813/Y`
4.189	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12815/C`
4.644	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12815/Y`
4.644	sky130_fd_sc_hvl__nor3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12818/B`
5.061	sky130_fd_sc_hvl__nor3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12818/Y`
5.061	sky130_fd_sc_hvl__o21a_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12819/A2`
5.451	sky130_fd_sc_hvl__o21a_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12819/X`
5.451	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12820/C`
5.780	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12820/Y`
5.780	sky130_fd_sc_hvl__a22oi_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12837/B1`
6.062	sky130_fd_sc_hvl__a22oi_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12837/Y`
6.062	sky130_fd_sc_hvl__o21ai_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$13483/A1`
6.639	sky130_fd_sc_hvl__o21ai_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$13483/Y`
6.639	sky130_fd_sc_hvl__nor3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$13498/B`
7.159	sky130_fd_sc_hvl__nor3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$13498/Y`
7.159	sky130_fd_sc_hvl__xnor2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$13500/B`
7.460	sky130_fd_sc_hvl__xnor2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$13500/Y`
7.460	sky130_fd_sc_hvl__nor2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$13501/B`
7.540	sky130_fd_sc_hvl__nor2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$13501/Y`
7.540	sky130_fd_sc_hvl__dfxtp_1	`s4_exponent[4]$_SDFFE_PP0P_/D`

Path 2-7.706 ns

From: s4_exponent[1]$_SDFFE_PP0P_/Q

To: s4_exponent[1]$_SDFFE_PP0P_/D

Data Arrival: 7.477 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`s4_exponent[1]$_SDFFE_PP0P_/CLK`
0.932	sky130_fd_sc_hvl__dfxtp_1	`s4_exponent[1]$_SDFFE_PP0P_/Q`
0.932	sky130_fd_sc_hvl__nor2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12792/A`
1.245	sky130_fd_sc_hvl__nor2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12792/Y`
1.245	sky130_fd_sc_hvl__and3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12793/C`
1.666	sky130_fd_sc_hvl__and3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12793/X`
1.666	sky130_fd_sc_hvl__xnor2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12801/B`
1.926	sky130_fd_sc_hvl__xnor2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12801/Y`
1.926	sky130_fd_sc_hvl__o21ai_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12802/A2`
2.318	sky130_fd_sc_hvl__o21ai_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12802/Y`
2.318	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12803/C`
2.781	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12803/Y`
2.781	sky130_fd_sc_hvl__nor3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12806/B`
3.199	sky130_fd_sc_hvl__nor3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12806/Y`
3.199	sky130_fd_sc_hvl__o21a_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12807/A2`
3.546	sky130_fd_sc_hvl__o21a_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12807/X`
3.546	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12810/C`
3.858	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12810/Y`
3.858	sky130_fd_sc_hvl__o21ai_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12813/A1`
4.189	sky130_fd_sc_hvl__o21ai_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12813/Y`
4.189	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12815/C`
4.644	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12815/Y`
4.644	sky130_fd_sc_hvl__nor3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12818/B`
5.061	sky130_fd_sc_hvl__nor3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12818/Y`
5.061	sky130_fd_sc_hvl__o21a_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12819/A2`
5.451	sky130_fd_sc_hvl__o21a_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12819/X`
5.451	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12820/C`
5.780	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12820/Y`
5.780	sky130_fd_sc_hvl__a22oi_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12837/B1`
6.062	sky130_fd_sc_hvl__a22oi_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12837/Y`
6.062	sky130_fd_sc_hvl__and2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12865/A`
6.586	sky130_fd_sc_hvl__and2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12865/X`
6.586	sky130_fd_sc_hvl__mux2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$13488/S`
7.189	sky130_fd_sc_hvl__mux2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$13488/X`
7.189	sky130_fd_sc_hvl__o21ai_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$13489/A2`
7.387	sky130_fd_sc_hvl__o21ai_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$13489/Y`
7.387	sky130_fd_sc_hvl__a21oi_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$13490/B1`
7.477	sky130_fd_sc_hvl__a21oi_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$13490/Y`
7.477	sky130_fd_sc_hvl__dfxtp_1	`s4_exponent[1]$_SDFFE_PP0P_/D`

Path 3-7.706 ns

From: s4_exponent[1]$_SDFFE_PP0P_/Q

To: s4_exponent[2]$_SDFFE_PP0P_/D

Data Arrival: 7.477 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`s4_exponent[1]$_SDFFE_PP0P_/CLK`
0.932	sky130_fd_sc_hvl__dfxtp_1	`s4_exponent[1]$_SDFFE_PP0P_/Q`
0.932	sky130_fd_sc_hvl__nor2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12792/A`
1.245	sky130_fd_sc_hvl__nor2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12792/Y`
1.245	sky130_fd_sc_hvl__and3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12793/C`
1.666	sky130_fd_sc_hvl__and3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12793/X`
1.666	sky130_fd_sc_hvl__xnor2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12801/B`
1.926	sky130_fd_sc_hvl__xnor2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12801/Y`
1.926	sky130_fd_sc_hvl__o21ai_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12802/A2`
2.318	sky130_fd_sc_hvl__o21ai_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12802/Y`
2.318	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12803/C`
2.781	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12803/Y`
2.781	sky130_fd_sc_hvl__nor3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12806/B`
3.199	sky130_fd_sc_hvl__nor3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12806/Y`
3.199	sky130_fd_sc_hvl__o21a_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12807/A2`
3.546	sky130_fd_sc_hvl__o21a_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12807/X`
3.546	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12810/C`
3.858	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12810/Y`
3.858	sky130_fd_sc_hvl__o21ai_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12813/A1`
4.189	sky130_fd_sc_hvl__o21ai_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12813/Y`
4.189	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12815/C`
4.644	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12815/Y`
4.644	sky130_fd_sc_hvl__nor3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12818/B`
5.061	sky130_fd_sc_hvl__nor3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12818/Y`
5.061	sky130_fd_sc_hvl__o21a_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12819/A2`
5.451	sky130_fd_sc_hvl__o21a_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12819/X`
5.451	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12820/C`
5.780	sky130_fd_sc_hvl__nand3_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12820/Y`
5.780	sky130_fd_sc_hvl__a22oi_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12837/B1`
6.062	sky130_fd_sc_hvl__a22oi_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12837/Y`
6.062	sky130_fd_sc_hvl__and2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12865/A`
6.586	sky130_fd_sc_hvl__and2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$12865/X`
6.586	sky130_fd_sc_hvl__mux2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$13493/S`
7.189	sky130_fd_sc_hvl__mux2_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$13493/X`
7.189	sky130_fd_sc_hvl__o21ai_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$13494/A2`
7.387	sky130_fd_sc_hvl__o21ai_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$13494/Y`
7.387	sky130_fd_sc_hvl__a21oi_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$13495/B1`
7.477	sky130_fd_sc_hvl__a21oi_1	`$abc$12603$auto$blifparse.cc:396:parse_blif$13495/Y`
7.477	sky130_fd_sc_hvl__dfxtp_1	`s4_exponent[2]$_SDFFE_PP0P_/D`

Post-Synthesis Verilog

Download synth.v