Parallel Prefix Sum

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Submission #2

PASSED

RankingPercentile

Latency

153.95 (32 cycles)ns

3rd

top 67%

Throughput

207.86 (100.0%)MHz

3rd

top 67%

Area

8125μm²

4th

top 100%

Score

92.51

3rd

top 67%

Submitted Solution

// PipelineC solution template.
#include "uintN_t.h"
#include "intN_t.h"
#include "stream/stream.h"

// Input stream interface:
//   input.valid (input): Asserted when input data is valid
//   input.data.* (input): Input payload fields
//   input_ready (output): Assert when ready to accept input
//
// Output flow interface (no backpressure):
//   output.valid (output): Assert when output data is valid
//   output.data.* (output): Output payload fields

typedef struct input_payload_t {
  uint16_t array_fragment;
  uint1_t array_last;
} input_payload_t;
DECL_STREAM_TYPE(input_payload_t)

typedef struct output_payload_t {
  uint24_t fragment;
  uint1_t last;
} output_payload_t;
DECL_STREAM_TYPE(output_payload_t)

DECL_INPUT(stream(input_payload_t), input)
DECL_OUTPUT(uint1_t, input_ready)

DECL_OUTPUT(stream(output_payload_t), output)

#define CLK_RATE_MHZ 0.001
DECL_INPUT(uint1_t, clk)
CLK_MHZ(clk, CLK_RATE_MHZ)
MAIN_MHZ(solution, CLK_RATE_MHZ)
void solution()
{
  // Your implementation here
  static uint24_t acc = 0;
  
  input_ready = 1;
  
  if (input.valid) {
    output.data.last = input.data.array_last;
    acc += input.data.array_fragment;
    output.data.fragment = acc;
    if (input.data.array_last) {
      acc = 0;
    }
    output.valid = 1;
  }
}

Compile Log

/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/C_TO_LOGIC.py:7114: SyntaxWarning: invalid escape sequence '\/'
  
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/C_TO_LOGIC.py:7485: SyntaxWarning: invalid escape sequence '\d'
  )
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/C_TO_LOGIC.py:10680: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + "_WRITE" + f"\s?\("
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/C_TO_LOGIC.py:10680: SyntaxWarning: invalid escape sequence '\s'
  r = f"\w+" + "_WRITE" + f"\s?\("
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/C_TO_LOGIC.py:10682: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + "_WRITE_[0-9]+" + f"\s?\("
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/C_TO_LOGIC.py:10682: SyntaxWarning: invalid escape sequence '\s'
  r = f"\w+" + "_WRITE_[0-9]+" + f"\s?\("
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/C_TO_LOGIC.py:10688: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + "_READ" + f"\s?\("
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/C_TO_LOGIC.py:10688: SyntaxWarning: invalid escape sequence '\s'
  r = f"\w+" + "_READ" + f"\s?\("
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/C_TO_LOGIC.py:10690: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + "_READ_[0-9]+" + f"\s?\("
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/C_TO_LOGIC.py:10690: SyntaxWarning: invalid escape sequence '\s'
  r = f"\w+" + "_READ_[0-9]+" + f"\s?\("
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:272: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_SINGLE_INST.h"
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:348: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_array(_[0-9]+)+_t"
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:374: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_array_N_t.h"
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:404: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_bytes_t.h"
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:434: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + C_TO_FSM.FSM_EXT + ".h"
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:526: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + C_TO_FSM.FSM_EXT
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:598: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_bytes_t"
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:652: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_bytes_t"
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:1469: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_array_[0-9]+_t"
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:1902: SyntaxWarning: invalid escape sequence '\s'
  for type_regex in [f"uint[0-9]+_negate\s?\("]:  # DO int,float negate?
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:1963: SyntaxWarning: invalid escape sequence '\s'
  for type_regex in [f"int[0-9]+_abs\s?\("]:  # Float abs is bit manip func
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:2049: SyntaxWarning: invalid escape sequence '\w'
  for type_regex in [f"\w+_mux[0-9]+\s?\("]:
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:2245: SyntaxWarning: invalid escape sequence '\s'
  for type_regex in [f"count0s_uint[0-9]+\s?\("]:
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:2474: SyntaxWarning: invalid escape sequence '\s'
  regex = type_regex + "_" + op_regex + f"[0-9]+\s?\("
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:2841: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_[0-9]+_[0-9]+\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:2877: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"u?int[0-9]+_u?int[0-9]+\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:2915: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"[^_][u?]int[0-9]+_[0-9]+\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:2955: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"[^_]rotl[0-9]+_[0-9]+\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:2988: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"[^_]rotr[0-9]+_[0-9]+\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:3023: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"u?int[0-9]+_uint[0-9]+_[0-9]+\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:3064: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_uint[0-9]+_uint[0-9]+\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:3110: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_uint[0-9]+\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:3147: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_abs\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:3183: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_sign\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:3215: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"bswap_[0-9]+\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:3249: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"uint[0-9]+_array[0-9]+_(?:be|le)\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SYN.py:1183: SyntaxWarning: invalid escape sequence '\/'
  

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Output directory: /submission/user/pipelinec_output
================== Parsing C Code to Logical Hierarchy ================================
Parsing: /submission/user/Solution.c
Preprocessing file...
Parsing C syntax...
Parsing non-function definitions...
Parsing derived fsm logic functions...
Doing old-style code generation based on PipelineC supported text patterns...
Elaborating function dataflow...
Defaulting to pyrtl based timing estimates...
Using PYRTL synthesizing for part: None
Elaborating dataflow of function: solution
Elaborating user function hierarchies down to raw HDL logic...
Doing obvious logic trimming/collapsing...
Writing generated PipelineC code from elaboration to output directories...
Writing cache of parsed information to file...
================== Writing Resulting Logic to File ================================
Writing output files before adding pipelining...
Writing log of integer module instances: /submission/user/pipelinec_output/integer_module_instances.log
Writing VHDL files for all functions (before any added pipelining)...
Writing multi main top level files...
Writing the constant struct+enum definitions as defined from C code...
Writing global wire definitions as parsed from C code...
================== Adding Timing Information from Synthesis Tool ================================
Synthesizing before pipelining to get path delays...

Synthesizing function: solution
Function 1/1, elapsed time 0:00:03.051105...
...Waiting on synthesis for: solution
Running: /submission/user/pipelinec_output/solution/pyrtl_0CLK_23eb2db7.log
solution FMAX: 78.740 MHz (12.700 ns path delay)
================== Beginning Throughput Sweep ================================
Function: solution Target MHz: 0.001
Starting with no added pipelining...
Starting with blank sweep state...
Starting middle out sweep...
Starting from timing params without added pipelining...
Collecting modules to pipeline...
Pipelining modules...
Updating output files...
Estimated register usage: /submission/user/pipelinec_output/solution/solution_9a89_registers.log
Running syn w timing params...
Elapsed time: 0:00:04.524859...
Running: /submission/user/pipelinec_output/solution/pyrtl_9a89.log
solution Clock Goal: 0.00 (MHz) Current: 78.17 (MHz)(12.79 ns) 0 clks
Met timing...
================== Writing Results of Throughput Sweep ================================
Output VHDL files: /submission/user/pipelinec_output/vhdl_files.txt
Done.

Generated Verilog

module Solution(
    input clk,
    input reset,
    input i_valid,
    output i_ready,
    input [15:0] i_payload_array_fragment,
    input i_payload_array_last,
    output o_valid,
    output [23:0] o_payload_fragment,
    output o_payload_last
);

    wire [16:0] input_data;
    assign input_data = { i_payload_array_last, i_payload_array_fragment };

    wire [24:0] output_data;
    wire output_valid;
    wire output_input_ready;

    solution inner(
        .clk(clk),
        .\input[data] (input_data),
        .\input[valid] (i_valid),
        .\output[data] (output_data),
        .\output[valid] (output_valid),
        .input_ready(output_input_ready)
    );

    assign i_ready = output_input_ready;
    assign o_valid = output_valid;
    assign o_payload_fragment = output_data[23:0];
    assign o_payload_last = output_data[24:24];

endmodule


/* Generated by Yosys 0.55 (git sha1 60f126cd00c94892782470192d6c9f7abebe7c05, g++ 14.3.0 -fPIC -O3) */

module bin_op_plus_uint24_t_uint16_t_0clk_de264c78(left, right, return_output);
  wire [24:0] _0_;
  wire [211:0] \:141.read_pipe ;
  input [23:0] left;
  wire [23:0] left;
  output [24:0] return_output;
  wire [24:0] return_output;
  input [15:0] right;
  wire [15:0] right;
  assign _0_ = { 1'h0, left } + { 9'h000, right };
  assign \:141.read_pipe  = { left, right, 172'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx };
  assign return_output = _0_;
endmodule

module mux_uint1_t_output_payload_t_stream_t_output_payload_t_stream_t_0clk_de264c78(cond, \iftrue[data] , \iftrue[valid] , \iffalse[data] , \iffalse[valid] , \return_output[data] , \return_output[valid] );
  wire _0_;
  wire [25:0] _1_;
  wire [78:0] \:97.read_pipe ;
  input cond;
  wire cond;
  input [24:0] \iffalse[data] ;
  wire [24:0] \iffalse[data] ;
  input \iffalse[valid] ;
  wire \iffalse[valid] ;
  input [24:0] \iftrue[data] ;
  wire [24:0] \iftrue[data] ;
  input \iftrue[valid] ;
  wire \iftrue[valid] ;
  output [24:0] \return_output[data] ;
  wire [24:0] \return_output[data] ;
  output \return_output[valid] ;
  wire \return_output[valid] ;
  assign _0_ = cond == 1'h1;
  assign _1_ = _0_ ? { \iftrue[valid] , \iftrue[data]  } : { \iffalse[valid] , \iffalse[data]  };
  assign \:97.read_pipe  = { \iffalse[valid] , \iffalse[data] , \iftrue[valid] , \iftrue[data] , cond, 26'hxxxxxxx };
  assign \return_output[data]  = _1_[24:0];
  assign \return_output[valid]  = _1_[25];
endmodule

module mux_uint1_t_uint24_t_uint24_t_0clk_de264c78(cond, iftrue, iffalse, return_output);
  wire _0_;
  wire [23:0] _1_;
  wire [72:0] \:119.read_pipe ;
  input cond;
  wire cond;
  input [23:0] iffalse;
  wire [23:0] iffalse;
  input [23:0] iftrue;
  wire [23:0] iftrue;
  output [23:0] return_output;
  wire [23:0] return_output;
  assign _0_ = cond == 1'h1;
  assign _1_ = _0_ ? iftrue : iffalse;
  assign \:119.read_pipe  = { iffalse, iftrue, cond, 24'hxxxxxx };
  assign return_output = _1_;
endmodule

module solution(\input[data] , \input[valid] , clk, input_ready, \output[data] , \output[valid] );
  wire [25:0] _0_;
  wire _1_;
  input clk;
  wire clk;
  (* dont_touch = "true" *)
  (* keep = "true" *)
  (* syn_keep = 1'h1 *)
  wire clk_1p0khz;
  wire [17:0] global_to_module;
  input [16:0] \input[data] ;
  wire [16:0] \input[data] ;
  input \input[valid] ;
  wire \input[valid] ;
  output input_ready;
  wire input_ready;
  wire [26:0] module_to_global;
  output [24:0] \output[data] ;
  wire [24:0] \output[data] ;
  output \output[valid] ;
  wire \output[valid] ;
  solution_0clk_23eb2db7 solution_0clk_23eb2db7 (
    .clk(clk_1p0khz),
    .clock_enable(1'h1),
    .\global_to_module[input] (global_to_module),
    .\module_to_global[input_ready] (_1_),
    .\module_to_global[output] (_0_)
  );
  assign clk_1p0khz = clk;
  assign module_to_global = { _1_, _0_ };
  assign global_to_module = { \input[valid] , \input[data]  };
  assign input_ready = module_to_global[26];
  assign \output[data]  = module_to_global[24:0];
  assign \output[valid]  = module_to_global[25];
endmodule

module solution_0clk_23eb2db7(clk, clock_enable, \global_to_module[input] , \module_to_global[output] , \module_to_global[input_ready] );
  wire [23:0] _00_;
  reg [23:0] _01_ = 24'h000000;
  wire [25:0] _02_;
  reg [25:0] _03_ = 26'h0000000;
  wire [24:0] _04_;
  wire _05_;
  wire [23:0] _06_;
  wire [24:0] _07_;
  wire [23:0] _08_;
  wire _09_;
  wire [25:0] _10_;
  wire [23:0] acc;
  wire acc_mux_solution_c_l43_c3_e456_cond;
  wire [23:0] acc_mux_solution_c_l43_c3_e456_iffalse;
  wire [23:0] acc_mux_solution_c_l43_c3_e456_iftrue;
  wire [23:0] acc_mux_solution_c_l43_c3_e456_return_output;
  wire acc_mux_solution_c_l47_c5_7e4d_cond;
  wire [23:0] acc_mux_solution_c_l47_c5_7e4d_iffalse;
  wire [23:0] acc_mux_solution_c_l47_c5_7e4d_iftrue;
  wire [23:0] acc_mux_solution_c_l47_c5_7e4d_return_output;
  wire [23:0] bin_op_plus_solution_c_l45_c5_85e9_left;
  wire [24:0] bin_op_plus_solution_c_l45_c5_85e9_return_output;
  wire [15:0] bin_op_plus_solution_c_l45_c5_85e9_right;
  input clk;
  wire clk;
  wire clk_en_internal;
  input clock_enable;
  wire clock_enable;
  input [17:0] \global_to_module[input] ;
  wire [17:0] \global_to_module[input] ;
  output \module_to_global[input_ready] ;
  wire \module_to_global[input_ready] ;
  output [25:0] \module_to_global[output] ;
  wire [25:0] \module_to_global[output] ;
  wire [25:0] \output ;
  wire output_mux_solution_c_l43_c3_e456_cond;
  wire [25:0] output_mux_solution_c_l43_c3_e456_iffalse;
  wire [25:0] output_mux_solution_c_l43_c3_e456_iftrue;
  wire [25:0] output_mux_solution_c_l43_c3_e456_return_output;
  wire [23:0] reg_comb_acc;
  wire [25:0] reg_comb_output;
  assign _09_ = clk_en_internal ? 1'h1 : 1'h0;
  assign _10_ = clk_en_internal ? reg_comb_output : \output ;
  assign _00_ = clk_en_internal ? reg_comb_acc : acc;
  always @(posedge clk)
    _01_ <= _00_;
  assign _02_ = clk_en_internal ? reg_comb_output : \output ;
  always @(posedge clk)
    _03_ <= _02_;
  mux_uint1_t_uint24_t_uint24_t_0clk_de264c78 acc_mux_solution_c_l43_c3_e456 (
    .cond(acc_mux_solution_c_l43_c3_e456_cond),
    .iffalse(acc_mux_solution_c_l43_c3_e456_iffalse),
    .iftrue(acc_mux_solution_c_l43_c3_e456_iftrue),
    .return_output(_06_)
  );
  mux_uint1_t_uint24_t_uint24_t_0clk_de264c78 acc_mux_solution_c_l47_c5_7e4d (
    .cond(acc_mux_solution_c_l47_c5_7e4d_cond),
    .iffalse(acc_mux_solution_c_l47_c5_7e4d_iffalse),
    .iftrue(acc_mux_solution_c_l47_c5_7e4d_iftrue),
    .return_output(_08_)
  );
  bin_op_plus_uint24_t_uint16_t_0clk_de264c78 bin_op_plus_solution_c_l45_c5_85e9 (
    .left(bin_op_plus_solution_c_l45_c5_85e9_left),
    .return_output(_07_),
    .right(bin_op_plus_solution_c_l45_c5_85e9_right)
  );
  mux_uint1_t_output_payload_t_stream_t_output_payload_t_stream_t_0clk_de264c78 output_mux_solution_c_l43_c3_e456 (
    .cond(output_mux_solution_c_l43_c3_e456_cond),
    .\iffalse[data] (output_mux_solution_c_l43_c3_e456_iffalse[24:0]),
    .\iffalse[valid] (output_mux_solution_c_l43_c3_e456_iffalse[25]),
    .\iftrue[data] (output_mux_solution_c_l43_c3_e456_iftrue[24:0]),
    .\iftrue[valid] (output_mux_solution_c_l43_c3_e456_iftrue[25]),
    .\return_output[data] (_04_),
    .\return_output[valid] (_05_)
  );
  assign acc = _01_;
  assign \output  = _03_;
  assign reg_comb_acc = acc_mux_solution_c_l43_c3_e456_return_output;
  assign reg_comb_output = output_mux_solution_c_l43_c3_e456_return_output;
  assign clk_en_internal = clock_enable;
  assign output_mux_solution_c_l43_c3_e456_cond = \global_to_module[input] [17];
  assign output_mux_solution_c_l43_c3_e456_iftrue = { 1'h1, \global_to_module[input] [16], bin_op_plus_solution_c_l45_c5_85e9_return_output[23:0] };
  assign output_mux_solution_c_l43_c3_e456_iffalse = \output ;
  assign output_mux_solution_c_l43_c3_e456_return_output = { _05_, _04_ };
  assign acc_mux_solution_c_l43_c3_e456_cond = \global_to_module[input] [17];
  assign acc_mux_solution_c_l43_c3_e456_iftrue = acc_mux_solution_c_l47_c5_7e4d_return_output;
  assign acc_mux_solution_c_l43_c3_e456_iffalse = acc;
  assign acc_mux_solution_c_l43_c3_e456_return_output = _06_;
  assign bin_op_plus_solution_c_l45_c5_85e9_left = acc;
  assign bin_op_plus_solution_c_l45_c5_85e9_right = \global_to_module[input] [15:0];
  assign bin_op_plus_solution_c_l45_c5_85e9_return_output = _07_;
  assign acc_mux_solution_c_l47_c5_7e4d_cond = \global_to_module[input] [16];
  assign acc_mux_solution_c_l47_c5_7e4d_iftrue = 24'h000000;
  assign acc_mux_solution_c_l47_c5_7e4d_iffalse = bin_op_plus_solution_c_l45_c5_85e9_return_output[23:0];
  assign acc_mux_solution_c_l47_c5_7e4d_return_output = _08_;
  assign \module_to_global[output]  = _10_;
  assign \module_to_global[input_ready]  = _09_;
endmodule

Timing Analysis

Path 1-4.812 ns

From: inner/solution_0clk_23eb2db7/_01_[1]$_DFFE_PP_/Q

To: inner/solution_0clk_23eb2db7/_01_[23]$_DFFE_PP_/D

Data Arrival: 4.629 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`inner/solution_0clk_23eb2db7/_01_[1]$_DFFE_PP_/CLK`
0.768	sky130_fd_sc_hvl__dfxtp_1	`inner/solution_0clk_23eb2db7/_01_[1]$_DFFE_PP_/Q`
0.768	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$638/B`
1.152	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$638/Y`
1.152	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$646/A2`
1.546	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$646/Y`
1.546	sky130_fd_sc_hvl__a21oi_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$666/A1`
1.974	sky130_fd_sc_hvl__a21oi_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$666/Y`
1.974	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$690/A2`
2.540	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$690/Y`
2.540	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$762/B`
2.701	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$762/Y`
2.701	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$763/B`
3.068	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$763/Y`
3.068	sky130_fd_sc_hvl__nand3_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$784/A`
3.435	sky130_fd_sc_hvl__nand3_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$784/Y`
3.435	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$789/A2`
3.697	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$789/Y`
3.697	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$790/A`
3.894	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$790/Y`
3.894	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l47_c5_7e4d/$abc$873$auto$blifparse.cc:396:parse_blif$943/A`
3.994	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l47_c5_7e4d/$abc$873$auto$blifparse.cc:396:parse_blif$943/Y`
3.994	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l47_c5_7e4d/$abc$873$auto$blifparse.cc:396:parse_blif$945/A2`
4.126	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l47_c5_7e4d/$abc$873$auto$blifparse.cc:396:parse_blif$945/Y`
4.126	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l43_c3_e456/$abc$873$auto$blifparse.cc:396:parse_blif$944/B`
4.237	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l43_c3_e456/$abc$873$auto$blifparse.cc:396:parse_blif$944/Y`
4.237	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l43_c3_e456/$abc$873$auto$blifparse.cc:396:parse_blif$945/B1`
4.390	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l43_c3_e456/$abc$873$auto$blifparse.cc:396:parse_blif$945/Y`
4.390	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/$abc$947$auto$blifparse.cc:396:parse_blif$1000/B`
4.502	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/$abc$947$auto$blifparse.cc:396:parse_blif$1000/Y`
4.502	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/$abc$947$auto$blifparse.cc:396:parse_blif$1001/B1`
4.629	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/$abc$947$auto$blifparse.cc:396:parse_blif$1001/Y`
4.629	sky130_fd_sc_hvl__dfxtp_1	`inner/solution_0clk_23eb2db7/_01_[23]$_DFFE_PP_/D`

Path 2-4.734 ns

From: inner/solution_0clk_23eb2db7/_01_[1]$_DFFE_PP_/Q

To: inner/solution_0clk_23eb2db7/_01_[22]$_DFFE_PP_/D

Data Arrival: 4.551 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`inner/solution_0clk_23eb2db7/_01_[1]$_DFFE_PP_/CLK`
0.768	sky130_fd_sc_hvl__dfxtp_1	`inner/solution_0clk_23eb2db7/_01_[1]$_DFFE_PP_/Q`
0.768	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$638/B`
1.152	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$638/Y`
1.152	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$646/A2`
1.546	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$646/Y`
1.546	sky130_fd_sc_hvl__a21oi_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$666/A1`
1.974	sky130_fd_sc_hvl__a21oi_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$666/Y`
1.974	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$690/A2`
2.540	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$690/Y`
2.540	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$762/B`
2.701	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$762/Y`
2.701	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$763/B`
3.068	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$763/Y`
3.068	sky130_fd_sc_hvl__nand3_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$784/A`
3.435	sky130_fd_sc_hvl__nand3_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$784/Y`
3.435	sky130_fd_sc_hvl__xor2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$785/B`
3.808	sky130_fd_sc_hvl__xor2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$785/X`
3.808	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l47_c5_7e4d/$abc$873$auto$blifparse.cc:396:parse_blif$940/A`
3.915	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l47_c5_7e4d/$abc$873$auto$blifparse.cc:396:parse_blif$940/Y`
3.915	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l47_c5_7e4d/$abc$873$auto$blifparse.cc:396:parse_blif$942/A2`
4.048	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l47_c5_7e4d/$abc$873$auto$blifparse.cc:396:parse_blif$942/Y`
4.048	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l43_c3_e456/$abc$873$auto$blifparse.cc:396:parse_blif$941/B`
4.160	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l43_c3_e456/$abc$873$auto$blifparse.cc:396:parse_blif$941/Y`
4.160	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l43_c3_e456/$abc$873$auto$blifparse.cc:396:parse_blif$942/B1`
4.312	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l43_c3_e456/$abc$873$auto$blifparse.cc:396:parse_blif$942/Y`
4.312	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/$abc$947$auto$blifparse.cc:396:parse_blif$997/B`
4.425	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/$abc$947$auto$blifparse.cc:396:parse_blif$997/Y`
4.425	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/$abc$947$auto$blifparse.cc:396:parse_blif$998/B1`
4.551	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/$abc$947$auto$blifparse.cc:396:parse_blif$998/Y`
4.551	sky130_fd_sc_hvl__dfxtp_1	`inner/solution_0clk_23eb2db7/_01_[22]$_DFFE_PP_/D`

Path 3-4.630 ns

From: inner/solution_0clk_23eb2db7/_01_[1]$_DFFE_PP_/Q

To: inner/solution_0clk_23eb2db7/_01_[21]$_DFFE_PP_/D

Data Arrival: 4.448 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`inner/solution_0clk_23eb2db7/_01_[1]$_DFFE_PP_/CLK`
0.768	sky130_fd_sc_hvl__dfxtp_1	`inner/solution_0clk_23eb2db7/_01_[1]$_DFFE_PP_/Q`
0.768	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$638/B`
1.152	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$638/Y`
1.152	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$646/A2`
1.546	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$646/Y`
1.546	sky130_fd_sc_hvl__a21oi_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$666/A1`
1.974	sky130_fd_sc_hvl__a21oi_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$666/Y`
1.974	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$690/A2`
2.540	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$690/Y`
2.540	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$762/B`
2.701	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$762/Y`
2.701	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$763/B`
3.068	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$763/Y`
3.068	sky130_fd_sc_hvl__nand3_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$780/A`
3.360	sky130_fd_sc_hvl__nand3_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$780/Y`
3.360	sky130_fd_sc_hvl__xor2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$781/B`
3.706	sky130_fd_sc_hvl__xor2_1	`inner/solution_0clk_23eb2db7/bin_op_plus_solution_c_l45_c5_85e9/$abc$637$auto$blifparse.cc:396:parse_blif$781/X`
3.706	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l47_c5_7e4d/$abc$873$auto$blifparse.cc:396:parse_blif$937/A`
3.812	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l47_c5_7e4d/$abc$873$auto$blifparse.cc:396:parse_blif$937/Y`
3.812	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l47_c5_7e4d/$abc$873$auto$blifparse.cc:396:parse_blif$939/A2`
3.944	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l47_c5_7e4d/$abc$873$auto$blifparse.cc:396:parse_blif$939/Y`
3.944	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l43_c3_e456/$abc$873$auto$blifparse.cc:396:parse_blif$938/B`
4.056	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l43_c3_e456/$abc$873$auto$blifparse.cc:396:parse_blif$938/Y`
4.056	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l43_c3_e456/$abc$873$auto$blifparse.cc:396:parse_blif$939/B1`
4.209	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/acc_mux_solution_c_l43_c3_e456/$abc$873$auto$blifparse.cc:396:parse_blif$939/Y`
4.209	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/$abc$947$auto$blifparse.cc:396:parse_blif$994/B`
4.321	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_23eb2db7/$abc$947$auto$blifparse.cc:396:parse_blif$994/Y`
4.321	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/$abc$947$auto$blifparse.cc:396:parse_blif$995/B1`
4.448	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_23eb2db7/$abc$947$auto$blifparse.cc:396:parse_blif$995/Y`
4.448	sky130_fd_sc_hvl__dfxtp_1	`inner/solution_0clk_23eb2db7/_01_[21]$_DFFE_PP_/D`

Post-Synthesis Verilog

Download synth.v