Histogram - Latchup

1 / 1

View past submissions Leaderboard

Back to submissions

Submission #3

PASSED

RankingPercentile

Latency

17914.51 (1299 cycles)ns

4th

top 100%

Throughput

45.75 (63.1%)MHz

4th

top 100%

Area

24410μm²

4th

top 100%

Score

90.81

4th

top 100%

Submitted Solution

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready,
  input wire i_valid,
  input wire [4-1:0] i_payload_stream_fragment,
  input wire i_payload_stream_last,
  output wire [12-1:0] o_payload_fragment,
  output wire o_payload_last,
  output wire o_valid
);

// Define your design here
  
  parameter START = 0, READING = 1, WRITING = 2, DONE = 3;
  reg[1:0] state;
  reg[1:0] next_state;
  reg[3:0] counter;
  
  reg [11:0] hist [0:15];// = {16{12'd0}} ;
  
  integer i;
  
  always @(*) begin
    case (state)
      START: next_state = i_valid ? READING : START;
      READING: next_state = i_payload_stream_last ? WRITING : READING;
      WRITING: next_state = (counter < 4'd15) ? WRITING : DONE;
      DONE: next_state = i_valid ? READING : START;
    endcase
  end
  
  always @(posedge clk) begin
    if (reset) begin
      state <= START;
    end
    else begin
      state <= next_state;
      if (state == START) begin
        counter <= 4'd0;
        for (i = 0; i < 16; i += 1) begin
          hist[i] <= 12'd0;
        end
        /*if (i_valid) begin
          hist[i_payload_stream_fragment] <= hist[i_payload_stream_fragment] + 1;
        end*/
      end
      if (state == READING) begin
        hist[i_payload_stream_fragment] <= hist[i_payload_stream_fragment] + 1;
      end
      else if (state == WRITING) begin
        // o_payload_fragment <= hist[counter];
        // o_payload_last <= counter == 4'd15 ? 1'b1 : 1'b0;
        counter <= counter + 4'b1;
      end
      else if (state == DONE) begin
        counter <= 4'd0;
        for (i = 0; i < 16; i += 1) begin
          hist[i] <= 12'd0;
        end
      end
    end
  end
  
  assign i_ready = state == READING;
  assign o_valid = state == WRITING;
  assign o_payload_fragment = state == WRITING ? hist[counter] : 12'd0;
  assign o_payload_last = state == WRITING & counter == 4'd15 ? 1'b1 : 1'b0;

endmodule

Generated Verilog

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready,
  input wire i_valid,
  input wire [4-1:0] i_payload_stream_fragment,
  input wire i_payload_stream_last,
  output wire [12-1:0] o_payload_fragment,
  output wire o_payload_last,
  output wire o_valid
);

// Define your design here
  
  parameter START = 0, READING = 1, WRITING = 2, DONE = 3;
  reg[1:0] state;
  reg[1:0] next_state;
  reg[3:0] counter;
  
  reg [11:0] hist [0:15];// = {16{12'd0}} ;
  
  integer i;
  
  always @(*) begin
    case (state)
      START: next_state = i_valid ? READING : START;
      READING: next_state = i_payload_stream_last ? WRITING : READING;
      WRITING: next_state = (counter < 4'd15) ? WRITING : DONE;
      DONE: next_state = i_valid ? READING : START;
    endcase
  end
  
  always @(posedge clk) begin
    if (reset) begin
      state <= START;
    end
    else begin
      state <= next_state;
      if (state == START) begin
        counter <= 4'd0;
        for (i = 0; i < 16; i += 1) begin
          hist[i] <= 12'd0;
        end
        /*if (i_valid) begin
          hist[i_payload_stream_fragment] <= hist[i_payload_stream_fragment] + 1;
        end*/
      end
      if (state == READING) begin
        hist[i_payload_stream_fragment] <= hist[i_payload_stream_fragment] + 1;
      end
      else if (state == WRITING) begin
        // o_payload_fragment <= hist[counter];
        // o_payload_last <= counter == 4'd15 ? 1'b1 : 1'b0;
        counter <= counter + 4'b1;
      end
      else if (state == DONE) begin
        counter <= 4'd0;
        for (i = 0; i < 16; i += 1) begin
          hist[i] <= 12'd0;
        end
      end
    end
  end
  
  assign i_ready = state == READING;
  assign o_valid = state == WRITING;
  assign o_payload_fragment = state == WRITING ? hist[counter] : 12'd0;
  assign o_payload_last = state == WRITING & counter == 4'd15 ? 1'b1 : 1'b0;

endmodule

Timing Analysis

Path 1-13.790 ns

From: state[1]$_DFF_P_/Q

To: hist[0][11]$_DFFE_PP_/D

Data Arrival: 13.620 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`state[1]$_DFF_P_/CLK`
0.958	sky130_fd_sc_hvl__dfxtp_1	`state[1]$_DFF_P_/Q`
0.958	sky130_fd_sc_hvl__nand2_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5455/B`
3.132	sky130_fd_sc_hvl__nand2_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5455/Y`
3.132	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5456/B1`
8.785	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5456/Y`
8.785	sky130_fd_sc_hvl__nor2_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5858/B`
9.863	sky130_fd_sc_hvl__nor2_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5858/Y`
9.863	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5860/A1`
10.160	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5860/Y`
10.160	sky130_fd_sc_hvl__a21o_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5864/A1`
10.500	sky130_fd_sc_hvl__a21o_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5864/X`
10.500	sky130_fd_sc_hvl__a21oi_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5872/A1`
10.760	sky130_fd_sc_hvl__a21oi_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5872/Y`
10.760	sky130_fd_sc_hvl__o22ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5873/B2`
10.970	sky130_fd_sc_hvl__o22ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5873/Y`
10.970	sky130_fd_sc_hvl__nor2_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5874/B`
11.280	sky130_fd_sc_hvl__nor2_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5874/Y`
11.280	sky130_fd_sc_hvl__nand3_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5875/C`
11.550	sky130_fd_sc_hvl__nand3_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5875/Y`
11.550	sky130_fd_sc_hvl__nor3_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5876/C`
13.120	sky130_fd_sc_hvl__nor3_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5876/Y`
13.120	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$6038/A1`
13.380	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$6038/Y`
13.380	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$6039/A2`
13.620	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$6039/Y`
13.620	sky130_fd_sc_hvl__dfxtp_1	`hist[0][11]$_DFFE_PP_/D`

Path 2-13.790 ns

From: state[1]$_DFF_P_/Q

To: hist[10][11]$_DFFE_PP_/D

Data Arrival: 13.620 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`state[1]$_DFF_P_/CLK`
0.958	sky130_fd_sc_hvl__dfxtp_1	`state[1]$_DFF_P_/Q`
0.958	sky130_fd_sc_hvl__nand2_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5455/B`
3.132	sky130_fd_sc_hvl__nand2_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5455/Y`
3.132	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5456/B1`
8.785	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5456/Y`
8.785	sky130_fd_sc_hvl__nor2_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5858/B`
9.863	sky130_fd_sc_hvl__nor2_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5858/Y`
9.863	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5860/A1`
10.160	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5860/Y`
10.160	sky130_fd_sc_hvl__a21o_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5864/A1`
10.500	sky130_fd_sc_hvl__a21o_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5864/X`
10.500	sky130_fd_sc_hvl__a21oi_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5872/A1`
10.760	sky130_fd_sc_hvl__a21oi_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5872/Y`
10.760	sky130_fd_sc_hvl__o22ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5873/B2`
10.970	sky130_fd_sc_hvl__o22ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5873/Y`
10.970	sky130_fd_sc_hvl__nor2_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5874/B`
11.280	sky130_fd_sc_hvl__nor2_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5874/Y`
11.280	sky130_fd_sc_hvl__nand3_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5875/C`
11.550	sky130_fd_sc_hvl__nand3_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5875/Y`
11.550	sky130_fd_sc_hvl__nor3_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5876/C`
13.120	sky130_fd_sc_hvl__nor3_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5876/Y`
13.120	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$6033/A1`
13.380	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$6033/Y`
13.380	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$6034/A2`
13.620	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$6034/Y`
13.620	sky130_fd_sc_hvl__dfxtp_1	`hist[10][11]$_DFFE_PP_/D`

Path 3-13.790 ns

From: state[1]$_DFF_P_/Q

To: hist[11][11]$_DFFE_PP_/D

Data Arrival: 13.620 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`state[1]$_DFF_P_/CLK`
0.958	sky130_fd_sc_hvl__dfxtp_1	`state[1]$_DFF_P_/Q`
0.958	sky130_fd_sc_hvl__nand2_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5455/B`
3.132	sky130_fd_sc_hvl__nand2_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5455/Y`
3.132	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5456/B1`
8.785	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5456/Y`
8.785	sky130_fd_sc_hvl__nor2_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5858/B`
9.863	sky130_fd_sc_hvl__nor2_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5858/Y`
9.863	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5860/A1`
10.160	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5860/Y`
10.160	sky130_fd_sc_hvl__a21o_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5864/A1`
10.500	sky130_fd_sc_hvl__a21o_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5864/X`
10.500	sky130_fd_sc_hvl__a21oi_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5872/A1`
10.760	sky130_fd_sc_hvl__a21oi_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5872/Y`
10.760	sky130_fd_sc_hvl__o22ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5873/B2`
10.970	sky130_fd_sc_hvl__o22ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5873/Y`
10.970	sky130_fd_sc_hvl__nor2_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5874/B`
11.280	sky130_fd_sc_hvl__nor2_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5874/Y`
11.280	sky130_fd_sc_hvl__nand3_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5875/C`
11.550	sky130_fd_sc_hvl__nand3_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5875/Y`
11.550	sky130_fd_sc_hvl__nor3_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5876/C`
13.120	sky130_fd_sc_hvl__nor3_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$5876/Y`
13.120	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$6028/A1`
13.380	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$6028/Y`
13.380	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$6029/A2`
13.620	sky130_fd_sc_hvl__o21ai_1	`$abc$5405$auto$blifparse.cc:396:parse_blif$6029/Y`
13.620	sky130_fd_sc_hvl__dfxtp_1	`hist[11][11]$_DFFE_PP_/D`

Post-Synthesis Verilog

Download synth.v