Histogram - Latchup

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Submitted Solution

`timescale 1ns / 1ps
`default_nettype none

// Histogram: count occurrences of each 4-bit value in an input stream,
// then output 16 bin counts in order.
//
// Input stream interface (ready/valid handshake, registered):
//   i_ready (output): Asserted when module can accept input this cycle
//   i_valid (input):  Asserted when input data is valid
//   i_payload_stream_fragment: 4-bit input value
//   i_payload_stream_last:     Marks final value in the stream
//
// Output interface (no backpressure, registered):
//   o_valid:            Asserted for 16 consecutive cycles
//   o_payload_fragment: 12-bit bin count for the current index
//   o_payload_last:     Marks the final output (bin 15)
//
// All outputs registered. i_ready is predictive: set based on what the
// module will be able to accept next cycle.

// AI Assisted:
// I'm using this as a test problem to help me figure out agentic-AI methods
// for RTL design.
//
// there's not much to say here.  It's FPGA targeted because that's what I'm
// trying to get the agentic AI to design for.  This is after a few changes.
// the AI really likes to have combinatorial outputs.
//
// I'm not thrilled that the AI generated this code, but it's fine at this scale.
// I don't mean about the DMEM and read-modify-write.  That's part of the
// actual problem and I was testing out the AI's baseline responses.  which is
// code "for a 7-series artix -1 speed grade running at 125MHz".  DMEM + add +
// fsm is probably fine at 125M.
//
// it moved the output logic into the 1-process, "storybook" FSM.
// that's fine, but also can become an anti-pattern.
//
// This solution isn't really intended to be "interesting" or competitive.
//
// if you actually want a high speed solution, I think you'd make some even/odd
// split (or ABCD split) to have 2-4 parallel units doing the local lookup and
// accumulation over 2-4 cycles.  then an adder tree on the final output to
// combine results.
//
// or something else that would be interesting.  this design could use a shift
// register for example.
//
// I'm mainly submitting this because I'm not sure if there's more to the problem
// than what I was expecting.

module Solution (
  input wire clk,
  input wire reset,
  output reg i_ready,
  input wire i_valid,
  input wire [4-1:0] i_payload_stream_fragment,
  input wire i_payload_stream_last,
  output reg [12-1:0] o_payload_fragment,
  output reg o_payload_last,
  output reg o_valid
);

////////////////////////////////////////////////////////////////////////////////
// {{{ Declarations
localparam ACCUM  = 1'b0;
localparam OUTPUT = 1'b1;

reg        state_q;
reg  [3:0] out_cnt_q;

/* ram_style = "distributed" */
reg [11:0] hist [0:15];
// }}}

////////////////////////////////////////////////////////////////////////////////
// {{{ Main Logic

initial begin
  integer i;
  i = 0;
  for (i = 0; i < 16; i = i + 1) begin
    hist[i] = '0;
  end
end

always @(posedge clk) begin
  // Default: deassert output valid each cycle (overridden in OUTPUT)
  o_valid        <= 1'b0;
  o_payload_last <= 1'b0;

  case (state_q)
    ACCUM: begin
      i_ready <= 1'b1;
      if (i_valid && i_ready) begin
        hist[i_payload_stream_fragment] <= hist[i_payload_stream_fragment] + 12'd1;
        if (i_payload_stream_last) begin
          state_q   <= OUTPUT;
          out_cnt_q <= 4'd0;
          i_ready   <= 1'b0;
        end
      end
    end

    OUTPUT: begin
      o_valid            <= 1'b1;
      o_payload_fragment <= hist[out_cnt_q];
      o_payload_last     <= (out_cnt_q == 4'd15);

      hist[out_cnt_q] <= 12'd0;
      out_cnt_q       <= out_cnt_q + 4'd1;

      i_ready <= 1'b0;
      if (out_cnt_q == 4'd15) begin
        state_q <= ACCUM;
        i_ready <= 1'b1;
      end
    end

    default: begin
      state_q <= ACCUM;
      i_ready <= 1'b1;
    end
  endcase

  if (reset) begin
    state_q   <= ACCUM;
    out_cnt_q <= 4'd0;
    o_valid   <= 1'b0;
    i_ready   <= 1'b1;
  end
end
// }}}

endmodule

`resetall

Generated Verilog

`timescale 1ns / 1ps
`default_nettype none

// Histogram: count occurrences of each 4-bit value in an input stream,
// then output 16 bin counts in order.
//
// Input stream interface (ready/valid handshake, registered):
//   i_ready (output): Asserted when module can accept input this cycle
//   i_valid (input):  Asserted when input data is valid
//   i_payload_stream_fragment: 4-bit input value
//   i_payload_stream_last:     Marks final value in the stream
//
// Output interface (no backpressure, registered):
//   o_valid:            Asserted for 16 consecutive cycles
//   o_payload_fragment: 12-bit bin count for the current index
//   o_payload_last:     Marks the final output (bin 15)
//
// All outputs registered. i_ready is predictive: set based on what the
// module will be able to accept next cycle.

// AI Assisted:
// I'm using this as a test problem to help me figure out agentic-AI methods
// for RTL design.
//
// there's not much to say here.  It's FPGA targeted because that's what I'm
// trying to get the agentic AI to design for.  This is after a few changes.
// the AI really likes to have combinatorial outputs.
//
// I'm not thrilled that the AI generated this code, but it's fine at this scale.
// I don't mean about the DMEM and read-modify-write.  That's part of the
// actual problem and I was testing out the AI's baseline responses.  which is
// code "for a 7-series artix -1 speed grade running at 125MHz".  DMEM + add +
// fsm is probably fine at 125M.
//
// it moved the output logic into the 1-process, "storybook" FSM.
// that's fine, but also can become an anti-pattern.
//
// This solution isn't really intended to be "interesting" or competitive.
//
// if you actually want a high speed solution, I think you'd make some even/odd
// split (or ABCD split) to have 2-4 parallel units doing the local lookup and
// accumulation over 2-4 cycles.  then an adder tree on the final output to
// combine results.
//
// or something else that would be interesting.  this design could use a shift
// register for example.
//
// I'm mainly submitting this because I'm not sure if there's more to the problem
// than what I was expecting.

module Solution (
  input wire clk,
  input wire reset,
  output reg i_ready,
  input wire i_valid,
  input wire [4-1:0] i_payload_stream_fragment,
  input wire i_payload_stream_last,
  output reg [12-1:0] o_payload_fragment,
  output reg o_payload_last,
  output reg o_valid
);

////////////////////////////////////////////////////////////////////////////////
// {{{ Declarations
localparam ACCUM  = 1'b0;
localparam OUTPUT = 1'b1;

reg        state_q;
reg  [3:0] out_cnt_q;

/* ram_style = "distributed" */
reg [11:0] hist [0:15];
// }}}

////////////////////////////////////////////////////////////////////////////////
// {{{ Main Logic

initial begin
  integer i;
  i = 0;
  for (i = 0; i < 16; i = i + 1) begin
    hist[i] = '0;
  end
end

always @(posedge clk) begin
  // Default: deassert output valid each cycle (overridden in OUTPUT)
  o_valid        <= 1'b0;
  o_payload_last <= 1'b0;

  case (state_q)
    ACCUM: begin
      i_ready <= 1'b1;
      if (i_valid && i_ready) begin
        hist[i_payload_stream_fragment] <= hist[i_payload_stream_fragment] + 12'd1;
        if (i_payload_stream_last) begin
          state_q   <= OUTPUT;
          out_cnt_q <= 4'd0;
          i_ready   <= 1'b0;
        end
      end
    end

    OUTPUT: begin
      o_valid            <= 1'b1;
      o_payload_fragment <= hist[out_cnt_q];
      o_payload_last     <= (out_cnt_q == 4'd15);

      hist[out_cnt_q] <= 12'd0;
      out_cnt_q       <= out_cnt_q + 4'd1;

      i_ready <= 1'b0;
      if (out_cnt_q == 4'd15) begin
        state_q <= ACCUM;
        i_ready <= 1'b1;
      end
    end

    default: begin
      state_q <= ACCUM;
      i_ready <= 1'b1;
    end
  endcase

  if (reset) begin
    state_q   <= ACCUM;
    out_cnt_q <= 4'd0;
    o_valid   <= 1'b0;
    i_ready   <= 1'b1;
  end
end
// }}}

endmodule

`resetall

Timing Analysis

Path 1-6.213 ns

From: out_cnt_q[2]$_SDFFE_PP0P_/Q

To: hist[2][0]$_DFFE_PP_/D

Data Arrival: 6.021 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`out_cnt_q[2]$_SDFFE_PP0P_/CLK`
2.402	sky130_fd_sc_hvl__dfxtp_1	`out_cnt_q[2]$_SDFFE_PP0P_/Q`
2.402	sky130_fd_sc_hvl__mux2_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3125/A1`
3.866	sky130_fd_sc_hvl__mux2_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3125/X`
3.866	sky130_fd_sc_hvl__nor2_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3330/B`
4.168	sky130_fd_sc_hvl__nor2_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3330/Y`
4.168	sky130_fd_sc_hvl__nand3_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3595/C`
5.206	sky130_fd_sc_hvl__nand3_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3595/Y`
5.206	sky130_fd_sc_hvl__mux2_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3596/S`
6.021	sky130_fd_sc_hvl__mux2_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3596/X`
6.021	sky130_fd_sc_hvl__dfxtp_1	`hist[2][0]$_DFFE_PP_/D`

Path 2-6.213 ns

From: out_cnt_q[2]$_SDFFE_PP0P_/Q

To: hist[2][10]$_DFFE_PP_/D

Data Arrival: 6.021 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`out_cnt_q[2]$_SDFFE_PP0P_/CLK`
2.402	sky130_fd_sc_hvl__dfxtp_1	`out_cnt_q[2]$_SDFFE_PP0P_/Q`
2.402	sky130_fd_sc_hvl__mux2_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3125/A1`
3.866	sky130_fd_sc_hvl__mux2_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3125/X`
3.866	sky130_fd_sc_hvl__nor2_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3330/B`
4.168	sky130_fd_sc_hvl__nor2_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3330/Y`
4.168	sky130_fd_sc_hvl__nand3_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3595/C`
5.206	sky130_fd_sc_hvl__nand3_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3595/Y`
5.206	sky130_fd_sc_hvl__mux2_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3606/S`
6.021	sky130_fd_sc_hvl__mux2_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3606/X`
6.021	sky130_fd_sc_hvl__dfxtp_1	`hist[2][10]$_DFFE_PP_/D`

Path 3-6.213 ns

From: out_cnt_q[2]$_SDFFE_PP0P_/Q

To: hist[2][11]$_DFFE_PP_/D

Data Arrival: 6.021 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`out_cnt_q[2]$_SDFFE_PP0P_/CLK`
2.402	sky130_fd_sc_hvl__dfxtp_1	`out_cnt_q[2]$_SDFFE_PP0P_/Q`
2.402	sky130_fd_sc_hvl__mux2_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3125/A1`
3.866	sky130_fd_sc_hvl__mux2_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3125/X`
3.866	sky130_fd_sc_hvl__nor2_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3330/B`
4.168	sky130_fd_sc_hvl__nor2_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3330/Y`
4.168	sky130_fd_sc_hvl__nand3_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3595/C`
5.206	sky130_fd_sc_hvl__nand3_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3595/Y`
5.206	sky130_fd_sc_hvl__mux2_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3607/S`
6.021	sky130_fd_sc_hvl__mux2_1	`$abc$3105$auto$blifparse.cc:396:parse_blif$3607/X`
6.021	sky130_fd_sc_hvl__dfxtp_1	`hist[2][11]$_DFFE_PP_/D`

Post-Synthesis Verilog

Download synth.v