Railgun Calibration

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Submission #1

PASSED

RankingPercentile

Latency

369.80 (51 cycles)ns

2nd

top 50%

Max Frequency

137.91MHz

2nd

top 50%

Area

4294μm²

2nd

top 50%

Submitted Solution

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready,
  input wire i_valid,
  input wire [4-1:0] i_payload_coils_fragment,
  input wire i_payload_coils_last,
  output wire [64-1:0] o_payload,
  output wire o_valid
);

// Define your design here

// I'm assuming the smaller version of the solution was already done.
// so mine is doing the multiply up front.
  
// also, not sure what to do for under 3 coils.
reg [3:0] x0_1 = 0;
reg [6:0] x0_10 = 0;
reg [9:0] x0_100 = 0;
reg [3:0] x1_1 = 0;
reg [6:0] x1_10 = 0;
reg [9:0] x1_100 = 0;
reg [3:0] x2_1 = 0;
//reg [6:0] x2_10; // not used
reg [9:0] x2_100 = 0;
reg last = 0;

wire [3:0] in1 = i_payload_coils_fragment;
wire [6:0] in10 = (i_payload_coils_fragment << 3) + (i_payload_coils_fragment << 1); // 1010
wire [9:0] in100 = (i_payload_coils_fragment << 6) + (i_payload_coils_fragment << 5) + (i_payload_coils_fragment << 2); // 0110 0100

wire [9:0] output_sum = x2_100 + x1_10 + x0_1;

assign o_payload = {{(54){1'b0}}, output_sum};
assign i_ready = ~reset;
assign o_valid = last;

always@(posedge clk) begin
    if (i_valid) begin
        if (x2_1 < x1_1) begin
            x2_100 <= x1_100;
            x2_1 <= x1_1;
            x1_100 <= x0_100;
            x1_10 <= x0_10;
            x1_1 <= x0_1;
            x0_100 <= in100;
            x0_10 <= in10;
            x0_1 <= in1;
        end else if (x1_1 < x0_1) begin
            x1_100 <= x0_100;
            x1_10 <= x0_10;
            x1_1 <= x0_1;
            x0_100 <= in100;
            x0_10 <= in10;
            x0_1 <= in1;
        end else if (x0_1 < i_payload_coils_fragment) begin
            x0_100 <= in100;
            x0_10 <= in10;
            x0_1 <= in1;
        end
        last <= i_payload_coils_last;
    end

    if (reset) begin
        x0_1 <= 0;
        x0_10 <= 0;
        x0_100 <= 0;
        x1_1 <= 0;
        x1_10 <= 0;
        x1_100 <= 0;
        x2_1 <= 0;
        x2_100 <= 0;
        last <= 0;
    end
    
end

endmodule

Generated Verilog

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready,
  input wire i_valid,
  input wire [4-1:0] i_payload_coils_fragment,
  input wire i_payload_coils_last,
  output wire [64-1:0] o_payload,
  output wire o_valid
);

// Define your design here

// I'm assuming the smaller version of the solution was already done.
// so mine is doing the multiply up front.
  
// also, not sure what to do for under 3 coils.
reg [3:0] x0_1 = 0;
reg [6:0] x0_10 = 0;
reg [9:0] x0_100 = 0;
reg [3:0] x1_1 = 0;
reg [6:0] x1_10 = 0;
reg [9:0] x1_100 = 0;
reg [3:0] x2_1 = 0;
//reg [6:0] x2_10; // not used
reg [9:0] x2_100 = 0;
reg last = 0;

wire [3:0] in1 = i_payload_coils_fragment;
wire [6:0] in10 = (i_payload_coils_fragment << 3) + (i_payload_coils_fragment << 1); // 1010
wire [9:0] in100 = (i_payload_coils_fragment << 6) + (i_payload_coils_fragment << 5) + (i_payload_coils_fragment << 2); // 0110 0100

wire [9:0] output_sum = x2_100 + x1_10 + x0_1;

assign o_payload = {{(54){1'b0}}, output_sum};
assign i_ready = ~reset;
assign o_valid = last;

always@(posedge clk) begin
    if (i_valid) begin
        if (x2_1 < x1_1) begin
            x2_100 <= x1_100;
            x2_1 <= x1_1;
            x1_100 <= x0_100;
            x1_10 <= x0_10;
            x1_1 <= x0_1;
            x0_100 <= in100;
            x0_10 <= in10;
            x0_1 <= in1;
        end else if (x1_1 < x0_1) begin
            x1_100 <= x0_100;
            x1_10 <= x0_10;
            x1_1 <= x0_1;
            x0_100 <= in100;
            x0_10 <= in10;
            x0_1 <= in1;
        end else if (x0_1 < i_payload_coils_fragment) begin
            x0_100 <= in100;
            x0_10 <= in10;
            x0_1 <= in1;
        end
        last <= i_payload_coils_last;
    end

    if (reset) begin
        x0_1 <= 0;
        x0_10 <= 0;
        x0_100 <= 0;
        x1_1 <= 0;
        x1_10 <= 0;
        x1_100 <= 0;
        x2_1 <= 0;
        x2_100 <= 0;
        last <= 0;
    end
    
end

endmodule

Timing Analysis

Path 1-7.247 ns

From: x1_100[3]$_SDFFE_PP0P_/Q

To: x0_1[3]$_SDFFE_PP0P_/D

Data Arrival: 7.111 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`x1_100[3]$_SDFFE_PP0P_/CLK`
0.712	sky130_fd_sc_hvl__dfxtp_1	`x1_100[3]$_SDFFE_PP0P_/Q`
0.712	sky130_fd_sc_hvl__inv_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1073/A`
0.974	sky130_fd_sc_hvl__inv_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1073/Y`
0.974	sky130_fd_sc_hvl__o22ai_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1091/B2`
1.169	sky130_fd_sc_hvl__o22ai_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1091/Y`
1.169	sky130_fd_sc_hvl__a21oi_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1092/B1`
1.364	sky130_fd_sc_hvl__a21oi_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1092/Y`
1.364	sky130_fd_sc_hvl__o22ai_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1096/B1`
2.360	sky130_fd_sc_hvl__o22ai_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1096/Y`
2.360	sky130_fd_sc_hvl__a21oi_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1097/B1`
4.279	sky130_fd_sc_hvl__a21oi_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1097/Y`
4.279	sky130_fd_sc_hvl__o21ai_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1103/B1`
6.037	sky130_fd_sc_hvl__o21ai_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1103/Y`
6.037	sky130_fd_sc_hvl__mux2_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1178/S`
6.991	sky130_fd_sc_hvl__mux2_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1178/X`
6.991	sky130_fd_sc_hvl__nor2_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1179/B`
7.111	sky130_fd_sc_hvl__nor2_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1179/Y`
7.111	sky130_fd_sc_hvl__dfxtp_1	`x0_1[3]$_SDFFE_PP0P_/D`

Path 2-7.063 ns

From: x1_100[3]$_SDFFE_PP0P_/Q

To: x0_10[3]$_SDFFE_PP0P_/D

Data Arrival: 6.893 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`x1_100[3]$_SDFFE_PP0P_/CLK`
0.712	sky130_fd_sc_hvl__dfxtp_1	`x1_100[3]$_SDFFE_PP0P_/Q`
0.712	sky130_fd_sc_hvl__inv_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1073/A`
0.974	sky130_fd_sc_hvl__inv_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1073/Y`
0.974	sky130_fd_sc_hvl__o22ai_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1091/B2`
1.169	sky130_fd_sc_hvl__o22ai_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1091/Y`
1.169	sky130_fd_sc_hvl__a21oi_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1092/B1`
1.364	sky130_fd_sc_hvl__a21oi_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1092/Y`
1.364	sky130_fd_sc_hvl__o22ai_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1096/B1`
2.360	sky130_fd_sc_hvl__o22ai_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1096/Y`
2.360	sky130_fd_sc_hvl__a21oi_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1097/B1`
4.279	sky130_fd_sc_hvl__a21oi_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1097/Y`
4.279	sky130_fd_sc_hvl__o21ai_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1103/B1`
6.037	sky130_fd_sc_hvl__o21ai_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1103/Y`
6.037	sky130_fd_sc_hvl__nand2_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1107/B`
6.436	sky130_fd_sc_hvl__nand2_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1107/Y`
6.436	sky130_fd_sc_hvl__nand2_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1109/A`
6.607	sky130_fd_sc_hvl__nand2_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1109/Y`
6.607	sky130_fd_sc_hvl__a22oi_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1110/B2`
6.812	sky130_fd_sc_hvl__a22oi_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1110/Y`
6.812	sky130_fd_sc_hvl__nor2_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1111/B`
6.893	sky130_fd_sc_hvl__nor2_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1111/Y`
6.893	sky130_fd_sc_hvl__dfxtp_1	`x0_10[3]$_SDFFE_PP0P_/D`

Path 3-6.955 ns

From: x1_100[3]$_SDFFE_PP0P_/Q

To: x0_100[5]$_SDFFE_PP0P_/D

Data Arrival: 6.664 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`x1_100[3]$_SDFFE_PP0P_/CLK`
0.712	sky130_fd_sc_hvl__dfxtp_1	`x1_100[3]$_SDFFE_PP0P_/Q`
0.712	sky130_fd_sc_hvl__inv_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1073/A`
0.974	sky130_fd_sc_hvl__inv_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1073/Y`
0.974	sky130_fd_sc_hvl__o22ai_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1091/B2`
1.169	sky130_fd_sc_hvl__o22ai_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1091/Y`
1.169	sky130_fd_sc_hvl__a21oi_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1092/B1`
1.364	sky130_fd_sc_hvl__a21oi_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1092/Y`
1.364	sky130_fd_sc_hvl__o22ai_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1096/B1`
2.360	sky130_fd_sc_hvl__o22ai_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1096/Y`
2.360	sky130_fd_sc_hvl__a21oi_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1097/B1`
4.279	sky130_fd_sc_hvl__a21oi_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1097/Y`
4.279	sky130_fd_sc_hvl__o21ai_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1103/B1`
6.037	sky130_fd_sc_hvl__o21ai_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1103/Y`
6.037	sky130_fd_sc_hvl__o21ai_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1195/A2`
6.569	sky130_fd_sc_hvl__o21ai_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1195/Y`
6.569	sky130_fd_sc_hvl__a21oi_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1196/B1`
6.664	sky130_fd_sc_hvl__a21oi_1	`$abc$1066$auto$blifparse.cc:396:parse_blif$1196/Y`
6.664	sky130_fd_sc_hvl__dfxtp_1	`x0_100[5]$_SDFFE_PP0P_/D`

Post-Synthesis Verilog

Download synth.v