Bunker Network - Latchup

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Submitted Solution

// PipelineC solution template.
#include "uintN_t.h"
#include "intN_t.h"
#include "stream/stream.h"

// Input stream interface:
//   input.valid (input): Asserted when input data is valid
//   input.data.* (input): Input payload fields
//   input_ready (output): Assert when ready to accept input
//
// Output flow interface (no backpressure):
//   output.valid (output): Assert when output data is valid
//   output.data.* (output): Output payload fields

typedef struct input_payload_t {
  uint1_t grid_fragment_fragment;
  uint1_t grid_fragment_last;
  uint1_t grid_last;
} input_payload_t;
DECL_STREAM_TYPE(input_payload_t)

typedef struct output_payload_t {
  uint16_t result;
} output_payload_t;
DECL_STREAM_TYPE(output_payload_t)

DECL_INPUT(stream(input_payload_t), input)
DECL_OUTPUT(uint1_t, input_ready)

DECL_OUTPUT(stream(output_payload_t), output)

#define CLK_RATE_MHZ 0.001
DECL_INPUT(uint1_t, clk)
CLK_MHZ(clk, CLK_RATE_MHZ)

// See https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Latchup-Solutions for details

#include "uintN_t.h"
#include "intN_t.h"
#include "arrays.h"
#include "global_func_inst.h"
#include "fifo.h"

#define WINDOW_HEIGHT 3
#define WINDOW_WIDTH 3
#define WINDOW_CENTER_X (WINDOW_WIDTH / 2)
#define WINDOW_CENTER_Y (WINDOW_HEIGHT / 2)
#define X_INIT ((-WINDOW_CENTER_X) - 1)
#define Y_INIT (-WINDOW_CENTER_Y)
#define window_sliding_flags_and uint1_array_and4 // WINDOW_HEIGHT+1
#define MAX_LINE_WIDTH 128 // Used to size fifo buffers
#define MAX_NUM_LINES 128
#define line_w_t int9_t // min: log2 line width +1
#define line_h_t int9_t // min: log2 num lines + 1
#define input_t uint1_t
#define EMPTY 0 // '.'
#define BUNKER 1 // 'X'

// Window stuff
typedef struct window_t{
  input_t data[WINDOW_WIDTH][WINDOW_HEIGHT];
}window_t;
window_t slide_window(window_t curr, input_t next_input_col[WINDOW_HEIGHT]){
  // Sliding right, shifting columns
  window_t next = curr;
  for(uint32_t x = 0; x < WINDOW_WIDTH; x+=1){
    // Copy column x+1 into x
    for(uint32_t y = 0; y < WINDOW_HEIGHT; y+=1){
      if(x < (WINDOW_WIDTH-1)){
        next.data[x][y] = curr.data[x+1][y];
      }else{
        next.data[x][y] = next_input_col[y];
      }
    }
  }
  return next;
}


// Define type of FIFO for holding a line of input
FIFO_FWFT(line_fifo, input_t, MAX_LINE_WIDTH) // IS FPGA BRAM BASED SO DOESNT WELL WITH SKY130?
// Still better than try to make 128 long shift reg?
// Still better than 128 long chain of skid buffers?


// TODO REMOVE TEMP end of frame hack once sending eod through pipeline
uint1_t done_frame_pulse;


// Input stream -> sliding window output using fifos
typedef struct sliding_window_t{
  window_t window;
  line_w_t window_x_pos;
  line_h_t window_y_pos;
  uint1_t window_valid;
  uint1_t ready_for_data_in;
}sliding_window_t;
sliding_window_t sliding_window(
  input_t data,
  uint1_t grid_fragment_last,
  uint1_t grid_last,
  uint1_t data_valid
){
  sliding_window_t o;

  // Window output single cycle valid from regs
  static window_t window;
  static uint1_t window_valid;
  o.window = window;
  o.window_valid = window_valid;
  window_valid = 0;

  // Number of line buffer fifos matching height of window
  // FIFO outputs feed into next fifo as window slides
  // Re: #pragma FEEDBACK
  //  All fifo output signals are only available after the line_fifo() func call
  //  to uses those output values on the input side of func call before invocation
  //  they are declared as FEEDBACK, final assigned value becomes first read value
  uint1_t fifo_output_xfer_enable[WINDOW_HEIGHT];
  #pragma FEEDBACK fifo_output_xfer_enable
  // Write side of fifos
  input_t fifo_inputs[WINDOW_HEIGHT];
  uint1_t fifo_input_valids[WINDOW_HEIGHT];
  uint1_t fifo_readys_for_input[WINDOW_HEIGHT];
  #pragma FEEDBACK fifo_readys_for_input
  // Read side of fifos
  input_t fifo_outputs[WINDOW_HEIGHT];
  #pragma FEEDBACK fifo_outputs
  uint1_t fifo_output_valids[WINDOW_HEIGHT];
  #pragma FEEDBACK fifo_output_valids
  uint1_t fifo_readys_for_output[WINDOW_HEIGHT];

  // Input stream goes into first fifo
  fifo_inputs[0] = data;
  fifo_input_valids[0] = data_valid;
  o.ready_for_data_in = fifo_readys_for_input[0];

  // Count off measuring current line width use eod like fragment flags
  // use eod like fragment flags for end of frame
  // gate flow of next different size frame until end of frame goes out?
  static line_w_t line_width_counter;
  static line_h_t num_lines_counter;
  static line_w_t current_line_width_reg = MAX_LINE_WIDTH;
  line_w_t current_line_width = current_line_width_reg;
  static line_h_t current_num_lines_reg = MAX_NUM_LINES;
  line_h_t current_num_lines = current_num_lines_reg;
  static uint1_t input_side_in_end_of_frame;
  done_frame_pulse = 0;
  if(input_side_in_end_of_frame){
    fifo_input_valids[0] = 0;
    o.ready_for_data_in = 0;
  }
  if(data_valid & o.ready_for_data_in){
    line_width_counter += 1;
    if(grid_fragment_last){
      num_lines_counter += 1;
      current_line_width = line_width_counter;
      line_width_counter = 0;
      if(grid_last){
        current_num_lines = num_lines_counter;
        num_lines_counter = 0;
        input_side_in_end_of_frame = 1;
      }
    }
  }

  // Instances of fifo with output[i] into next[i+1] input wiring
  for(uint32_t i=0; i<WINDOW_HEIGHT; i+=1){
    // FIFO input is from previous line, default disconnected
    fifo_readys_for_output[i] = 0;
    if(i<(WINDOW_HEIGHT-1)){
      fifo_inputs[i+1] = fifo_outputs[i];
    }
    if(i<(WINDOW_HEIGHT-1)){
      // FIFO[i] outputs feed into next fifo[i+1] as window slides
      fifo_input_valids[i+1] = fifo_output_valids[i] & fifo_output_xfer_enable[i];
      fifo_readys_for_output[i] = fifo_readys_for_input[i+1] & fifo_output_xfer_enable[i];
    }else{
      // Last fifo just drains to nowhere as window slides
      fifo_readys_for_output[i] = fifo_output_xfer_enable[i];
    }
    // The fifo itself
    line_fifo_t fifo_out = line_fifo(
      fifo_readys_for_output[i],
      fifo_inputs[i],
      fifo_input_valids[i]
    );
    // FIFO output feedback connections
    fifo_readys_for_input[i] = fifo_out.data_in_ready;
    fifo_outputs[i] = fifo_out.data_out;
    fifo_output_valids[i] = fifo_out.data_out_valid;
  }

  // Window center begins outside of frame
  static line_w_t window_x_pos = X_INIT;
  static line_h_t window_y_pos = Y_INIT;
  o.window_x_pos = window_x_pos;
  o.window_y_pos = window_y_pos;
  // When is more data needed from which fifos?
  static uint1_t want_data_from_fifo[WINDOW_HEIGHT] = {1,1,1};
  
  // Want to slide window if not yet done frame
  // Need to slide window in y direction enough to drain fifos for next frame too
  static uint1_t win_y_lte_num_lines = 1;
  static uint1_t win_y_lt_num_lines = 1;
  static uint1_t win_x_lte_width = 1;
  static uint1_t win_y_lte_num_lines_minus_i[WINDOW_HEIGHT] = {1,1,1};
  uint1_t window_sliding_flags[WINDOW_HEIGHT+1];
  window_sliding_flags[WINDOW_HEIGHT] = win_y_lte_num_lines;
  // But only will slide if have data from all needed fifos
  for(uint32_t i=0; i<WINDOW_HEIGHT; i+=1){
    window_sliding_flags[i] = (fifo_output_valids[i] | ~want_data_from_fifo[i]);
  }
  uint1_t window_sliding = window_sliding_flags_and(window_sliding_flags);

  // Actually reading from fifo if sliding window
  for(uint32_t i=0; i<WINDOW_HEIGHT; i+=1){
    fifo_output_xfer_enable[i] = want_data_from_fifo[i] & window_sliding;
  }

  // Input column values into sliding window have reversed indexing
  // relative to input stream into fifo[i=0] indexing above
  input_t next_input_col[WINDOW_HEIGHT];
  for(uint32_t i=0; i<WINDOW_HEIGHT; i+=1){
    uint32_t y = WINDOW_HEIGHT - 1 - i;
    next_input_col[y] = EMPTY;
    if(fifo_output_valids[i] & fifo_readys_for_output[i]){
      next_input_col[y] = fifo_outputs[i];
    }
  }
  
  // Do window sliding along current row/clearing as needed for next row
  for(uint32_t i=0; i<WINDOW_HEIGHT; i+=1){
    want_data_from_fifo[i] = 
      (window_y_pos >= (i-WINDOW_CENTER_Y)) &
      (window_y_pos <= 
       (current_num_lines_reg-(WINDOW_CENTER_Y+1-i))
      ) &
      (window_x_pos < (current_line_width_reg-2));
  }
  win_y_lte_num_lines = window_y_pos <= current_num_lines_reg;
  //for(uint32_t i=0; i<WINDOW_HEIGHT; i+=1){
  //  win_y_lte_num_lines_minus_i[i] = window_y_pos <=
  //             (current_num_lines_reg-(WINDOW_CENTER_Y+1-i));
  //}
  //win_y_lt_num_lines = window_y_pos < current_num_lines_reg;
  if(window_sliding){
    //printf("Current window center pos: %d,%d (valid=%d)\n", window_x_pos, window_y_pos, o.window_valid);
    //print_3x3("Current:", window.data);
    // Next window is valid?
    if(win_x_lte_width){
      //printf("Sliding right...\n");
      for(uint32_t i=0; i<WINDOW_HEIGHT; i+=1){
        want_data_from_fifo[i] = 
          (window_y_pos >= (i-WINDOW_CENTER_Y)) &
          //(window_y_pos <= 
          // (current_num_lines_reg-(WINDOW_CENTER_Y+1-i))
          //) &
          win_y_lte_num_lines_minus_i[i] &
          (window_x_pos < (current_line_width_reg-3));
      }
      window_x_pos += 1;
      win_x_lte_width = window_x_pos < (current_line_width_reg-1);
      window = slide_window(window, next_input_col);
      window_valid = (window_x_pos >= 0) & (window_y_pos >= 0) & (win_y_lt_num_lines);
    }else{
      //printf("End of line reset...\n");
      window_t empty_window;
      window = empty_window;
      window_x_pos = X_INIT;
      win_x_lte_width = 1;
      if(win_y_lt_num_lines){
        //window_y_pos += 1;
        //win_y_lte_num_lines = window_y_pos <= current_num_lines_reg;
        
        win_y_lte_num_lines = win_y_lt_num_lines; //window_y_pos < current_num_lines_reg;
        
        
        for(uint32_t i=0; i<WINDOW_HEIGHT; i+=1){
          want_data_from_fifo[i] = 
            (window_y_pos >= (i-WINDOW_CENTER_Y-1)) &
            win_y_lte_num_lines_minus_i[i];
        }
        
        
        for(uint32_t i=0; i<WINDOW_HEIGHT; i+=1){
          win_y_lte_num_lines_minus_i[i] = window_y_pos <=
                     (current_num_lines_reg-(WINDOW_CENTER_Y+2-i));
        }
        
        window_y_pos += 1;
        
        win_y_lt_num_lines = window_y_pos < current_num_lines_reg;
      }else{
        // End of frame reset
        window_y_pos = Y_INIT;
        win_y_lte_num_lines = 1;
        for(uint32_t i=0; i<WINDOW_HEIGHT; i+=1){
          win_y_lte_num_lines_minus_i[i] = 1;
        }
        win_y_lt_num_lines = 1;
        done_frame_pulse = 1;
        input_side_in_end_of_frame = 0;
        line_width_counter = 0;
        num_lines_counter = 0;
        current_line_width = MAX_LINE_WIDTH;
        current_num_lines = MAX_NUM_LINES;
        for(uint32_t i=0; i<WINDOW_HEIGHT; i+=1){
          want_data_from_fifo[i] = 1;
        }
      }
    }
  }

  // Update regs with next
  current_line_width_reg = current_line_width;
  current_num_lines_reg = current_num_lines;
  
  return o;
}

//TODO IO structs for sideband data through pipeline
// is_vul
// eod flags based on input window center pos x,y

// Pure function pipeline counting neighbors around the center location
uint1_t center_bunker_vulnerable(window_t window){
  uint4_t neighbor_count;
  input_t center;
  for (uint32_t i = 0; i < WINDOW_WIDTH; i+=1)
  {
    for (uint32_t j = 0; j < WINDOW_HEIGHT; j+=1)
    {
      if((i==WINDOW_CENTER_X)&(j==WINDOW_CENTER_Y)){
        center = window.data[i][j];
      }else{
        neighbor_count += (window.data[i][j]==BUNKER);
      }
    }
  }
  return (center==BUNKER) & (neighbor_count < 4);
}
// center_bunker_vulnerable_pipeline : uint1_t center_bunker_vulnerable(window_t)
//  instance of pipeline without handshaking but does include stream valid bit
//  delcares global variable wires as ports to connect to, named like center_bunker_vulnerable_pipeline _in/_out...
GLOBAL_PIPELINE_INST_W_VALID_ID(center_bunker_vulnerable_pipeline, uint1_t, center_bunker_vulnerable, window_t)


MAIN_MHZ(sliding_window_process, CLK_RATE_MHZ)
void sliding_window_process(){
  // Input stream into instance of sliding window
  sliding_window_t sw = sliding_window(
    input.data.grid_fragment_fragment,
    input.data.grid_fragment_last,
    input.data.grid_last,
    input.valid
    //1 // Pipeline always ready_for_window_out
  );
  // Sliding window output into compute pipeline
  input_ready = sw.ready_for_data_in;
  center_bunker_vulnerable_pipeline_in = sw.window;
  center_bunker_vulnerable_pipeline_in_valid = sw.window_valid;
}


// Accumulate how many total locations and output
MAIN_MHZ(accum_pipeline_output, CLK_RATE_MHZ)
void accum_pipeline_output(){
  static uint16_t total;
  
  // Output once at end of frame
  // TODO REMOVE Hacky temp done signal once sending sideband through pipeline, TODO smaller count
  static uint3_t num_cycles_done_frame;
  static uint1_t done_frame;
  static uint1_t done_frame_pulse_reg;
  if(done_frame){
    if(num_cycles_done_frame < 4){
      num_cycles_done_frame += 1;
    }else{
      done_frame = 0;
      num_cycles_done_frame = 0;
    }
  }
  if(~done_frame){
    if(done_frame_pulse_reg){
      done_frame = 1;
    }
  }
  output.valid = num_cycles_done_frame == 3;
  //output.valid = center_bunker_vulnerable_pipeline_out_valid &
  //  center_bunker_vulnerable_pipeline_out.eod[0] & 
  //  center_bunker_vulnerable_pipeline_out.eod[1];
  output.data.result = total;
  if(output.valid){
    total = 0;
  }else if(center_bunker_vulnerable_pipeline_out_valid){
    total += center_bunker_vulnerable_pipeline_out; //.is_vul;
  }
  done_frame_pulse_reg = done_frame_pulse;
}

Compile Log

/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:7114: SyntaxWarning: invalid escape sequence '\/'
  
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:7485: SyntaxWarning: invalid escape sequence '\d'
  )
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10680: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + "_WRITE" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10680: SyntaxWarning: invalid escape sequence '\s'
  r = f"\w+" + "_WRITE" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10682: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + "_WRITE_[0-9]+" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10682: SyntaxWarning: invalid escape sequence '\s'
  r = f"\w+" + "_WRITE_[0-9]+" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10688: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + "_READ" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10688: SyntaxWarning: invalid escape sequence '\s'
  r = f"\w+" + "_READ" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10690: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + "_READ_[0-9]+" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10690: SyntaxWarning: invalid escape sequence '\s'
  r = f"\w+" + "_READ_[0-9]+" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:272: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_SINGLE_INST.h"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:348: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_array(_[0-9]+)+_t"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:374: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_array_N_t.h"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:404: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_bytes_t.h"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:434: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + C_TO_FSM.FSM_EXT + ".h"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:526: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + C_TO_FSM.FSM_EXT
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:598: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_bytes_t"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:652: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_bytes_t"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:1469: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_array_[0-9]+_t"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:1902: SyntaxWarning: invalid escape sequence '\s'
  for type_regex in [f"uint[0-9]+_negate\s?\("]:  # DO int,float negate?
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:1963: SyntaxWarning: invalid escape sequence '\s'
  for type_regex in [f"int[0-9]+_abs\s?\("]:  # Float abs is bit manip func
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2049: SyntaxWarning: invalid escape sequence '\w'
  for type_regex in [f"\w+_mux[0-9]+\s?\("]:
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2245: SyntaxWarning: invalid escape sequence '\s'
  for type_regex in [f"count0s_uint[0-9]+\s?\("]:
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2474: SyntaxWarning: invalid escape sequence '\s'
  regex = type_regex + "_" + op_regex + f"[0-9]+\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2841: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_[0-9]+_[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2877: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"u?int[0-9]+_u?int[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2915: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"[^_][u?]int[0-9]+_[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2955: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"[^_]rotl[0-9]+_[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2988: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"[^_]rotr[0-9]+_[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:3023: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"u?int[0-9]+_uint[0-9]+_[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:3064: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_uint[0-9]+_uint[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:3110: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_uint[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:3147: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_abs\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:3183: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_sign\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:3215: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"bswap_[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:3249: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"uint[0-9]+_array[0-9]+_(?:be|le)\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SYN.py:1183: SyntaxWarning: invalid escape sequence '\/'
  

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Output directory: /submission/user/pipelinec_output
================== Parsing C Code to Logical Hierarchy ================================
Parsing: /submission/user/Solution.c
Preprocessing file...
Parsing C syntax...
Parsing non-function definitions...
Marking global variable center_bunker_vulnerable_pipeline_in_id as constant since never written...
Matching clock domain: main function center_bunker_vulnerable_pipeline based on shared global variable center_bunker_vulnerable_pipeline_in used with clock domain for main function sliding_window_process @ 0.001 MHz, Group: None
Parsing derived fsm logic functions...
Doing old-style code generation based on PipelineC supported text patterns...
... found: int1_array_and4
... found: uint1_array_and4
Elaborating function dataflow...
Defaulting to pyrtl based timing estimates...
Using PYRTL synthesizing for part: None
Elaborating dataflow of function: slide_window
Elaborating dataflow of function: line_fifo
Elaborating dataflow of function: sliding_window
Elaborating dataflow of function: center_bunker_vulnerable
Elaborating dataflow of function: center_bunker_vulnerable_pipeline
Elaborating dataflow of function: sliding_window_process
Elaborating dataflow of function: accum_pipeline_output
Elaborating user function hierarchies down to raw HDL logic...
... found: BIN_OP_LT_uint4_t_uint3_t
... found: BIN_OP_GTE_int9_t_int2_t
... found: BIN_OP_GTE_uint1_t_uint1_t
... found: BIN_OP_LTE_int9_t_int10_t
... found: BIN_OP_LTE_uint8_t_uint8_t
... found: BIN_OP_LT_int9_t_int10_t
... found: BIN_OP_LT_uint8_t_uint8_t
... found: BIN_OP_LTE_int9_t_int9_t
... found: BIN_OP_GTE_int9_t_int3_t
... found: BIN_OP_GTE_uint2_t_uint2_t
... found: BIN_OP_LT_int9_t_int9_t
... found: BIN_OP_LT_uint3_t_uint3_t
Doing obvious logic trimming/collapsing...
Writing generated PipelineC code from elaboration to output directories...
Writing cache of parsed information to file...
================== Writing Resulting Logic to File ================================
Writing output files before adding pipelining...
Writing log of integer module instances: /submission/user/pipelinec_output/integer_module_instances.log
Writing VHDL files for all functions (before any added pipelining)...
Writing multi main top level files...
Writing the constant struct+enum definitions as defined from C code...
Writing global wire definitions as parsed from C code...
================== Adding Timing Information from Synthesis Tool ================================
Synthesizing before pipelining to get path delays...

Synthesizing function: BIN_OP_PLUS_uint4_t_uint1_t
Synthesizing function: BIN_OP_EQ_uint1_t_uint1_t
Synthesizing function: MUX_uint1_t_uint1_t_uint1_t
Synthesizing function: BIN_OP_MINUS_int4_t_int4_t
Synthesizing function: BIN_OP_LT_uint4_t_uint3_t
Synthesizing function: BIN_OP_AND_uint1_t_uint1_t
Synthesizing function: center_bunker_vulnerable
Running: /submission/user/pipelinec_output/built_in/BIN_OP_PLUS_uint4_t_uint1_t/pyrtl_0CLK_de264c78.log
Synthesizing function: sliding_window
Running: /submission/user/pipelinec_output/built_in/MUX_uint1_t_uint1_t_uint1_t/pyrtl_0CLK_de264c78.log
Running: /submission/user/pipelinec_output/built_in/BIN_OP_EQ_uint1_t_uint1_t/pyrtl_0CLK_de264c78.log
Synthesizing function: center_bunker_vulnerable_pipeline
Synthesizing function: sliding_window_process
Synthesizing function: accum_pipeline_output
Function 28/38, elapsed time 0:00:19.430136...
...Waiting on synthesis for: BIN_OP_PLUS_uint4_t_uint1_t
Running: /submission/user/pipelinec_output/built_in/BIN_OP_MINUS_int4_t_int4_t/pyrtl_0CLK_de264c78.log
Running: /submission/user/pipelinec_output/built_in/BIN_OP_LT_uint4_t_uint3_t/pyrtl_0CLK_5af1a430.log
Running: /submission/user/pipelinec_output/built_in/BIN_OP_AND_uint1_t_uint1_t/pyrtl_0CLK_de264c78.log
BIN_OP_PLUS_uint4_t_uint1_t Path delay (maybe to be pipelined): 1.055 ns
Function 29/38, elapsed time 0:00:20.232458...
...Waiting on synthesis for: BIN_OP_EQ_uint1_t_uint1_t
BIN_OP_EQ_uint1_t_uint1_t Path delay (maybe to be pipelined): 0.505 ns
Function 30/38, elapsed time 0:00:20.233000...
...Waiting on synthesis for: MUX_uint1_t_uint1_t_uint1_t
MUX_uint1_t_uint1_t_uint1_t Path delay (maybe to be pipelined): 0.505 ns
Running: /submission/user/pipelinec_output/center_bunker_vulnerable/pyrtl_0CLK_6ad00a66.log
Function 31/38, elapsed time 0:00:20.233327...
...Waiting on synthesis for: BIN_OP_MINUS_int4_t_int4_t
BIN_OP_MINUS_int4_t_int4_t Path delay (maybe to be pipelined): 1.673 ns
Function 32/38, elapsed time 0:00:20.267969...
...Waiting on synthesis for: BIN_OP_LT_uint4_t_uint3_t
Running: /submission/user/pipelinec_output/sliding_window/pyrtl_0CLK_f144350a.log
Running: /submission/user/pipelinec_output/center_bunker_vulnerable_pipeline/pyrtl_0CLK_16f17d08.log
BIN_OP_LT_uint4_t_uint3_t Path delay (maybe to be pipelined): 2.081 ns
Function 33/38, elapsed time 0:00:21.269484...
...Waiting on synthesis for: BIN_OP_AND_uint1_t_uint1_t
BIN_OP_AND_uint1_t_uint1_t Path delay (maybe to be pipelined): 0.197 ns
Function 34/38, elapsed time 0:00:21.271362...
...Waiting on synthesis for: center_bunker_vulnerable
Running: /submission/user/pipelinec_output/sliding_window_process/pyrtl_0CLK_81b7b836.log
center_bunker_vulnerable Path delay (maybe to be pipelined): 6.609 ns
Function 35/38, elapsed time 0:00:21.639802...
...Waiting on synthesis for: sliding_window
Running: /submission/user/pipelinec_output/accum_pipeline_output/pyrtl_0CLK_d58ec462.log
sliding_window FMAX: 161.290 MHz (6.200 ns path delay)
Function 36/38, elapsed time 0:00:31.423098...
...Waiting on synthesis for: center_bunker_vulnerable_pipeline
center_bunker_vulnerable_pipeline Path delay (maybe to be pipelined): 6.885 ns
Function 37/38, elapsed time 0:00:31.423223...
...Waiting on synthesis for: sliding_window_process
sliding_window_process Path delay (maybe to be pipelined): 6.222 ns
Function 38/38, elapsed time 0:00:32.383647...
...Waiting on synthesis for: accum_pipeline_output
accum_pipeline_output FMAX: 243.902 MHz (4.100 ns path delay)
================== Beginning Throughput Sweep ================================
Function: center_bunker_vulnerable_pipeline Target MHz: 0.001
Function: sliding_window_process Target MHz: 0.001
Function: accum_pipeline_output Target MHz: 0.001
Starting with no added pipelining...
Starting with blank sweep state...
Starting middle out sweep...
Starting from timing params without added pipelining...
Collecting modules to pipeline...
Pipelining modules...
Updating output files...
Estimated register usage: /submission/user/pipelinec_output/solution/solution_e9a1_registers.log
Running syn w timing params...
Elapsed time: 0:00:32.415148...
Running: /submission/user/pipelinec_output/solution/pyrtl_e9a1.log
WARNING: No start reg name in timing report! Assuming all clock domains had critical paths...
accum_pipeline_output Clock Goal: 0.00 (MHz) Current: 145.25 (MHz)(6.88 ns) 0 clks
sliding_window_process Clock Goal: 0.00 (MHz) Current: 145.25 (MHz)(6.88 ns) 0 clks
center_bunker_vulnerable_pipeline Clock Goal: 0.00 (MHz) Current: 145.25 (MHz)(6.88 ns) 0 clks
Met timing...
================== Writing Results of Throughput Sweep ================================
Output VHDL files: /submission/user/pipelinec_output/vhdl_files.txt
Done.

Generated Verilog

module Solution(
    input clk,
    input reset,
    input i_valid,
    output i_ready,
    input i_payload_grid_fragment_fragment,
    input i_payload_grid_fragment_last,
    input i_payload_grid_last,
    output o_valid,
    output [15:0] o_payload
);

    wire [2:0] input_data;
    assign input_data = { i_payload_grid_last, i_payload_grid_fragment_last, i_payload_grid_fragment_fragment };

    wire [15:0] output_data;
    wire output_valid;
    wire output_input_ready;

    solution inner(
        .clk(clk),
        .\input[data] (input_data),
        .\input[valid] (i_valid),
        .\output[data] (output_data),
        .\output[valid] (output_valid),
        .input_ready(output_input_ready)
    );

    assign i_ready = output_input_ready;
    assign o_valid = output_valid;
    assign o_payload = output_data[15:0];

endmodule


/* Generated by Yosys 0.55 (git sha1 60f126cd00c94892782470192d6c9f7abebe7c05, g++ 14.3.0 -fPIC -O3) */

module accum_pipeline_output_0clk_d58ec462(clk, clock_enable, \global_to_module[center_bunker_vulnerable_pipeline_out_valid] , \global_to_module[center_bunker_vulnerable_pipeline_out] , \global_to_module[done_frame_pulse] , \module_to_global[output] );
  wire _00_;
  wire [2:0] _01_;
  wire _02_;
  wire _03_;
  wire [2:0] _04_;
  wire [3:0] _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire [15:0] _10_;
  wire [15:0] _11_;
  wire [16:0] _12_;
  wire [16:0] _13_;
  wire [15:0] _14_;
  reg [15:0] _15_ = 16'h0000;
  wire [2:0] _16_;
  reg [2:0] _17_ = 3'h0;
  wire _18_;
  reg _19_ = 1'h0;
  wire _20_;
  reg _21_ = 1'h0;
  wire [2:0] bin_op_eq_solution_c_l389_c18_5934_left;
  wire bin_op_eq_solution_c_l389_c18_5934_return_output;
  wire [1:0] bin_op_eq_solution_c_l389_c18_5934_right;
  wire [2:0] bin_op_lt_solution_c_l377_c8_1d60_left;
  wire bin_op_lt_solution_c_l377_c8_1d60_return_output;
  wire [2:0] bin_op_lt_solution_c_l377_c8_1d60_right;
  wire [2:0] bin_op_plus_solution_c_l378_c7_ff67_left;
  wire [3:0] bin_op_plus_solution_c_l378_c7_ff67_return_output;
  wire bin_op_plus_solution_c_l378_c7_ff67_right;
  wire [15:0] bin_op_plus_solution_c_l397_c5_0e37_left;
  wire [16:0] bin_op_plus_solution_c_l397_c5_0e37_return_output;
  wire bin_op_plus_solution_c_l397_c5_0e37_right;
  input clk;
  wire clk;
  wire clk_en_internal;
  input clock_enable;
  wire clock_enable;
  wire done_frame;
  wire done_frame_mux_solution_c_l376_c3_479b_cond;
  wire done_frame_mux_solution_c_l376_c3_479b_iffalse;
  wire done_frame_mux_solution_c_l376_c3_479b_iftrue;
  wire done_frame_mux_solution_c_l376_c3_479b_return_output;
  wire done_frame_mux_solution_c_l377_c5_5206_cond;
  wire done_frame_mux_solution_c_l377_c5_5206_iffalse;
  wire done_frame_mux_solution_c_l377_c5_5206_iftrue;
  wire done_frame_mux_solution_c_l377_c5_5206_return_output;
  wire done_frame_mux_solution_c_l384_c3_254a_cond;
  wire done_frame_mux_solution_c_l384_c3_254a_iffalse;
  wire done_frame_mux_solution_c_l384_c3_254a_iftrue;
  wire done_frame_mux_solution_c_l384_c3_254a_return_output;
  wire done_frame_mux_solution_c_l385_c5_f024_cond;
  wire done_frame_mux_solution_c_l385_c5_f024_iffalse;
  wire done_frame_mux_solution_c_l385_c5_f024_iftrue;
  wire done_frame_mux_solution_c_l385_c5_f024_return_output;
  wire done_frame_pulse_reg;
  input \global_to_module[center_bunker_vulnerable_pipeline_out] ;
  wire \global_to_module[center_bunker_vulnerable_pipeline_out] ;
  input \global_to_module[center_bunker_vulnerable_pipeline_out_valid] ;
  wire \global_to_module[center_bunker_vulnerable_pipeline_out_valid] ;
  input \global_to_module[done_frame_pulse] ;
  wire \global_to_module[done_frame_pulse] ;
  output [16:0] \module_to_global[output] ;
  wire [16:0] \module_to_global[output] ;
  wire [2:0] num_cycles_done_frame;
  wire num_cycles_done_frame_mux_solution_c_l376_c3_479b_cond;
  wire [2:0] num_cycles_done_frame_mux_solution_c_l376_c3_479b_iffalse;
  wire [2:0] num_cycles_done_frame_mux_solution_c_l376_c3_479b_iftrue;
  wire [2:0] num_cycles_done_frame_mux_solution_c_l376_c3_479b_return_output;
  wire num_cycles_done_frame_mux_solution_c_l377_c5_5206_cond;
  wire [2:0] num_cycles_done_frame_mux_solution_c_l377_c5_5206_iffalse;
  wire [2:0] num_cycles_done_frame_mux_solution_c_l377_c5_5206_iftrue;
  wire [2:0] num_cycles_done_frame_mux_solution_c_l377_c5_5206_return_output;
  wire reg_comb_done_frame;
  wire reg_comb_done_frame_pulse_reg;
  wire [2:0] reg_comb_num_cycles_done_frame;
  wire [15:0] reg_comb_total;
  wire [15:0] total;
  wire total_mux_solution_c_l394_c3_a493_cond;
  wire [15:0] total_mux_solution_c_l394_c3_a493_iffalse;
  wire [15:0] total_mux_solution_c_l394_c3_a493_iftrue;
  wire [15:0] total_mux_solution_c_l394_c3_a493_return_output;
  wire total_mux_solution_c_l396_c9_f704_cond;
  wire [15:0] total_mux_solution_c_l396_c9_f704_iffalse;
  wire [15:0] total_mux_solution_c_l396_c9_f704_iftrue;
  wire [15:0] total_mux_solution_c_l396_c9_f704_return_output;
  wire unary_op_not_solution_c_l384_c7_9257_expr;
  wire unary_op_not_solution_c_l384_c7_9257_return_output;
  assign _13_ = clk_en_internal ? { bin_op_eq_solution_c_l389_c18_5934_return_output, total } : 17'h00000;
  assign _14_ = clk_en_internal ? reg_comb_total : total;
  always @(posedge clk)
    _15_ <= _14_;
  assign _16_ = clk_en_internal ? reg_comb_num_cycles_done_frame : num_cycles_done_frame;
  always @(posedge clk)
    _17_ <= _16_;
  assign _18_ = clk_en_internal ? reg_comb_done_frame : done_frame;
  always @(posedge clk)
    _19_ <= _18_;
  assign _20_ = clk_en_internal ? reg_comb_done_frame_pulse_reg : done_frame_pulse_reg;
  always @(posedge clk)
    _21_ <= _20_;
  bin_op_eq_uint3_t_uint2_t_0clk_de264c78 bin_op_eq_solution_c_l389_c18_5934 (
    .left(bin_op_eq_solution_c_l389_c18_5934_left),
    .return_output(_09_),
    .right(bin_op_eq_solution_c_l389_c18_5934_right)
  );
  bin_op_lt_uint3_t_uint3_t_0clk_380ecc95 bin_op_lt_solution_c_l377_c8_1d60 (
    .left(bin_op_lt_solution_c_l377_c8_1d60_left),
    .return_output(_02_),
    .right(bin_op_lt_solution_c_l377_c8_1d60_right)
  );
  bin_op_plus_uint3_t_uint1_t_0clk_de264c78 bin_op_plus_solution_c_l378_c7_ff67 (
    .left(bin_op_plus_solution_c_l378_c7_ff67_left),
    .return_output(_05_),
    .right(bin_op_plus_solution_c_l378_c7_ff67_right)
  );
  bin_op_plus_uint16_t_uint1_t_0clk_de264c78 bin_op_plus_solution_c_l397_c5_0e37 (
    .left(bin_op_plus_solution_c_l397_c5_0e37_left),
    .return_output(_12_),
    .right(bin_op_plus_solution_c_l397_c5_0e37_right)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 done_frame_mux_solution_c_l376_c3_479b (
    .cond(done_frame_mux_solution_c_l376_c3_479b_cond),
    .iffalse(done_frame_mux_solution_c_l376_c3_479b_iffalse),
    .iftrue(done_frame_mux_solution_c_l376_c3_479b_iftrue),
    .return_output(_00_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 done_frame_mux_solution_c_l377_c5_5206 (
    .cond(done_frame_mux_solution_c_l377_c5_5206_cond),
    .iffalse(done_frame_mux_solution_c_l377_c5_5206_iffalse),
    .iftrue(done_frame_mux_solution_c_l377_c5_5206_iftrue),
    .return_output(_03_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 done_frame_mux_solution_c_l384_c3_254a (
    .cond(done_frame_mux_solution_c_l384_c3_254a_cond),
    .iffalse(done_frame_mux_solution_c_l384_c3_254a_iffalse),
    .iftrue(done_frame_mux_solution_c_l384_c3_254a_iftrue),
    .return_output(_07_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 done_frame_mux_solution_c_l385_c5_f024 (
    .cond(done_frame_mux_solution_c_l385_c5_f024_cond),
    .iffalse(done_frame_mux_solution_c_l385_c5_f024_iffalse),
    .iftrue(done_frame_mux_solution_c_l385_c5_f024_iftrue),
    .return_output(_08_)
  );
  mux_uint1_t_uint3_t_uint3_t_0clk_de264c78 num_cycles_done_frame_mux_solution_c_l376_c3_479b (
    .cond(num_cycles_done_frame_mux_solution_c_l376_c3_479b_cond),
    .iffalse(num_cycles_done_frame_mux_solution_c_l376_c3_479b_iffalse),
    .iftrue(num_cycles_done_frame_mux_solution_c_l376_c3_479b_iftrue),
    .return_output(_01_)
  );
  mux_uint1_t_uint3_t_uint3_t_0clk_de264c78 num_cycles_done_frame_mux_solution_c_l377_c5_5206 (
    .cond(num_cycles_done_frame_mux_solution_c_l377_c5_5206_cond),
    .iffalse(num_cycles_done_frame_mux_solution_c_l377_c5_5206_iffalse),
    .iftrue(num_cycles_done_frame_mux_solution_c_l377_c5_5206_iftrue),
    .return_output(_04_)
  );
  mux_uint1_t_uint16_t_uint16_t_0clk_de264c78 total_mux_solution_c_l394_c3_a493 (
    .cond(total_mux_solution_c_l394_c3_a493_cond),
    .iffalse(total_mux_solution_c_l394_c3_a493_iffalse),
    .iftrue(total_mux_solution_c_l394_c3_a493_iftrue),
    .return_output(_10_)
  );
  mux_uint1_t_uint16_t_uint16_t_0clk_de264c78 total_mux_solution_c_l396_c9_f704 (
    .cond(total_mux_solution_c_l396_c9_f704_cond),
    .iffalse(total_mux_solution_c_l396_c9_f704_iffalse),
    .iftrue(total_mux_solution_c_l396_c9_f704_iftrue),
    .return_output(_11_)
  );
  unary_op_not_uint1_t_0clk_de264c78 unary_op_not_solution_c_l384_c7_9257 (
    .expr(unary_op_not_solution_c_l384_c7_9257_expr),
    .return_output(_06_)
  );
  assign total = _15_;
  assign num_cycles_done_frame = _17_;
  assign done_frame = _19_;
  assign done_frame_pulse_reg = _21_;
  assign reg_comb_total = total_mux_solution_c_l394_c3_a493_return_output;
  assign reg_comb_num_cycles_done_frame = num_cycles_done_frame_mux_solution_c_l376_c3_479b_return_output;
  assign reg_comb_done_frame = done_frame_mux_solution_c_l384_c3_254a_return_output;
  assign reg_comb_done_frame_pulse_reg = \global_to_module[done_frame_pulse] ;
  assign clk_en_internal = clock_enable;
  assign done_frame_mux_solution_c_l376_c3_479b_cond = done_frame;
  assign done_frame_mux_solution_c_l376_c3_479b_iftrue = done_frame_mux_solution_c_l377_c5_5206_return_output;
  assign done_frame_mux_solution_c_l376_c3_479b_iffalse = done_frame;
  assign done_frame_mux_solution_c_l376_c3_479b_return_output = _00_;
  assign num_cycles_done_frame_mux_solution_c_l376_c3_479b_cond = done_frame;
  assign num_cycles_done_frame_mux_solution_c_l376_c3_479b_iftrue = num_cycles_done_frame_mux_solution_c_l377_c5_5206_return_output;
  assign num_cycles_done_frame_mux_solution_c_l376_c3_479b_iffalse = num_cycles_done_frame;
  assign num_cycles_done_frame_mux_solution_c_l376_c3_479b_return_output = _01_;
  assign bin_op_lt_solution_c_l377_c8_1d60_left = num_cycles_done_frame;
  assign bin_op_lt_solution_c_l377_c8_1d60_right = 3'h4;
  assign bin_op_lt_solution_c_l377_c8_1d60_return_output = _02_;
  assign done_frame_mux_solution_c_l377_c5_5206_cond = bin_op_lt_solution_c_l377_c8_1d60_return_output;
  assign done_frame_mux_solution_c_l377_c5_5206_iftrue = done_frame;
  assign done_frame_mux_solution_c_l377_c5_5206_iffalse = 1'h0;
  assign done_frame_mux_solution_c_l377_c5_5206_return_output = _03_;
  assign num_cycles_done_frame_mux_solution_c_l377_c5_5206_cond = bin_op_lt_solution_c_l377_c8_1d60_return_output;
  assign num_cycles_done_frame_mux_solution_c_l377_c5_5206_iftrue = bin_op_plus_solution_c_l378_c7_ff67_return_output[2:0];
  assign num_cycles_done_frame_mux_solution_c_l377_c5_5206_iffalse = 3'h0;
  assign num_cycles_done_frame_mux_solution_c_l377_c5_5206_return_output = _04_;
  assign bin_op_plus_solution_c_l378_c7_ff67_left = num_cycles_done_frame;
  assign bin_op_plus_solution_c_l378_c7_ff67_right = 1'h1;
  assign bin_op_plus_solution_c_l378_c7_ff67_return_output = _05_;
  assign unary_op_not_solution_c_l384_c7_9257_expr = done_frame_mux_solution_c_l376_c3_479b_return_output;
  assign unary_op_not_solution_c_l384_c7_9257_return_output = _06_;
  assign done_frame_mux_solution_c_l384_c3_254a_cond = unary_op_not_solution_c_l384_c7_9257_return_output;
  assign done_frame_mux_solution_c_l384_c3_254a_iftrue = done_frame_mux_solution_c_l385_c5_f024_return_output;
  assign done_frame_mux_solution_c_l384_c3_254a_iffalse = done_frame_mux_solution_c_l376_c3_479b_return_output;
  assign done_frame_mux_solution_c_l384_c3_254a_return_output = _07_;
  assign done_frame_mux_solution_c_l385_c5_f024_cond = done_frame_pulse_reg;
  assign done_frame_mux_solution_c_l385_c5_f024_iftrue = 1'h1;
  assign done_frame_mux_solution_c_l385_c5_f024_iffalse = done_frame_mux_solution_c_l376_c3_479b_return_output;
  assign done_frame_mux_solution_c_l385_c5_f024_return_output = _08_;
  assign bin_op_eq_solution_c_l389_c18_5934_left = num_cycles_done_frame_mux_solution_c_l376_c3_479b_return_output;
  assign bin_op_eq_solution_c_l389_c18_5934_right = 2'h3;
  assign bin_op_eq_solution_c_l389_c18_5934_return_output = _09_;
  assign total_mux_solution_c_l394_c3_a493_cond = bin_op_eq_solution_c_l389_c18_5934_return_output;
  assign total_mux_solution_c_l394_c3_a493_iftrue = 16'h0000;
  assign total_mux_solution_c_l394_c3_a493_iffalse = total_mux_solution_c_l396_c9_f704_return_output;
  assign total_mux_solution_c_l394_c3_a493_return_output = _10_;
  assign total_mux_solution_c_l396_c9_f704_cond = \global_to_module[center_bunker_vulnerable_pipeline_out_valid] ;
  assign total_mux_solution_c_l396_c9_f704_iftrue = bin_op_plus_solution_c_l397_c5_0e37_return_output[15:0];
  assign total_mux_solution_c_l396_c9_f704_iffalse = total;
  assign total_mux_solution_c_l396_c9_f704_return_output = _11_;
  assign bin_op_plus_solution_c_l397_c5_0e37_left = total;
  assign bin_op_plus_solution_c_l397_c5_0e37_right = \global_to_module[center_bunker_vulnerable_pipeline_out] ;
  assign bin_op_plus_solution_c_l397_c5_0e37_return_output = _12_;
  assign \module_to_global[output]  = _13_;
endmodule

module bin_op_and_uint1_t_uint1_t_0clk_de264c78(left, right, return_output);
  wire _0_;
  wire [4:0] \:1856.read_pipe ;
  input left;
  wire left;
  output return_output;
  wire return_output;
  input right;
  wire right;
  assign _0_ = left & right;
  assign \:1856.read_pipe  = { left, right, 3'hx };
  assign return_output = _0_;
endmodule

module bin_op_eq_uint1_t_uint1_t_0clk_de264c78(left, right, return_output);
  wire _0_;
  wire _1_;
  wire _2_;
  wire [5:0] \:2679.read_pipe ;
  input left;
  wire left;
  output return_output;
  wire return_output;
  input right;
  wire right;
  assign _0_ = left == right;
  assign _1_ = _0_ & 1'h1;
  assign _2_ = _1_ ? 1'h1 : 1'h0;
  assign \:2679.read_pipe  = { left, right, 4'bx011 };
  assign return_output = _2_;
endmodule

module bin_op_eq_uint2_t_uint2_t_0clk_de264c78(left, right, return_output);
  wire _0_;
  wire _1_;
  wire _2_;
  wire [9:0] \:2939.read_pipe ;
  input [1:0] left;
  wire [1:0] left;
  output return_output;
  wire return_output;
  input [1:0] right;
  wire [1:0] right;
  assign _0_ = left == right;
  assign _1_ = _0_ & 1'h1;
  assign _2_ = _1_ ? 1'h1 : 1'h0;
  assign \:2939.read_pipe  = { left, right, 6'bx01111 };
  assign return_output = _2_;
endmodule

module bin_op_eq_uint3_t_uint2_t_0clk_de264c78(left, right, return_output);
  wire _0_;
  wire _1_;
  wire _2_;
  wire [12:0] \:1630.read_pipe ;
  input [2:0] left;
  wire [2:0] left;
  output return_output;
  wire return_output;
  input [1:0] right;
  wire [1:0] right;
  assign _0_ = left == { 1'h0, right };
  assign _1_ = _0_ & 1'h1;
  assign _2_ = _1_ ? 1'h1 : 1'h0;
  assign \:1630.read_pipe  = { left, right, 8'bx0111111 };
  assign return_output = _2_;
endmodule

module bin_op_eq_uint7_t_uint7_t_0clk_de264c78(left, right, return_output);
  wire _0_;
  wire _1_;
  wire _2_;
  wire [29:0] \:3095.read_pipe ;
  input [6:0] left;
  wire [6:0] left;
  output return_output;
  wire return_output;
  input [6:0] right;
  wire [6:0] right;
  assign _0_ = left == right;
  assign _1_ = _0_ & 1'h1;
  assign _2_ = _1_ ? 1'h1 : 1'h0;
  assign \:3095.read_pipe  = { left, right, 16'bx011111111111111 };
  assign return_output = _2_;
endmodule

module bin_op_eq_uint8_t_uint8_t_0clk_de264c78(left, right, return_output);
  wire _0_;
  wire _1_;
  wire _2_;
  wire [33:0] \:2841.read_pipe ;
  input [7:0] left;
  wire [7:0] left;
  output return_output;
  wire return_output;
  input [7:0] right;
  wire [7:0] right;
  assign _0_ = left == right;
  assign _1_ = _0_ & 1'h1;
  assign _2_ = _1_ ? 1'h1 : 1'h0;
  assign \:2841.read_pipe  = { left, right, 18'bx01111111111111111 };
  assign return_output = _2_;
endmodule

module bin_op_gte_int9_t_int2_t_0clk_6b4fb28a(left, right, return_output);
  wire [8:0] _0_;
  wire [8:0] _1_;
  wire _2_;
  wire _3_;
  wire _4_;
  wire _5_;
  wire [7:0] bin_op_eq_bin_op_gte_int9_t_int2_t_c_l20_c8_1438_left;
  wire bin_op_eq_bin_op_gte_int9_t_int2_t_c_l20_c8_1438_return_output;
  wire [7:0] bin_op_eq_bin_op_gte_int9_t_int2_t_c_l20_c8_1438_right;
  wire bin_op_gte_bin_op_gte_int9_t_int2_t_c_l22_c14_9f54_left;
  wire bin_op_gte_bin_op_gte_int9_t_int2_t_c_l22_c14_9f54_return_output;
  wire bin_op_gte_bin_op_gte_int9_t_int2_t_c_l22_c14_9f54_right;
  wire [8:0] const_sr_1_bin_op_gte_int9_t_int2_t_c_l12_c31_9bfc_return_output;
  wire [8:0] const_sr_1_bin_op_gte_int9_t_int2_t_c_l12_c31_9bfc_x;
  wire [8:0] const_sr_1_bin_op_gte_int9_t_int2_t_c_l13_c34_11ac_return_output;
  wire [8:0] const_sr_1_bin_op_gte_int9_t_int2_t_c_l13_c34_11ac_x;
  input [8:0] left;
  wire [8:0] left;
  output return_output;
  wire return_output;
  input [1:0] right;
  wire [1:0] right;
  wire rv_mux_bin_op_gte_int9_t_int2_t_c_l20_c5_c4c7_cond;
  wire rv_mux_bin_op_gte_int9_t_int2_t_c_l20_c5_c4c7_iffalse;
  wire rv_mux_bin_op_gte_int9_t_int2_t_c_l20_c5_c4c7_iftrue;
  wire rv_mux_bin_op_gte_int9_t_int2_t_c_l20_c5_c4c7_return_output;
  wire unary_op_not_bin_op_gte_int9_t_int2_t_c_l28_c15_4ca0_expr;
  wire unary_op_not_bin_op_gte_int9_t_int2_t_c_l28_c15_4ca0_return_output;
  bin_op_eq_uint8_t_uint8_t_0clk_de264c78 bin_op_eq_bin_op_gte_int9_t_int2_t_c_l20_c8_1438 (
    .left(bin_op_eq_bin_op_gte_int9_t_int2_t_c_l20_c8_1438_left),
    .return_output(_2_),
    .right(bin_op_eq_bin_op_gte_int9_t_int2_t_c_l20_c8_1438_right)
  );
  bin_op_gte_uint1_t_uint1_t_0clk_6f2c5aad bin_op_gte_bin_op_gte_int9_t_int2_t_c_l22_c14_9f54 (
    .left(bin_op_gte_bin_op_gte_int9_t_int2_t_c_l22_c14_9f54_left),
    .return_output(_4_),
    .right(bin_op_gte_bin_op_gte_int9_t_int2_t_c_l22_c14_9f54_right)
  );
  const_sr_1_int9_t_0clk_de264c78 const_sr_1_bin_op_gte_int9_t_int2_t_c_l12_c31_9bfc (
    .return_output(_0_),
    .x(const_sr_1_bin_op_gte_int9_t_int2_t_c_l12_c31_9bfc_x)
  );
  const_sr_1_int9_t_0clk_de264c78 const_sr_1_bin_op_gte_int9_t_int2_t_c_l13_c34_11ac (
    .return_output(_1_),
    .x(const_sr_1_bin_op_gte_int9_t_int2_t_c_l13_c34_11ac_x)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 rv_mux_bin_op_gte_int9_t_int2_t_c_l20_c5_c4c7 (
    .cond(rv_mux_bin_op_gte_int9_t_int2_t_c_l20_c5_c4c7_cond),
    .iffalse(rv_mux_bin_op_gte_int9_t_int2_t_c_l20_c5_c4c7_iffalse),
    .iftrue(rv_mux_bin_op_gte_int9_t_int2_t_c_l20_c5_c4c7_iftrue),
    .return_output(_3_)
  );
  unary_op_not_uint1_t_0clk_de264c78 unary_op_not_bin_op_gte_int9_t_int2_t_c_l28_c15_4ca0 (
    .expr(unary_op_not_bin_op_gte_int9_t_int2_t_c_l28_c15_4ca0_expr),
    .return_output(_5_)
  );
  assign const_sr_1_bin_op_gte_int9_t_int2_t_c_l12_c31_9bfc_x = left;
  assign const_sr_1_bin_op_gte_int9_t_int2_t_c_l12_c31_9bfc_return_output = _0_;
  assign const_sr_1_bin_op_gte_int9_t_int2_t_c_l13_c34_11ac_x = { right[1], right[1], right[1], right[1], right[1], right[1], right[1], right };
  assign const_sr_1_bin_op_gte_int9_t_int2_t_c_l13_c34_11ac_return_output = _1_;
  assign bin_op_eq_bin_op_gte_int9_t_int2_t_c_l20_c8_1438_left = const_sr_1_bin_op_gte_int9_t_int2_t_c_l12_c31_9bfc_return_output[7:0];
  assign bin_op_eq_bin_op_gte_int9_t_int2_t_c_l20_c8_1438_right = const_sr_1_bin_op_gte_int9_t_int2_t_c_l13_c34_11ac_return_output[7:0];
  assign bin_op_eq_bin_op_gte_int9_t_int2_t_c_l20_c8_1438_return_output = _2_;
  assign rv_mux_bin_op_gte_int9_t_int2_t_c_l20_c5_c4c7_cond = bin_op_eq_bin_op_gte_int9_t_int2_t_c_l20_c8_1438_return_output;
  assign rv_mux_bin_op_gte_int9_t_int2_t_c_l20_c5_c4c7_iftrue = bin_op_gte_bin_op_gte_int9_t_int2_t_c_l22_c14_9f54_return_output;
  assign rv_mux_bin_op_gte_int9_t_int2_t_c_l20_c5_c4c7_iffalse = unary_op_not_bin_op_gte_int9_t_int2_t_c_l28_c15_4ca0_return_output;
  assign rv_mux_bin_op_gte_int9_t_int2_t_c_l20_c5_c4c7_return_output = _3_;
  assign bin_op_gte_bin_op_gte_int9_t_int2_t_c_l22_c14_9f54_left = left[0];
  assign bin_op_gte_bin_op_gte_int9_t_int2_t_c_l22_c14_9f54_right = right[0];
  assign bin_op_gte_bin_op_gte_int9_t_int2_t_c_l22_c14_9f54_return_output = _4_;
  assign unary_op_not_bin_op_gte_int9_t_int2_t_c_l28_c15_4ca0_expr = left[8];
  assign unary_op_not_bin_op_gte_int9_t_int2_t_c_l28_c15_4ca0_return_output = _5_;
  assign return_output = rv_mux_bin_op_gte_int9_t_int2_t_c_l20_c5_c4c7_return_output;
endmodule

module bin_op_gte_int9_t_int3_t_0clk_6b4fb28a(left, right, return_output);
  wire [8:0] _0_;
  wire [8:0] _1_;
  wire _2_;
  wire _3_;
  wire _4_;
  wire _5_;
  wire [6:0] bin_op_eq_bin_op_gte_int9_t_int3_t_c_l20_c8_8d26_left;
  wire bin_op_eq_bin_op_gte_int9_t_int3_t_c_l20_c8_8d26_return_output;
  wire [6:0] bin_op_eq_bin_op_gte_int9_t_int3_t_c_l20_c8_8d26_right;
  wire [1:0] bin_op_gte_bin_op_gte_int9_t_int3_t_c_l22_c14_5620_left;
  wire bin_op_gte_bin_op_gte_int9_t_int3_t_c_l22_c14_5620_return_output;
  wire [1:0] bin_op_gte_bin_op_gte_int9_t_int3_t_c_l22_c14_5620_right;
  wire [8:0] const_sr_2_bin_op_gte_int9_t_int3_t_c_l12_c31_7994_return_output;
  wire [8:0] const_sr_2_bin_op_gte_int9_t_int3_t_c_l12_c31_7994_x;
  wire [8:0] const_sr_2_bin_op_gte_int9_t_int3_t_c_l13_c34_2176_return_output;
  wire [8:0] const_sr_2_bin_op_gte_int9_t_int3_t_c_l13_c34_2176_x;
  input [8:0] left;
  wire [8:0] left;
  output return_output;
  wire return_output;
  input [2:0] right;
  wire [2:0] right;
  wire rv_mux_bin_op_gte_int9_t_int3_t_c_l20_c5_c912_cond;
  wire rv_mux_bin_op_gte_int9_t_int3_t_c_l20_c5_c912_iffalse;
  wire rv_mux_bin_op_gte_int9_t_int3_t_c_l20_c5_c912_iftrue;
  wire rv_mux_bin_op_gte_int9_t_int3_t_c_l20_c5_c912_return_output;
  wire unary_op_not_bin_op_gte_int9_t_int3_t_c_l28_c15_eff7_expr;
  wire unary_op_not_bin_op_gte_int9_t_int3_t_c_l28_c15_eff7_return_output;
  bin_op_eq_uint7_t_uint7_t_0clk_de264c78 bin_op_eq_bin_op_gte_int9_t_int3_t_c_l20_c8_8d26 (
    .left(bin_op_eq_bin_op_gte_int9_t_int3_t_c_l20_c8_8d26_left),
    .return_output(_2_),
    .right(bin_op_eq_bin_op_gte_int9_t_int3_t_c_l20_c8_8d26_right)
  );
  bin_op_gte_uint2_t_uint2_t_0clk_6f2c5aad bin_op_gte_bin_op_gte_int9_t_int3_t_c_l22_c14_5620 (
    .left(bin_op_gte_bin_op_gte_int9_t_int3_t_c_l22_c14_5620_left),
    .return_output(_4_),
    .right(bin_op_gte_bin_op_gte_int9_t_int3_t_c_l22_c14_5620_right)
  );
  const_sr_2_int9_t_0clk_de264c78 const_sr_2_bin_op_gte_int9_t_int3_t_c_l12_c31_7994 (
    .return_output(_0_),
    .x(const_sr_2_bin_op_gte_int9_t_int3_t_c_l12_c31_7994_x)
  );
  const_sr_2_int9_t_0clk_de264c78 const_sr_2_bin_op_gte_int9_t_int3_t_c_l13_c34_2176 (
    .return_output(_1_),
    .x(const_sr_2_bin_op_gte_int9_t_int3_t_c_l13_c34_2176_x)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 rv_mux_bin_op_gte_int9_t_int3_t_c_l20_c5_c912 (
    .cond(rv_mux_bin_op_gte_int9_t_int3_t_c_l20_c5_c912_cond),
    .iffalse(rv_mux_bin_op_gte_int9_t_int3_t_c_l20_c5_c912_iffalse),
    .iftrue(rv_mux_bin_op_gte_int9_t_int3_t_c_l20_c5_c912_iftrue),
    .return_output(_3_)
  );
  unary_op_not_uint1_t_0clk_de264c78 unary_op_not_bin_op_gte_int9_t_int3_t_c_l28_c15_eff7 (
    .expr(unary_op_not_bin_op_gte_int9_t_int3_t_c_l28_c15_eff7_expr),
    .return_output(_5_)
  );
  assign const_sr_2_bin_op_gte_int9_t_int3_t_c_l12_c31_7994_x = left;
  assign const_sr_2_bin_op_gte_int9_t_int3_t_c_l12_c31_7994_return_output = _0_;
  assign const_sr_2_bin_op_gte_int9_t_int3_t_c_l13_c34_2176_x = { right[2], right[2], right[2], right[2], right[2], right[2], right };
  assign const_sr_2_bin_op_gte_int9_t_int3_t_c_l13_c34_2176_return_output = _1_;
  assign bin_op_eq_bin_op_gte_int9_t_int3_t_c_l20_c8_8d26_left = const_sr_2_bin_op_gte_int9_t_int3_t_c_l12_c31_7994_return_output[6:0];
  assign bin_op_eq_bin_op_gte_int9_t_int3_t_c_l20_c8_8d26_right = const_sr_2_bin_op_gte_int9_t_int3_t_c_l13_c34_2176_return_output[6:0];
  assign bin_op_eq_bin_op_gte_int9_t_int3_t_c_l20_c8_8d26_return_output = _2_;
  assign rv_mux_bin_op_gte_int9_t_int3_t_c_l20_c5_c912_cond = bin_op_eq_bin_op_gte_int9_t_int3_t_c_l20_c8_8d26_return_output;
  assign rv_mux_bin_op_gte_int9_t_int3_t_c_l20_c5_c912_iftrue = bin_op_gte_bin_op_gte_int9_t_int3_t_c_l22_c14_5620_return_output;
  assign rv_mux_bin_op_gte_int9_t_int3_t_c_l20_c5_c912_iffalse = unary_op_not_bin_op_gte_int9_t_int3_t_c_l28_c15_eff7_return_output;
  assign rv_mux_bin_op_gte_int9_t_int3_t_c_l20_c5_c912_return_output = _3_;
  assign bin_op_gte_bin_op_gte_int9_t_int3_t_c_l22_c14_5620_left = left[1:0];
  assign bin_op_gte_bin_op_gte_int9_t_int3_t_c_l22_c14_5620_right = right[1:0];
  assign bin_op_gte_bin_op_gte_int9_t_int3_t_c_l22_c14_5620_return_output = _4_;
  assign unary_op_not_bin_op_gte_int9_t_int3_t_c_l28_c15_eff7_expr = left[8];
  assign unary_op_not_bin_op_gte_int9_t_int3_t_c_l28_c15_eff7_return_output = _5_;
  assign return_output = rv_mux_bin_op_gte_int9_t_int3_t_c_l20_c5_c912_return_output;
endmodule

module bin_op_gte_uint1_t_uint1_t_0clk_6f2c5aad(left, right, return_output);
  wire [2:0] _0_;
  wire _1_;
  wire [1:0] bin_op_minus_bin_op_gte_uint1_t_uint1_t_c_l14_c18_2601_left;
  wire [2:0] bin_op_minus_bin_op_gte_uint1_t_uint1_t_c_l14_c18_2601_return_output;
  wire [1:0] bin_op_minus_bin_op_gte_uint1_t_uint1_t_c_l14_c18_2601_right;
  input left;
  wire left;
  output return_output;
  wire return_output;
  input right;
  wire right;
  wire unary_op_not_bin_op_gte_uint1_t_uint1_t_c_l16_c11_fb7b_expr;
  wire unary_op_not_bin_op_gte_uint1_t_uint1_t_c_l16_c11_fb7b_return_output;
  bin_op_minus_int2_t_int2_t_0clk_de264c78 bin_op_minus_bin_op_gte_uint1_t_uint1_t_c_l14_c18_2601 (
    .left(bin_op_minus_bin_op_gte_uint1_t_uint1_t_c_l14_c18_2601_left),
    .return_output(_0_),
    .right(bin_op_minus_bin_op_gte_uint1_t_uint1_t_c_l14_c18_2601_right)
  );
  unary_op_not_uint1_t_0clk_de264c78 unary_op_not_bin_op_gte_uint1_t_uint1_t_c_l16_c11_fb7b (
    .expr(unary_op_not_bin_op_gte_uint1_t_uint1_t_c_l16_c11_fb7b_expr),
    .return_output(_1_)
  );
  assign bin_op_minus_bin_op_gte_uint1_t_uint1_t_c_l14_c18_2601_left = { 1'h0, left };
  assign bin_op_minus_bin_op_gte_uint1_t_uint1_t_c_l14_c18_2601_right = { 1'h0, right };
  assign bin_op_minus_bin_op_gte_uint1_t_uint1_t_c_l14_c18_2601_return_output = _0_;
  assign unary_op_not_bin_op_gte_uint1_t_uint1_t_c_l16_c11_fb7b_expr = bin_op_minus_bin_op_gte_uint1_t_uint1_t_c_l14_c18_2601_return_output[1];
  assign unary_op_not_bin_op_gte_uint1_t_uint1_t_c_l16_c11_fb7b_return_output = _1_;
  assign return_output = unary_op_not_bin_op_gte_uint1_t_uint1_t_c_l16_c11_fb7b_return_output;
endmodule

module bin_op_gte_uint2_t_uint2_t_0clk_6f2c5aad(left, right, return_output);
  wire [3:0] _0_;
  wire _1_;
  wire [2:0] bin_op_minus_bin_op_gte_uint2_t_uint2_t_c_l14_c18_9d04_left;
  wire [3:0] bin_op_minus_bin_op_gte_uint2_t_uint2_t_c_l14_c18_9d04_return_output;
  wire [2:0] bin_op_minus_bin_op_gte_uint2_t_uint2_t_c_l14_c18_9d04_right;
  input [1:0] left;
  wire [1:0] left;
  output return_output;
  wire return_output;
  input [1:0] right;
  wire [1:0] right;
  wire unary_op_not_bin_op_gte_uint2_t_uint2_t_c_l16_c11_ae64_expr;
  wire unary_op_not_bin_op_gte_uint2_t_uint2_t_c_l16_c11_ae64_return_output;
  bin_op_minus_int3_t_int3_t_0clk_de264c78 bin_op_minus_bin_op_gte_uint2_t_uint2_t_c_l14_c18_9d04 (
    .left(bin_op_minus_bin_op_gte_uint2_t_uint2_t_c_l14_c18_9d04_left),
    .return_output(_0_),
    .right(bin_op_minus_bin_op_gte_uint2_t_uint2_t_c_l14_c18_9d04_right)
  );
  unary_op_not_uint1_t_0clk_de264c78 unary_op_not_bin_op_gte_uint2_t_uint2_t_c_l16_c11_ae64 (
    .expr(unary_op_not_bin_op_gte_uint2_t_uint2_t_c_l16_c11_ae64_expr),
    .return_output(_1_)
  );
  assign bin_op_minus_bin_op_gte_uint2_t_uint2_t_c_l14_c18_9d04_left = { 1'h0, left };
  assign bin_op_minus_bin_op_gte_uint2_t_uint2_t_c_l14_c18_9d04_right = { 1'h0, right };
  assign bin_op_minus_bin_op_gte_uint2_t_uint2_t_c_l14_c18_9d04_return_output = _0_;
  assign unary_op_not_bin_op_gte_uint2_t_uint2_t_c_l16_c11_ae64_expr = bin_op_minus_bin_op_gte_uint2_t_uint2_t_c_l14_c18_9d04_return_output[2];
  assign unary_op_not_bin_op_gte_uint2_t_uint2_t_c_l16_c11_ae64_return_output = _1_;
  assign return_output = unary_op_not_bin_op_gte_uint2_t_uint2_t_c_l16_c11_ae64_return_output;
endmodule

module bin_op_lt_int9_t_int10_t_0clk_1aac2328(left, right, return_output);
  wire [9:0] _0_;
  wire [9:0] _1_;
  wire _2_;
  wire _3_;
  wire _4_;
  wire _5_;
  wire [1:0] bin_op_eq_bin_op_lt_int9_t_int10_t_c_l20_c8_7b60_left;
  wire bin_op_eq_bin_op_lt_int9_t_int10_t_c_l20_c8_7b60_return_output;
  wire [1:0] bin_op_eq_bin_op_lt_int9_t_int10_t_c_l20_c8_7b60_right;
  wire [7:0] bin_op_lt_bin_op_lt_int9_t_int10_t_c_l22_c14_7864_left;
  wire bin_op_lt_bin_op_lt_int9_t_int10_t_c_l22_c14_7864_return_output;
  wire [7:0] bin_op_lt_bin_op_lt_int9_t_int10_t_c_l22_c14_7864_right;
  wire [9:0] const_sr_8_bin_op_lt_int9_t_int10_t_c_l12_c31_de99_return_output;
  wire [9:0] const_sr_8_bin_op_lt_int9_t_int10_t_c_l12_c31_de99_x;
  wire [9:0] const_sr_8_bin_op_lt_int9_t_int10_t_c_l13_c34_c6bd_return_output;
  wire [9:0] const_sr_8_bin_op_lt_int9_t_int10_t_c_l13_c34_c6bd_x;
  input [8:0] left;
  wire [8:0] left;
  output return_output;
  wire return_output;
  input [9:0] right;
  wire [9:0] right;
  wire rv_mux_bin_op_lt_int9_t_int10_t_c_l20_c5_4763_cond;
  wire rv_mux_bin_op_lt_int9_t_int10_t_c_l20_c5_4763_iffalse;
  wire rv_mux_bin_op_lt_int9_t_int10_t_c_l20_c5_4763_iftrue;
  wire rv_mux_bin_op_lt_int9_t_int10_t_c_l20_c5_4763_return_output;
  wire unary_op_not_bin_op_lt_int9_t_int10_t_c_l28_c15_f35c_expr;
  wire unary_op_not_bin_op_lt_int9_t_int10_t_c_l28_c15_f35c_return_output;
  bin_op_eq_uint2_t_uint2_t_0clk_de264c78 bin_op_eq_bin_op_lt_int9_t_int10_t_c_l20_c8_7b60 (
    .left(bin_op_eq_bin_op_lt_int9_t_int10_t_c_l20_c8_7b60_left),
    .return_output(_2_),
    .right(bin_op_eq_bin_op_lt_int9_t_int10_t_c_l20_c8_7b60_right)
  );
  bin_op_lt_uint8_t_uint8_t_0clk_380ecc95 bin_op_lt_bin_op_lt_int9_t_int10_t_c_l22_c14_7864 (
    .left(bin_op_lt_bin_op_lt_int9_t_int10_t_c_l22_c14_7864_left),
    .return_output(_4_),
    .right(bin_op_lt_bin_op_lt_int9_t_int10_t_c_l22_c14_7864_right)
  );
  const_sr_8_int10_t_0clk_de264c78 const_sr_8_bin_op_lt_int9_t_int10_t_c_l12_c31_de99 (
    .return_output(_0_),
    .x(const_sr_8_bin_op_lt_int9_t_int10_t_c_l12_c31_de99_x)
  );
  const_sr_8_int10_t_0clk_de264c78 const_sr_8_bin_op_lt_int9_t_int10_t_c_l13_c34_c6bd (
    .return_output(_1_),
    .x(const_sr_8_bin_op_lt_int9_t_int10_t_c_l13_c34_c6bd_x)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 rv_mux_bin_op_lt_int9_t_int10_t_c_l20_c5_4763 (
    .cond(rv_mux_bin_op_lt_int9_t_int10_t_c_l20_c5_4763_cond),
    .iffalse(rv_mux_bin_op_lt_int9_t_int10_t_c_l20_c5_4763_iffalse),
    .iftrue(rv_mux_bin_op_lt_int9_t_int10_t_c_l20_c5_4763_iftrue),
    .return_output(_3_)
  );
  unary_op_not_uint1_t_0clk_de264c78 unary_op_not_bin_op_lt_int9_t_int10_t_c_l28_c15_f35c (
    .expr(unary_op_not_bin_op_lt_int9_t_int10_t_c_l28_c15_f35c_expr),
    .return_output(_5_)
  );
  assign const_sr_8_bin_op_lt_int9_t_int10_t_c_l12_c31_de99_x = right;
  assign const_sr_8_bin_op_lt_int9_t_int10_t_c_l12_c31_de99_return_output = _0_;
  assign const_sr_8_bin_op_lt_int9_t_int10_t_c_l13_c34_c6bd_x = { left[8], left };
  assign const_sr_8_bin_op_lt_int9_t_int10_t_c_l13_c34_c6bd_return_output = _1_;
  assign bin_op_eq_bin_op_lt_int9_t_int10_t_c_l20_c8_7b60_left = const_sr_8_bin_op_lt_int9_t_int10_t_c_l12_c31_de99_return_output[1:0];
  assign bin_op_eq_bin_op_lt_int9_t_int10_t_c_l20_c8_7b60_right = const_sr_8_bin_op_lt_int9_t_int10_t_c_l13_c34_c6bd_return_output[1:0];
  assign bin_op_eq_bin_op_lt_int9_t_int10_t_c_l20_c8_7b60_return_output = _2_;
  assign rv_mux_bin_op_lt_int9_t_int10_t_c_l20_c5_4763_cond = bin_op_eq_bin_op_lt_int9_t_int10_t_c_l20_c8_7b60_return_output;
  assign rv_mux_bin_op_lt_int9_t_int10_t_c_l20_c5_4763_iftrue = bin_op_lt_bin_op_lt_int9_t_int10_t_c_l22_c14_7864_return_output;
  assign rv_mux_bin_op_lt_int9_t_int10_t_c_l20_c5_4763_iffalse = unary_op_not_bin_op_lt_int9_t_int10_t_c_l28_c15_f35c_return_output;
  assign rv_mux_bin_op_lt_int9_t_int10_t_c_l20_c5_4763_return_output = _3_;
  assign bin_op_lt_bin_op_lt_int9_t_int10_t_c_l22_c14_7864_left = left[7:0];
  assign bin_op_lt_bin_op_lt_int9_t_int10_t_c_l22_c14_7864_right = right[7:0];
  assign bin_op_lt_bin_op_lt_int9_t_int10_t_c_l22_c14_7864_return_output = _4_;
  assign unary_op_not_bin_op_lt_int9_t_int10_t_c_l28_c15_f35c_expr = right[9];
  assign unary_op_not_bin_op_lt_int9_t_int10_t_c_l28_c15_f35c_return_output = _5_;
  assign return_output = rv_mux_bin_op_lt_int9_t_int10_t_c_l20_c5_4763_return_output;
endmodule

module bin_op_lt_int9_t_int9_t_0clk_794ce60a(left, right, return_output);
  wire [8:0] _0_;
  wire [8:0] _1_;
  wire _2_;
  wire _3_;
  wire _4_;
  wire bin_op_eq_bin_op_lt_int9_t_int9_t_c_l20_c8_6d33_left;
  wire bin_op_eq_bin_op_lt_int9_t_int9_t_c_l20_c8_6d33_return_output;
  wire bin_op_eq_bin_op_lt_int9_t_int9_t_c_l20_c8_6d33_right;
  wire [7:0] bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03_left;
  wire bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03_return_output;
  wire [7:0] bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03_right;
  wire [8:0] const_sr_8_bin_op_lt_int9_t_int9_t_c_l12_c31_5a74_return_output;
  wire [8:0] const_sr_8_bin_op_lt_int9_t_int9_t_c_l12_c31_5a74_x;
  wire [8:0] const_sr_8_bin_op_lt_int9_t_int9_t_c_l13_c34_5539_return_output;
  wire [8:0] const_sr_8_bin_op_lt_int9_t_int9_t_c_l13_c34_5539_x;
  input [8:0] left;
  wire [8:0] left;
  output return_output;
  wire return_output;
  input [8:0] right;
  wire [8:0] right;
  wire rv_mux_bin_op_lt_int9_t_int9_t_c_l20_c5_10d2_cond;
  wire rv_mux_bin_op_lt_int9_t_int9_t_c_l20_c5_10d2_iffalse;
  wire rv_mux_bin_op_lt_int9_t_int9_t_c_l20_c5_10d2_iftrue;
  wire rv_mux_bin_op_lt_int9_t_int9_t_c_l20_c5_10d2_return_output;
  bin_op_eq_uint1_t_uint1_t_0clk_de264c78 bin_op_eq_bin_op_lt_int9_t_int9_t_c_l20_c8_6d33 (
    .left(bin_op_eq_bin_op_lt_int9_t_int9_t_c_l20_c8_6d33_left),
    .return_output(_2_),
    .right(bin_op_eq_bin_op_lt_int9_t_int9_t_c_l20_c8_6d33_right)
  );
  bin_op_lt_uint8_t_uint8_t_0clk_380ecc95 bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03 (
    .left(bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03_left),
    .return_output(_4_),
    .right(bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03_right)
  );
  const_sr_8_int9_t_0clk_de264c78 const_sr_8_bin_op_lt_int9_t_int9_t_c_l12_c31_5a74 (
    .return_output(_0_),
    .x(const_sr_8_bin_op_lt_int9_t_int9_t_c_l12_c31_5a74_x)
  );
  const_sr_8_int9_t_0clk_de264c78 const_sr_8_bin_op_lt_int9_t_int9_t_c_l13_c34_5539 (
    .return_output(_1_),
    .x(const_sr_8_bin_op_lt_int9_t_int9_t_c_l13_c34_5539_x)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 rv_mux_bin_op_lt_int9_t_int9_t_c_l20_c5_10d2 (
    .cond(rv_mux_bin_op_lt_int9_t_int9_t_c_l20_c5_10d2_cond),
    .iffalse(rv_mux_bin_op_lt_int9_t_int9_t_c_l20_c5_10d2_iffalse),
    .iftrue(rv_mux_bin_op_lt_int9_t_int9_t_c_l20_c5_10d2_iftrue),
    .return_output(_3_)
  );
  assign const_sr_8_bin_op_lt_int9_t_int9_t_c_l12_c31_5a74_x = right;
  assign const_sr_8_bin_op_lt_int9_t_int9_t_c_l12_c31_5a74_return_output = _0_;
  assign const_sr_8_bin_op_lt_int9_t_int9_t_c_l13_c34_5539_x = left;
  assign const_sr_8_bin_op_lt_int9_t_int9_t_c_l13_c34_5539_return_output = _1_;
  assign bin_op_eq_bin_op_lt_int9_t_int9_t_c_l20_c8_6d33_left = const_sr_8_bin_op_lt_int9_t_int9_t_c_l12_c31_5a74_return_output[0];
  assign bin_op_eq_bin_op_lt_int9_t_int9_t_c_l20_c8_6d33_right = const_sr_8_bin_op_lt_int9_t_int9_t_c_l13_c34_5539_return_output[0];
  assign bin_op_eq_bin_op_lt_int9_t_int9_t_c_l20_c8_6d33_return_output = _2_;
  assign rv_mux_bin_op_lt_int9_t_int9_t_c_l20_c5_10d2_cond = bin_op_eq_bin_op_lt_int9_t_int9_t_c_l20_c8_6d33_return_output;
  assign rv_mux_bin_op_lt_int9_t_int9_t_c_l20_c5_10d2_iftrue = bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03_return_output;
  assign rv_mux_bin_op_lt_int9_t_int9_t_c_l20_c5_10d2_iffalse = left[8];
  assign rv_mux_bin_op_lt_int9_t_int9_t_c_l20_c5_10d2_return_output = _3_;
  assign bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03_left = left[7:0];
  assign bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03_right = right[7:0];
  assign bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03_return_output = _4_;
  assign return_output = rv_mux_bin_op_lt_int9_t_int9_t_c_l20_c5_10d2_return_output;
endmodule

module bin_op_lt_uint3_t_uint3_t_0clk_380ecc95(left, right, return_output);
  wire [4:0] _0_;
  wire [3:0] bin_op_minus_bin_op_lt_uint3_t_uint3_t_c_l14_c18_bd9b_left;
  wire [4:0] bin_op_minus_bin_op_lt_uint3_t_uint3_t_c_l14_c18_bd9b_return_output;
  wire [3:0] bin_op_minus_bin_op_lt_uint3_t_uint3_t_c_l14_c18_bd9b_right;
  input [2:0] left;
  wire [2:0] left;
  output return_output;
  wire return_output;
  input [2:0] right;
  wire [2:0] right;
  bin_op_minus_int4_t_int4_t_0clk_de264c78 bin_op_minus_bin_op_lt_uint3_t_uint3_t_c_l14_c18_bd9b (
    .left(bin_op_minus_bin_op_lt_uint3_t_uint3_t_c_l14_c18_bd9b_left),
    .return_output(_0_),
    .right(bin_op_minus_bin_op_lt_uint3_t_uint3_t_c_l14_c18_bd9b_right)
  );
  assign bin_op_minus_bin_op_lt_uint3_t_uint3_t_c_l14_c18_bd9b_left = { 1'h0, left };
  assign bin_op_minus_bin_op_lt_uint3_t_uint3_t_c_l14_c18_bd9b_right = { 1'h0, right };
  assign bin_op_minus_bin_op_lt_uint3_t_uint3_t_c_l14_c18_bd9b_return_output = _0_;
  assign return_output = bin_op_minus_bin_op_lt_uint3_t_uint3_t_c_l14_c18_bd9b_return_output[3];
endmodule

module bin_op_lt_uint4_t_uint3_t_0clk_5af1a430(left, right, return_output);
  wire [3:0] _0_;
  wire _1_;
  wire _2_;
  wire [4:0] _3_;
  wire bin_op_eq_bin_op_lt_uint4_t_uint3_t_c_l15_c6_c7bd_left;
  wire bin_op_eq_bin_op_lt_uint4_t_uint3_t_c_l15_c6_c7bd_return_output;
  wire bin_op_eq_bin_op_lt_uint4_t_uint3_t_c_l15_c6_c7bd_right;
  wire [3:0] bin_op_minus_bin_op_lt_uint4_t_uint3_t_c_l17_c18_65ab_left;
  wire [4:0] bin_op_minus_bin_op_lt_uint4_t_uint3_t_c_l17_c18_65ab_return_output;
  wire [3:0] bin_op_minus_bin_op_lt_uint4_t_uint3_t_c_l17_c18_65ab_right;
  wire [3:0] const_sr_3_bin_op_lt_uint4_t_uint3_t_c_l13_c9_6e80_return_output;
  wire [3:0] const_sr_3_bin_op_lt_uint4_t_uint3_t_c_l13_c9_6e80_x;
  input [3:0] left;
  wire [3:0] left;
  output return_output;
  wire return_output;
  input [2:0] right;
  wire [2:0] right;
  wire rv_mux_bin_op_lt_uint4_t_uint3_t_c_l15_c3_8114_cond;
  wire rv_mux_bin_op_lt_uint4_t_uint3_t_c_l15_c3_8114_iffalse;
  wire rv_mux_bin_op_lt_uint4_t_uint3_t_c_l15_c3_8114_iftrue;
  wire rv_mux_bin_op_lt_uint4_t_uint3_t_c_l15_c3_8114_return_output;
  bin_op_eq_uint1_t_uint1_t_0clk_de264c78 bin_op_eq_bin_op_lt_uint4_t_uint3_t_c_l15_c6_c7bd (
    .left(bin_op_eq_bin_op_lt_uint4_t_uint3_t_c_l15_c6_c7bd_left),
    .return_output(_1_),
    .right(bin_op_eq_bin_op_lt_uint4_t_uint3_t_c_l15_c6_c7bd_right)
  );
  bin_op_minus_int4_t_int4_t_0clk_de264c78 bin_op_minus_bin_op_lt_uint4_t_uint3_t_c_l17_c18_65ab (
    .left(bin_op_minus_bin_op_lt_uint4_t_uint3_t_c_l17_c18_65ab_left),
    .return_output(_3_),
    .right(bin_op_minus_bin_op_lt_uint4_t_uint3_t_c_l17_c18_65ab_right)
  );
  const_sr_3_uint4_t_0clk_de264c78 const_sr_3_bin_op_lt_uint4_t_uint3_t_c_l13_c9_6e80 (
    .return_output(_0_),
    .x(const_sr_3_bin_op_lt_uint4_t_uint3_t_c_l13_c9_6e80_x)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 rv_mux_bin_op_lt_uint4_t_uint3_t_c_l15_c3_8114 (
    .cond(rv_mux_bin_op_lt_uint4_t_uint3_t_c_l15_c3_8114_cond),
    .iffalse(rv_mux_bin_op_lt_uint4_t_uint3_t_c_l15_c3_8114_iffalse),
    .iftrue(rv_mux_bin_op_lt_uint4_t_uint3_t_c_l15_c3_8114_iftrue),
    .return_output(_2_)
  );
  assign const_sr_3_bin_op_lt_uint4_t_uint3_t_c_l13_c9_6e80_x = left;
  assign const_sr_3_bin_op_lt_uint4_t_uint3_t_c_l13_c9_6e80_return_output = _0_;
  assign bin_op_eq_bin_op_lt_uint4_t_uint3_t_c_l15_c6_c7bd_left = const_sr_3_bin_op_lt_uint4_t_uint3_t_c_l13_c9_6e80_return_output[0];
  assign bin_op_eq_bin_op_lt_uint4_t_uint3_t_c_l15_c6_c7bd_right = 1'h0;
  assign bin_op_eq_bin_op_lt_uint4_t_uint3_t_c_l15_c6_c7bd_return_output = _1_;
  assign rv_mux_bin_op_lt_uint4_t_uint3_t_c_l15_c3_8114_cond = bin_op_eq_bin_op_lt_uint4_t_uint3_t_c_l15_c6_c7bd_return_output;
  assign rv_mux_bin_op_lt_uint4_t_uint3_t_c_l15_c3_8114_iftrue = bin_op_minus_bin_op_lt_uint4_t_uint3_t_c_l17_c18_65ab_return_output[3];
  assign rv_mux_bin_op_lt_uint4_t_uint3_t_c_l15_c3_8114_iffalse = 1'h0;
  assign rv_mux_bin_op_lt_uint4_t_uint3_t_c_l15_c3_8114_return_output = _2_;
  assign bin_op_minus_bin_op_lt_uint4_t_uint3_t_c_l17_c18_65ab_left = { 1'h0, left[2:0] };
  assign bin_op_minus_bin_op_lt_uint4_t_uint3_t_c_l17_c18_65ab_right = { 1'h0, right };
  assign bin_op_minus_bin_op_lt_uint4_t_uint3_t_c_l17_c18_65ab_return_output = _3_;
  assign return_output = rv_mux_bin_op_lt_uint4_t_uint3_t_c_l15_c3_8114_return_output;
endmodule

module bin_op_lt_uint8_t_uint8_t_0clk_380ecc95(left, right, return_output);
  wire [9:0] _0_;
  wire [8:0] bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42_left;
  wire [9:0] bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42_return_output;
  wire [8:0] bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42_right;
  input [7:0] left;
  wire [7:0] left;
  output return_output;
  wire return_output;
  input [7:0] right;
  wire [7:0] right;
  bin_op_minus_int9_t_int9_t_0clk_de264c78 bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42 (
    .left(bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42_left),
    .return_output(_0_),
    .right(bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42_right)
  );
  assign bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42_left = { 1'h0, left };
  assign bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42_right = { 1'h0, right };
  assign bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42_return_output = _0_;
  assign return_output = bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42_return_output[8];
endmodule

module bin_op_lte_int9_t_int10_t_0clk_6b4fb28a(left, right, return_output);
  wire [9:0] _0_;
  wire [9:0] _1_;
  wire _2_;
  wire _3_;
  wire _4_;
  wire _5_;
  wire [1:0] bin_op_eq_bin_op_lte_int9_t_int10_t_c_l20_c8_8030_left;
  wire bin_op_eq_bin_op_lte_int9_t_int10_t_c_l20_c8_8030_return_output;
  wire [1:0] bin_op_eq_bin_op_lte_int9_t_int10_t_c_l20_c8_8030_right;
  wire [7:0] bin_op_lte_bin_op_lte_int9_t_int10_t_c_l22_c14_0767_left;
  wire bin_op_lte_bin_op_lte_int9_t_int10_t_c_l22_c14_0767_return_output;
  wire [7:0] bin_op_lte_bin_op_lte_int9_t_int10_t_c_l22_c14_0767_right;
  wire [9:0] const_sr_8_bin_op_lte_int9_t_int10_t_c_l12_c31_e9a8_return_output;
  wire [9:0] const_sr_8_bin_op_lte_int9_t_int10_t_c_l12_c31_e9a8_x;
  wire [9:0] const_sr_8_bin_op_lte_int9_t_int10_t_c_l13_c34_7e68_return_output;
  wire [9:0] const_sr_8_bin_op_lte_int9_t_int10_t_c_l13_c34_7e68_x;
  input [8:0] left;
  wire [8:0] left;
  output return_output;
  wire return_output;
  input [9:0] right;
  wire [9:0] right;
  wire rv_mux_bin_op_lte_int9_t_int10_t_c_l20_c5_3055_cond;
  wire rv_mux_bin_op_lte_int9_t_int10_t_c_l20_c5_3055_iffalse;
  wire rv_mux_bin_op_lte_int9_t_int10_t_c_l20_c5_3055_iftrue;
  wire rv_mux_bin_op_lte_int9_t_int10_t_c_l20_c5_3055_return_output;
  wire unary_op_not_bin_op_lte_int9_t_int10_t_c_l28_c15_366a_expr;
  wire unary_op_not_bin_op_lte_int9_t_int10_t_c_l28_c15_366a_return_output;
  bin_op_eq_uint2_t_uint2_t_0clk_de264c78 bin_op_eq_bin_op_lte_int9_t_int10_t_c_l20_c8_8030 (
    .left(bin_op_eq_bin_op_lte_int9_t_int10_t_c_l20_c8_8030_left),
    .return_output(_2_),
    .right(bin_op_eq_bin_op_lte_int9_t_int10_t_c_l20_c8_8030_right)
  );
  bin_op_lte_uint8_t_uint8_t_0clk_6f2c5aad bin_op_lte_bin_op_lte_int9_t_int10_t_c_l22_c14_0767 (
    .left(bin_op_lte_bin_op_lte_int9_t_int10_t_c_l22_c14_0767_left),
    .return_output(_4_),
    .right(bin_op_lte_bin_op_lte_int9_t_int10_t_c_l22_c14_0767_right)
  );
  const_sr_8_int10_t_0clk_de264c78 const_sr_8_bin_op_lte_int9_t_int10_t_c_l12_c31_e9a8 (
    .return_output(_0_),
    .x(const_sr_8_bin_op_lte_int9_t_int10_t_c_l12_c31_e9a8_x)
  );
  const_sr_8_int10_t_0clk_de264c78 const_sr_8_bin_op_lte_int9_t_int10_t_c_l13_c34_7e68 (
    .return_output(_1_),
    .x(const_sr_8_bin_op_lte_int9_t_int10_t_c_l13_c34_7e68_x)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 rv_mux_bin_op_lte_int9_t_int10_t_c_l20_c5_3055 (
    .cond(rv_mux_bin_op_lte_int9_t_int10_t_c_l20_c5_3055_cond),
    .iffalse(rv_mux_bin_op_lte_int9_t_int10_t_c_l20_c5_3055_iffalse),
    .iftrue(rv_mux_bin_op_lte_int9_t_int10_t_c_l20_c5_3055_iftrue),
    .return_output(_3_)
  );
  unary_op_not_uint1_t_0clk_de264c78 unary_op_not_bin_op_lte_int9_t_int10_t_c_l28_c15_366a (
    .expr(unary_op_not_bin_op_lte_int9_t_int10_t_c_l28_c15_366a_expr),
    .return_output(_5_)
  );
  assign const_sr_8_bin_op_lte_int9_t_int10_t_c_l12_c31_e9a8_x = right;
  assign const_sr_8_bin_op_lte_int9_t_int10_t_c_l12_c31_e9a8_return_output = _0_;
  assign const_sr_8_bin_op_lte_int9_t_int10_t_c_l13_c34_7e68_x = { left[8], left };
  assign const_sr_8_bin_op_lte_int9_t_int10_t_c_l13_c34_7e68_return_output = _1_;
  assign bin_op_eq_bin_op_lte_int9_t_int10_t_c_l20_c8_8030_left = const_sr_8_bin_op_lte_int9_t_int10_t_c_l12_c31_e9a8_return_output[1:0];
  assign bin_op_eq_bin_op_lte_int9_t_int10_t_c_l20_c8_8030_right = const_sr_8_bin_op_lte_int9_t_int10_t_c_l13_c34_7e68_return_output[1:0];
  assign bin_op_eq_bin_op_lte_int9_t_int10_t_c_l20_c8_8030_return_output = _2_;
  assign rv_mux_bin_op_lte_int9_t_int10_t_c_l20_c5_3055_cond = bin_op_eq_bin_op_lte_int9_t_int10_t_c_l20_c8_8030_return_output;
  assign rv_mux_bin_op_lte_int9_t_int10_t_c_l20_c5_3055_iftrue = bin_op_lte_bin_op_lte_int9_t_int10_t_c_l22_c14_0767_return_output;
  assign rv_mux_bin_op_lte_int9_t_int10_t_c_l20_c5_3055_iffalse = unary_op_not_bin_op_lte_int9_t_int10_t_c_l28_c15_366a_return_output;
  assign rv_mux_bin_op_lte_int9_t_int10_t_c_l20_c5_3055_return_output = _3_;
  assign bin_op_lte_bin_op_lte_int9_t_int10_t_c_l22_c14_0767_left = left[7:0];
  assign bin_op_lte_bin_op_lte_int9_t_int10_t_c_l22_c14_0767_right = right[7:0];
  assign bin_op_lte_bin_op_lte_int9_t_int10_t_c_l22_c14_0767_return_output = _4_;
  assign unary_op_not_bin_op_lte_int9_t_int10_t_c_l28_c15_366a_expr = right[9];
  assign unary_op_not_bin_op_lte_int9_t_int10_t_c_l28_c15_366a_return_output = _5_;
  assign return_output = rv_mux_bin_op_lte_int9_t_int10_t_c_l20_c5_3055_return_output;
endmodule

module bin_op_lte_int9_t_int9_t_0clk_4f202194(left, right, return_output);
  wire [8:0] _0_;
  wire [8:0] _1_;
  wire _2_;
  wire _3_;
  wire _4_;
  wire bin_op_eq_bin_op_lte_int9_t_int9_t_c_l20_c8_d315_left;
  wire bin_op_eq_bin_op_lte_int9_t_int9_t_c_l20_c8_d315_return_output;
  wire bin_op_eq_bin_op_lte_int9_t_int9_t_c_l20_c8_d315_right;
  wire [7:0] bin_op_lte_bin_op_lte_int9_t_int9_t_c_l22_c14_5e81_left;
  wire bin_op_lte_bin_op_lte_int9_t_int9_t_c_l22_c14_5e81_return_output;
  wire [7:0] bin_op_lte_bin_op_lte_int9_t_int9_t_c_l22_c14_5e81_right;
  wire [8:0] const_sr_8_bin_op_lte_int9_t_int9_t_c_l12_c31_6344_return_output;
  wire [8:0] const_sr_8_bin_op_lte_int9_t_int9_t_c_l12_c31_6344_x;
  wire [8:0] const_sr_8_bin_op_lte_int9_t_int9_t_c_l13_c34_76e0_return_output;
  wire [8:0] const_sr_8_bin_op_lte_int9_t_int9_t_c_l13_c34_76e0_x;
  input [8:0] left;
  wire [8:0] left;
  output return_output;
  wire return_output;
  input [8:0] right;
  wire [8:0] right;
  wire rv_mux_bin_op_lte_int9_t_int9_t_c_l20_c5_0117_cond;
  wire rv_mux_bin_op_lte_int9_t_int9_t_c_l20_c5_0117_iffalse;
  wire rv_mux_bin_op_lte_int9_t_int9_t_c_l20_c5_0117_iftrue;
  wire rv_mux_bin_op_lte_int9_t_int9_t_c_l20_c5_0117_return_output;
  bin_op_eq_uint1_t_uint1_t_0clk_de264c78 bin_op_eq_bin_op_lte_int9_t_int9_t_c_l20_c8_d315 (
    .left(bin_op_eq_bin_op_lte_int9_t_int9_t_c_l20_c8_d315_left),
    .return_output(_2_),
    .right(bin_op_eq_bin_op_lte_int9_t_int9_t_c_l20_c8_d315_right)
  );
  bin_op_lte_uint8_t_uint8_t_0clk_6f2c5aad bin_op_lte_bin_op_lte_int9_t_int9_t_c_l22_c14_5e81 (
    .left(bin_op_lte_bin_op_lte_int9_t_int9_t_c_l22_c14_5e81_left),
    .return_output(_4_),
    .right(bin_op_lte_bin_op_lte_int9_t_int9_t_c_l22_c14_5e81_right)
  );
  const_sr_8_int9_t_0clk_de264c78 const_sr_8_bin_op_lte_int9_t_int9_t_c_l12_c31_6344 (
    .return_output(_0_),
    .x(const_sr_8_bin_op_lte_int9_t_int9_t_c_l12_c31_6344_x)
  );
  const_sr_8_int9_t_0clk_de264c78 const_sr_8_bin_op_lte_int9_t_int9_t_c_l13_c34_76e0 (
    .return_output(_1_),
    .x(const_sr_8_bin_op_lte_int9_t_int9_t_c_l13_c34_76e0_x)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 rv_mux_bin_op_lte_int9_t_int9_t_c_l20_c5_0117 (
    .cond(rv_mux_bin_op_lte_int9_t_int9_t_c_l20_c5_0117_cond),
    .iffalse(rv_mux_bin_op_lte_int9_t_int9_t_c_l20_c5_0117_iffalse),
    .iftrue(rv_mux_bin_op_lte_int9_t_int9_t_c_l20_c5_0117_iftrue),
    .return_output(_3_)
  );
  assign const_sr_8_bin_op_lte_int9_t_int9_t_c_l12_c31_6344_x = right;
  assign const_sr_8_bin_op_lte_int9_t_int9_t_c_l12_c31_6344_return_output = _0_;
  assign const_sr_8_bin_op_lte_int9_t_int9_t_c_l13_c34_76e0_x = left;
  assign const_sr_8_bin_op_lte_int9_t_int9_t_c_l13_c34_76e0_return_output = _1_;
  assign bin_op_eq_bin_op_lte_int9_t_int9_t_c_l20_c8_d315_left = const_sr_8_bin_op_lte_int9_t_int9_t_c_l12_c31_6344_return_output[0];
  assign bin_op_eq_bin_op_lte_int9_t_int9_t_c_l20_c8_d315_right = const_sr_8_bin_op_lte_int9_t_int9_t_c_l13_c34_76e0_return_output[0];
  assign bin_op_eq_bin_op_lte_int9_t_int9_t_c_l20_c8_d315_return_output = _2_;
  assign rv_mux_bin_op_lte_int9_t_int9_t_c_l20_c5_0117_cond = bin_op_eq_bin_op_lte_int9_t_int9_t_c_l20_c8_d315_return_output;
  assign rv_mux_bin_op_lte_int9_t_int9_t_c_l20_c5_0117_iftrue = bin_op_lte_bin_op_lte_int9_t_int9_t_c_l22_c14_5e81_return_output;
  assign rv_mux_bin_op_lte_int9_t_int9_t_c_l20_c5_0117_iffalse = left[8];
  assign rv_mux_bin_op_lte_int9_t_int9_t_c_l20_c5_0117_return_output = _3_;
  assign bin_op_lte_bin_op_lte_int9_t_int9_t_c_l22_c14_5e81_left = left[7:0];
  assign bin_op_lte_bin_op_lte_int9_t_int9_t_c_l22_c14_5e81_right = right[7:0];
  assign bin_op_lte_bin_op_lte_int9_t_int9_t_c_l22_c14_5e81_return_output = _4_;
  assign return_output = rv_mux_bin_op_lte_int9_t_int9_t_c_l20_c5_0117_return_output;
endmodule

module bin_op_lte_uint8_t_uint8_t_0clk_6f2c5aad(left, right, return_output);
  wire [9:0] _0_;
  wire _1_;
  wire [8:0] bin_op_minus_bin_op_lte_uint8_t_uint8_t_c_l14_c18_0d96_left;
  wire [9:0] bin_op_minus_bin_op_lte_uint8_t_uint8_t_c_l14_c18_0d96_return_output;
  wire [8:0] bin_op_minus_bin_op_lte_uint8_t_uint8_t_c_l14_c18_0d96_right;
  input [7:0] left;
  wire [7:0] left;
  output return_output;
  wire return_output;
  input [7:0] right;
  wire [7:0] right;
  wire unary_op_not_bin_op_lte_uint8_t_uint8_t_c_l16_c11_b6e1_expr;
  wire unary_op_not_bin_op_lte_uint8_t_uint8_t_c_l16_c11_b6e1_return_output;
  bin_op_minus_int9_t_int9_t_0clk_de264c78 bin_op_minus_bin_op_lte_uint8_t_uint8_t_c_l14_c18_0d96 (
    .left(bin_op_minus_bin_op_lte_uint8_t_uint8_t_c_l14_c18_0d96_left),
    .return_output(_0_),
    .right(bin_op_minus_bin_op_lte_uint8_t_uint8_t_c_l14_c18_0d96_right)
  );
  unary_op_not_uint1_t_0clk_de264c78 unary_op_not_bin_op_lte_uint8_t_uint8_t_c_l16_c11_b6e1 (
    .expr(unary_op_not_bin_op_lte_uint8_t_uint8_t_c_l16_c11_b6e1_expr),
    .return_output(_1_)
  );
  assign bin_op_minus_bin_op_lte_uint8_t_uint8_t_c_l14_c18_0d96_left = { 1'h0, right };
  assign bin_op_minus_bin_op_lte_uint8_t_uint8_t_c_l14_c18_0d96_right = { 1'h0, left };
  assign bin_op_minus_bin_op_lte_uint8_t_uint8_t_c_l14_c18_0d96_return_output = _0_;
  assign unary_op_not_bin_op_lte_uint8_t_uint8_t_c_l16_c11_b6e1_expr = bin_op_minus_bin_op_lte_uint8_t_uint8_t_c_l14_c18_0d96_return_output[8];
  assign unary_op_not_bin_op_lte_uint8_t_uint8_t_c_l16_c11_b6e1_return_output = _1_;
  assign return_output = unary_op_not_bin_op_lte_uint8_t_uint8_t_c_l16_c11_b6e1_return_output;
endmodule

module bin_op_minus_int2_t_int2_t_0clk_de264c78(left, right, return_output);
  wire [2:0] _0_;
  wire [2:0] _1_;
  wire [21:0] \:3174.read_pipe ;
  input [1:0] left;
  wire [1:0] left;
  output [2:0] return_output;
  wire [2:0] return_output;
  input [1:0] right;
  wire [1:0] right;
  assign _0_ = { left[1], left } - { right[1], right };
  assign _1_ = _0_ - 3'h0;
  assign \:3174.read_pipe  = { left, right, 18'hxxxxx };
  assign return_output = _1_;
endmodule

module bin_op_minus_int3_t_int3_t_0clk_de264c78(left, right, return_output);
  wire [3:0] _0_;
  wire [3:0] _1_;
  wire [30:0] \:3294.read_pipe ;
  input [2:0] left;
  wire [2:0] left;
  output [3:0] return_output;
  wire [3:0] return_output;
  input [2:0] right;
  wire [2:0] right;
  assign _0_ = { left[2], left } - { right[2], right };
  assign _1_ = _0_ - 4'h0;
  assign \:3294.read_pipe  = { left, right, 25'hxxxxxxx };
  assign return_output = _1_;
endmodule

module bin_op_minus_int4_t_int4_t_0clk_de264c78(left, right, return_output);
  wire [4:0] _0_;
  wire [4:0] _1_;
  wire [39:0] \:2600.read_pipe ;
  input [3:0] left;
  wire [3:0] left;
  output [4:0] return_output;
  wire [4:0] return_output;
  input [3:0] right;
  wire [3:0] right;
  assign _0_ = { left[3], left } - { right[3], right };
  assign _1_ = _0_ - 5'h00;
  assign \:2600.read_pipe  = { left, right, 32'hxxxxxxxx };
  assign return_output = _1_;
endmodule

module bin_op_minus_int9_t_int2_t_0clk_de264c78(left, right, return_output);
  wire [9:0] _0_;
  wire [9:0] _1_;
  wire [77:0] \:2223.read_pipe ;
  input [8:0] left;
  wire [8:0] left;
  output [9:0] return_output;
  wire [9:0] return_output;
  input [1:0] right;
  wire [1:0] right;
  assign _0_ = { left[8], left } - { right[1], right[1], right[1], right[1], right[1], right[1], right[1], right[1], right };
  assign _1_ = _0_ - 10'h000;
  assign \:2223.read_pipe  = { left, right, 67'hxxxxxxxxxxxxxxxxx };
  assign return_output = _1_;
endmodule

module bin_op_minus_int9_t_int3_t_0clk_de264c78(left, right, return_output);
  wire [9:0] _0_;
  wire [9:0] _1_;
  wire [78:0] \:2104.read_pipe ;
  input [8:0] left;
  wire [8:0] left;
  output [9:0] return_output;
  wire [9:0] return_output;
  input [2:0] right;
  wire [2:0] right;
  assign _0_ = { left[8], left } - { right[2], right[2], right[2], right[2], right[2], right[2], right[2], right };
  assign _1_ = _0_ - 10'h000;
  assign \:2104.read_pipe  = { left, right, 67'hxxxxxxxxxxxxxxxxx };
  assign return_output = _1_;
endmodule

module bin_op_minus_int9_t_int9_t_0clk_de264c78(left, right, return_output);
  wire [9:0] _0_;
  wire [9:0] _1_;
  wire [84:0] \:3234.read_pipe ;
  input [8:0] left;
  wire [8:0] left;
  output [9:0] return_output;
  wire [9:0] return_output;
  input [8:0] right;
  wire [8:0] right;
  assign _0_ = { left[8], left } - { right[8], right };
  assign _1_ = _0_ - 10'h000;
  assign \:3234.read_pipe  = { left, right, 67'hxxxxxxxxxxxxxxxxx };
  assign return_output = _1_;
endmodule

module bin_op_or_uint1_t_uint1_t_0clk_de264c78(left, right, return_output);
  wire _0_;
  wire [4:0] \:1989.read_pipe ;
  input left;
  wire left;
  output return_output;
  wire return_output;
  input right;
  wire right;
  assign _0_ = left | right;
  assign \:1989.read_pipe  = { left, right, 3'hx };
  assign return_output = _0_;
endmodule

module bin_op_plus_int9_t_int2_t_0clk_de264c78(left, right, return_output);
  wire [10:0] _0_;
  wire [10:0] _1_;
  wire [83:0] \:1904.read_pipe ;
  input [8:0] left;
  wire [8:0] left;
  output [9:0] return_output;
  wire [9:0] return_output;
  input [1:0] right;
  wire [1:0] right;
  assign _0_ = { 1'h0, left[8], left } + { 1'h0, right[1], right[1], right[1], right[1], right[1], right[1], right[1], right[1], right };
  assign _1_ = _0_ + 11'h000;
  assign \:1904.read_pipe  = { left, right, 73'hxxxxxxxxxxxxxxxxxxx };
  assign return_output = _1_[9:0];
endmodule

module bin_op_plus_uint16_t_uint1_t_0clk_de264c78(left, right, return_output);
  wire [16:0] _0_;
  wire [132:0] \:1690.read_pipe ;
  input [15:0] left;
  wire [15:0] left;
  output [16:0] return_output;
  wire [16:0] return_output;
  input right;
  wire right;
  assign _0_ = { 1'h0, left } + { 16'h0000, right };
  assign \:1690.read_pipe  = { left, right, 116'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxx };
  assign return_output = _0_;
endmodule

module bin_op_plus_uint3_t_uint1_t_0clk_de264c78(left, right, return_output);
  wire [3:0] _0_;
  wire [28:0] \:1556.read_pipe ;
  input [2:0] left;
  wire [2:0] left;
  output [3:0] return_output;
  wire [3:0] return_output;
  input right;
  wire right;
  assign _0_ = { 1'h0, left } + { 3'h0, right };
  assign \:1556.read_pipe  = { left, right, 25'hxxxxxxx };
  assign return_output = _0_;
endmodule

module bin_op_plus_uint4_t_uint1_t_0clk_de264c78(left, right, return_output);
  wire [4:0] _0_;
  wire [36:0] \:1743.read_pipe ;
  input [3:0] left;
  wire [3:0] left;
  output [4:0] return_output;
  wire [4:0] return_output;
  input right;
  wire right;
  assign _0_ = { 1'h0, left } + { 4'h0, right };
  assign \:1743.read_pipe  = { left, right, 32'hxxxxxxxx };
  assign return_output = _0_;
endmodule

module center_bunker_vulnerable_0clk_6ad00a66(\window[data] , return_output);
  wire [4:0] _0_;
  wire [4:0] _1_;
  wire [4:0] _2_;
  wire [4:0] _3_;
  wire [4:0] _4_;
  wire [4:0] _5_;
  wire [4:0] _6_;
  wire [4:0] _7_;
  wire _8_;
  wire _9_;
  wire bin_op_and_solution_c_l341_c11_6b2e_left;
  wire bin_op_and_solution_c_l341_c11_6b2e_return_output;
  wire bin_op_and_solution_c_l341_c11_6b2e_right;
  wire [3:0] bin_op_lt_solution_c_l341_c25_e503_left;
  wire bin_op_lt_solution_c_l341_c25_e503_return_output;
  wire [2:0] bin_op_lt_solution_c_l341_c25_e503_right;
  wire [3:0] for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_c201_left;
  wire [4:0] for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_c201_return_output;
  wire for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_c201_right;
  wire [3:0] for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_1_bin_op_plus_solution_c_l337_c9_54a1_left;
  wire [4:0] for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_1_bin_op_plus_solution_c_l337_c9_54a1_return_output;
  wire for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_1_bin_op_plus_solution_c_l337_c9_54a1_right;
  wire [3:0] for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_e6b9_left;
  wire [4:0] for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_e6b9_return_output;
  wire for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_e6b9_right;
  wire [3:0] for_solution_c_l330_c3_780b_iter_1_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_b8ba_left;
  wire [4:0] for_solution_c_l330_c3_780b_iter_1_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_b8ba_return_output;
  wire for_solution_c_l330_c3_780b_iter_1_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_b8ba_right;
  wire [3:0] for_solution_c_l330_c3_780b_iter_1_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_9f5d_left;
  wire [4:0] for_solution_c_l330_c3_780b_iter_1_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_9f5d_return_output;
  wire for_solution_c_l330_c3_780b_iter_1_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_9f5d_right;
  wire [3:0] for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_fde5_left;
  wire [4:0] for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_fde5_return_output;
  wire for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_fde5_right;
  wire [3:0] for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_1_bin_op_plus_solution_c_l337_c9_29a3_left;
  wire [4:0] for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_1_bin_op_plus_solution_c_l337_c9_29a3_return_output;
  wire for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_1_bin_op_plus_solution_c_l337_c9_29a3_right;
  wire [3:0] for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_4983_left;
  wire [4:0] for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_4983_return_output;
  wire for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_4983_right;
  output return_output;
  wire return_output;
  input [8:0] \window[data] ;
  wire [8:0] \window[data] ;
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 bin_op_and_solution_c_l341_c11_6b2e (
    .left(bin_op_and_solution_c_l341_c11_6b2e_left),
    .return_output(_9_),
    .right(bin_op_and_solution_c_l341_c11_6b2e_right)
  );
  bin_op_lt_uint4_t_uint3_t_0clk_5af1a430 bin_op_lt_solution_c_l341_c25_e503 (
    .left(bin_op_lt_solution_c_l341_c25_e503_left),
    .return_output(_8_),
    .right(bin_op_lt_solution_c_l341_c25_e503_right)
  );
  bin_op_plus_uint4_t_uint1_t_0clk_de264c78 for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_c201 (
    .left(for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_c201_left),
    .return_output(_0_),
    .right(for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_c201_right)
  );
  bin_op_plus_uint4_t_uint1_t_0clk_de264c78 for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_1_bin_op_plus_solution_c_l337_c9_54a1 (
    .left(for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_1_bin_op_plus_solution_c_l337_c9_54a1_left),
    .return_output(_1_),
    .right(for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_1_bin_op_plus_solution_c_l337_c9_54a1_right)
  );
  bin_op_plus_uint4_t_uint1_t_0clk_de264c78 for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_e6b9 (
    .left(for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_e6b9_left),
    .return_output(_2_),
    .right(for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_e6b9_right)
  );
  bin_op_plus_uint4_t_uint1_t_0clk_de264c78 for_solution_c_l330_c3_780b_iter_1_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_b8ba (
    .left(for_solution_c_l330_c3_780b_iter_1_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_b8ba_left),
    .return_output(_3_),
    .right(for_solution_c_l330_c3_780b_iter_1_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_b8ba_right)
  );
  bin_op_plus_uint4_t_uint1_t_0clk_de264c78 for_solution_c_l330_c3_780b_iter_1_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_9f5d (
    .left(for_solution_c_l330_c3_780b_iter_1_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_9f5d_left),
    .return_output(_4_),
    .right(for_solution_c_l330_c3_780b_iter_1_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_9f5d_right)
  );
  bin_op_plus_uint4_t_uint1_t_0clk_de264c78 for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_fde5 (
    .left(for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_fde5_left),
    .return_output(_5_),
    .right(for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_fde5_right)
  );
  bin_op_plus_uint4_t_uint1_t_0clk_de264c78 for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_1_bin_op_plus_solution_c_l337_c9_29a3 (
    .left(for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_1_bin_op_plus_solution_c_l337_c9_29a3_left),
    .return_output(_6_),
    .right(for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_1_bin_op_plus_solution_c_l337_c9_29a3_right)
  );
  bin_op_plus_uint4_t_uint1_t_0clk_de264c78 for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_4983 (
    .left(for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_4983_left),
    .return_output(_7_),
    .right(for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_4983_right)
  );
  assign for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_c201_left = 4'h0;
  assign for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_c201_right = \window[data] [8];
  assign for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_c201_return_output = _0_;
  assign for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_1_bin_op_plus_solution_c_l337_c9_54a1_left = for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_c201_return_output[3:0];
  assign for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_1_bin_op_plus_solution_c_l337_c9_54a1_right = \window[data] [7];
  assign for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_1_bin_op_plus_solution_c_l337_c9_54a1_return_output = _1_;
  assign for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_e6b9_left = for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_1_bin_op_plus_solution_c_l337_c9_54a1_return_output[3:0];
  assign for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_e6b9_right = \window[data] [6];
  assign for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_e6b9_return_output = _2_;
  assign for_solution_c_l330_c3_780b_iter_1_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_b8ba_left = for_solution_c_l330_c3_780b_iter_0_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_e6b9_return_output[3:0];
  assign for_solution_c_l330_c3_780b_iter_1_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_b8ba_right = \window[data] [5];
  assign for_solution_c_l330_c3_780b_iter_1_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_b8ba_return_output = _3_;
  assign for_solution_c_l330_c3_780b_iter_1_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_9f5d_left = for_solution_c_l330_c3_780b_iter_1_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_b8ba_return_output[3:0];
  assign for_solution_c_l330_c3_780b_iter_1_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_9f5d_right = \window[data] [3];
  assign for_solution_c_l330_c3_780b_iter_1_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_9f5d_return_output = _4_;
  assign for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_fde5_left = for_solution_c_l330_c3_780b_iter_1_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_9f5d_return_output[3:0];
  assign for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_fde5_right = \window[data] [2];
  assign for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_fde5_return_output = _5_;
  assign for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_1_bin_op_plus_solution_c_l337_c9_29a3_left = for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_0_bin_op_plus_solution_c_l337_c9_fde5_return_output[3:0];
  assign for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_1_bin_op_plus_solution_c_l337_c9_29a3_right = \window[data] [1];
  assign for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_1_bin_op_plus_solution_c_l337_c9_29a3_return_output = _6_;
  assign for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_4983_left = for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_1_bin_op_plus_solution_c_l337_c9_29a3_return_output[3:0];
  assign for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_4983_right = \window[data] [0];
  assign for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_4983_return_output = _7_;
  assign bin_op_lt_solution_c_l341_c25_e503_left = for_solution_c_l330_c3_780b_iter_2_for_solution_c_l332_c5_c0f8_iter_2_bin_op_plus_solution_c_l337_c9_4983_return_output[3:0];
  assign bin_op_lt_solution_c_l341_c25_e503_right = 3'h4;
  assign bin_op_lt_solution_c_l341_c25_e503_return_output = _8_;
  assign bin_op_and_solution_c_l341_c11_6b2e_left = \window[data] [4];
  assign bin_op_and_solution_c_l341_c11_6b2e_right = bin_op_lt_solution_c_l341_c25_e503_return_output;
  assign bin_op_and_solution_c_l341_c11_6b2e_return_output = _9_;
  assign return_output = bin_op_and_solution_c_l341_c11_6b2e_return_output;
endmodule

module center_bunker_vulnerable_pipeline_0clk_16f17d08(clk, clock_enable, \global_to_module[center_bunker_vulnerable_pipeline_in] , \global_to_module[center_bunker_vulnerable_pipeline_in_valid] , \module_to_global[center_bunker_vulnerable_pipeline_out] , \module_to_global[center_bunker_vulnerable_pipeline_out_valid] );
  wire _0_;
  wire _1_;
  wire _2_;
  wire [7:0] _3_;
  wire _4_;
  wire _5_;
  wire _6_;
  wire [8:0] _7_;
  wire [7:0] _8_;
  wire center_bunker_vulnerable_pipeline_in_reg_func_solution_c_l346_c92_f7ba_clock_enable;
  wire [8:0] center_bunker_vulnerable_pipeline_in_reg_func_solution_c_l346_c92_f7ba_data;
  wire [7:0] center_bunker_vulnerable_pipeline_in_reg_func_solution_c_l346_c92_f7ba_id;
  wire [17:0] center_bunker_vulnerable_pipeline_in_reg_func_solution_c_l346_c92_f7ba_return_output;
  wire center_bunker_vulnerable_pipeline_in_reg_func_solution_c_l346_c92_f7ba_valid;
  wire center_bunker_vulnerable_pipeline_out_reg_func_solution_c_l346_c358_b135_clock_enable;
  wire center_bunker_vulnerable_pipeline_out_reg_func_solution_c_l346_c358_b135_data;
  wire [7:0] center_bunker_vulnerable_pipeline_out_reg_func_solution_c_l346_c358_b135_id;
  wire [9:0] center_bunker_vulnerable_pipeline_out_reg_func_solution_c_l346_c358_b135_return_output;
  wire center_bunker_vulnerable_pipeline_out_reg_func_solution_c_l346_c358_b135_valid;
  wire center_bunker_vulnerable_solution_c_l346_c276_079d_return_output;
  wire [8:0] center_bunker_vulnerable_solution_c_l346_c276_079d_window;
  input clk;
  wire clk;
  wire clk_en_internal;
  input clock_enable;
  wire clock_enable;
  input [8:0] \global_to_module[center_bunker_vulnerable_pipeline_in] ;
  wire [8:0] \global_to_module[center_bunker_vulnerable_pipeline_in] ;
  input \global_to_module[center_bunker_vulnerable_pipeline_in_valid] ;
  wire \global_to_module[center_bunker_vulnerable_pipeline_in_valid] ;
  output \module_to_global[center_bunker_vulnerable_pipeline_out] ;
  wire \module_to_global[center_bunker_vulnerable_pipeline_out] ;
  output \module_to_global[center_bunker_vulnerable_pipeline_out_valid] ;
  wire \module_to_global[center_bunker_vulnerable_pipeline_out_valid] ;
  assign _5_ = clk_en_internal ? center_bunker_vulnerable_pipeline_out_reg_func_solution_c_l346_c358_b135_return_output[0] : 1'h0;
  assign _6_ = clk_en_internal ? center_bunker_vulnerable_pipeline_out_reg_func_solution_c_l346_c358_b135_return_output[9] : 1'h0;
  center_bunker_vulnerable_pipeline_in_reg_func_0clk_b45f1687 center_bunker_vulnerable_pipeline_in_reg_func_solution_c_l346_c92_f7ba (
    .clk(clk),
    .clock_enable(center_bunker_vulnerable_pipeline_in_reg_func_solution_c_l346_c92_f7ba_clock_enable),
    .\data[data] (center_bunker_vulnerable_pipeline_in_reg_func_solution_c_l346_c92_f7ba_data),
    .id(center_bunker_vulnerable_pipeline_in_reg_func_solution_c_l346_c92_f7ba_id),
    .\return_output[data] (_7_),
    .\return_output[id] (_8_),
    .\return_output[valid] (_0_),
    .valid(center_bunker_vulnerable_pipeline_in_reg_func_solution_c_l346_c92_f7ba_valid)
  );
  center_bunker_vulnerable_pipeline_out_reg_func_0clk_b45f1687 center_bunker_vulnerable_pipeline_out_reg_func_solution_c_l346_c358_b135 (
    .clk(clk),
    .clock_enable(center_bunker_vulnerable_pipeline_out_reg_func_solution_c_l346_c358_b135_clock_enable),
    .data(center_bunker_vulnerable_pipeline_out_reg_func_solution_c_l346_c358_b135_data),
    .id(center_bunker_vulnerable_pipeline_out_reg_func_solution_c_l346_c358_b135_id),
    .\return_output[data] (_2_),
    .\return_output[id] (_3_),
    .\return_output[valid] (_4_),
    .valid(center_bunker_vulnerable_pipeline_out_reg_func_solution_c_l346_c358_b135_valid)
  );
  center_bunker_vulnerable_0clk_6ad00a66 center_bunker_vulnerable_solution_c_l346_c276_079d (
    .return_output(_1_),
    .\window[data] (center_bunker_vulnerable_solution_c_l346_c276_079d_window)
  );
  assign clk_en_internal = clock_enable;
  assign center_bunker_vulnerable_pipeline_in_reg_func_solution_c_l346_c92_f7ba_clock_enable = clk_en_internal;
  assign center_bunker_vulnerable_pipeline_in_reg_func_solution_c_l346_c92_f7ba_data = \global_to_module[center_bunker_vulnerable_pipeline_in] ;
  assign center_bunker_vulnerable_pipeline_in_reg_func_solution_c_l346_c92_f7ba_id = 8'h00;
  assign center_bunker_vulnerable_pipeline_in_reg_func_solution_c_l346_c92_f7ba_valid = \global_to_module[center_bunker_vulnerable_pipeline_in_valid] ;
  assign center_bunker_vulnerable_pipeline_in_reg_func_solution_c_l346_c92_f7ba_return_output = { _0_, _8_, _7_ };
  assign center_bunker_vulnerable_solution_c_l346_c276_079d_window = center_bunker_vulnerable_pipeline_in_reg_func_solution_c_l346_c92_f7ba_return_output[8:0];
  assign center_bunker_vulnerable_solution_c_l346_c276_079d_return_output = _1_;
  assign center_bunker_vulnerable_pipeline_out_reg_func_solution_c_l346_c358_b135_clock_enable = clk_en_internal;
  assign center_bunker_vulnerable_pipeline_out_reg_func_solution_c_l346_c358_b135_data = center_bunker_vulnerable_solution_c_l346_c276_079d_return_output;
  assign center_bunker_vulnerable_pipeline_out_reg_func_solution_c_l346_c358_b135_id = center_bunker_vulnerable_pipeline_in_reg_func_solution_c_l346_c92_f7ba_return_output[16:9];
  assign center_bunker_vulnerable_pipeline_out_reg_func_solution_c_l346_c358_b135_valid = center_bunker_vulnerable_pipeline_in_reg_func_solution_c_l346_c92_f7ba_return_output[17];
  assign center_bunker_vulnerable_pipeline_out_reg_func_solution_c_l346_c358_b135_return_output = { _4_, _3_, _2_ };
  assign \module_to_global[center_bunker_vulnerable_pipeline_out]  = _5_;
  assign \module_to_global[center_bunker_vulnerable_pipeline_out_valid]  = _6_;
endmodule

module center_bunker_vulnerable_pipeline_in_reg_func_0clk_b45f1687(clk, clock_enable, \data[data] , id, valid, \return_output[data] , \return_output[id] , \return_output[valid] );
  wire [17:0] _0_;
  reg [17:0] _1_ = 18'h00000;
  input clk;
  wire clk;
  wire clk_en_internal;
  input clock_enable;
  wire clock_enable;
  input [8:0] \data[data] ;
  wire [8:0] \data[data] ;
  input [7:0] id;
  wire [7:0] id;
  wire [17:0] reg_comb_the_reg;
  output [8:0] \return_output[data] ;
  wire [8:0] \return_output[data] ;
  output [7:0] \return_output[id] ;
  wire [7:0] \return_output[id] ;
  output \return_output[valid] ;
  wire \return_output[valid] ;
  wire [17:0] the_reg;
  input valid;
  wire valid;
  assign _0_ = clk_en_internal ? reg_comb_the_reg : the_reg;
  always @(posedge clk)
    _1_ <= _0_;
  assign the_reg = _1_;
  assign reg_comb_the_reg = { valid, id, \data[data]  };
  assign clk_en_internal = clock_enable;
  assign \return_output[data]  = the_reg[8:0];
  assign \return_output[id]  = the_reg[16:9];
  assign \return_output[valid]  = the_reg[17];
endmodule

module center_bunker_vulnerable_pipeline_out_reg_func_0clk_b45f1687(clk, clock_enable, data, id, valid, \return_output[data] , \return_output[id] , \return_output[valid] );
  wire [9:0] _0_;
  reg [9:0] _1_ = 10'h000;
  input clk;
  wire clk;
  wire clk_en_internal;
  input clock_enable;
  wire clock_enable;
  input data;
  wire data;
  input [7:0] id;
  wire [7:0] id;
  wire [9:0] reg_comb_the_reg;
  output \return_output[data] ;
  wire \return_output[data] ;
  output [7:0] \return_output[id] ;
  wire [7:0] \return_output[id] ;
  output \return_output[valid] ;
  wire \return_output[valid] ;
  wire [9:0] the_reg;
  input valid;
  wire valid;
  assign _0_ = clk_en_internal ? reg_comb_the_reg : the_reg;
  always @(posedge clk)
    _1_ <= _0_;
  assign the_reg = _1_;
  assign reg_comb_the_reg = { valid, id, data };
  assign clk_en_internal = clock_enable;
  assign \return_output[data]  = the_reg[0];
  assign \return_output[id]  = the_reg[8:1];
  assign \return_output[valid]  = the_reg[9];
endmodule

module const_sr_1_int9_t_0clk_de264c78(x, return_output);
  wire [8:0] _0_;
  wire [17:0] \:2822.read_pipe ;
  output [8:0] return_output;
  wire [8:0] return_output;
  input [8:0] x;
  wire [8:0] x;
  assign _0_ = $signed(x) >>> 31'h00000001;
  assign \:2822.read_pipe  = { 9'hxxx, x };
  assign return_output = _0_;
endmodule

module const_sr_2_int9_t_0clk_de264c78(x, return_output);
  wire [8:0] _0_;
  wire [17:0] \:3076.read_pipe ;
  output [8:0] return_output;
  wire [8:0] return_output;
  input [8:0] x;
  wire [8:0] x;
  assign _0_ = $signed(x) >>> 31'h00000002;
  assign \:3076.read_pipe  = { 9'hxxx, x };
  assign return_output = _0_;
endmodule

module const_sr_3_uint4_t_0clk_de264c78(x, return_output);
  wire [3:0] _0_;
  wire [7:0] \:2660.read_pipe ;
  output [3:0] return_output;
  wire [3:0] return_output;
  input [3:0] x;
  wire [3:0] x;
  assign _0_ = x >> 31'h00000003;
  assign \:2660.read_pipe  = { 4'hx, x };
  assign return_output = _0_;
endmodule

module const_sr_8_int10_t_0clk_de264c78(x, return_output);
  wire [9:0] _0_;
  wire [19:0] \:2920.read_pipe ;
  output [9:0] return_output;
  wire [9:0] return_output;
  input [9:0] x;
  wire [9:0] x;
  assign _0_ = $signed(x) >>> 31'h00000008;
  assign \:2920.read_pipe  = { 10'hxxx, x };
  assign return_output = _0_;
endmodule

module const_sr_8_int9_t_0clk_de264c78(x, return_output);
  wire [8:0] _0_;
  wire [17:0] \:3018.read_pipe ;
  output [8:0] return_output;
  wire [8:0] return_output;
  input [8:0] x;
  wire [8:0] x;
  assign _0_ = $signed(x) >>> 31'h00000008;
  assign \:3018.read_pipe  = { 9'hxxx, x };
  assign return_output = _0_;
endmodule

module line_fifo_0clk_b45f1687(clk, clock_enable, ready_for_data_out, data_in, data_in_valid, \return_output[data_out] , \return_output[data_out_valid] , \return_output[data_in_ready] );
  wire _0_;
  wire _1_;
  wire _2_;
  wire _3_;
  wire _4_;
  input clk;
  wire clk;
  input clock_enable;
  wire clock_enable;
  input data_in;
  wire data_in;
  input data_in_valid;
  wire data_in_valid;
  wire din_slv;
  wire dout_slv;
  input ready_for_data_out;
  wire ready_for_data_out;
  output \return_output[data_in_ready] ;
  wire \return_output[data_in_ready] ;
  output \return_output[data_out] ;
  wire \return_output[data_out] ;
  output \return_output[data_out_valid] ;
  wire \return_output[data_out_valid] ;
  assign _3_ = data_in_valid & clock_enable;
  assign _4_ = ready_for_data_out & clock_enable;
  pipelinec_fifo_fwft_1_7 pipelinec_fifo_fwft_inst (
    .clk(clk),
    .data_in(din_slv),
    .data_out(_2_),
    .ready_in(_4_),
    .ready_out(_0_),
    .valid_in(_3_),
    .valid_out(_1_)
  );
  assign din_slv = data_in;
  assign dout_slv = _2_;
  assign \return_output[data_out]  = dout_slv;
  assign \return_output[data_out_valid]  = _1_;
  assign \return_output[data_in_ready]  = _0_;
endmodule

module mux_uint1_t_int9_t_int9_t_0clk_de264c78(cond, iftrue, iffalse, return_output);
  wire _0_;
  wire [8:0] _1_;
  wire [27:0] \:1882.read_pipe ;
  input cond;
  wire cond;
  input [8:0] iffalse;
  wire [8:0] iffalse;
  input [8:0] iftrue;
  wire [8:0] iftrue;
  output [8:0] return_output;
  wire [8:0] return_output;
  assign _0_ = cond == 1'h1;
  assign _1_ = _0_ ? iftrue : iffalse;
  assign \:1882.read_pipe  = { iffalse, iftrue, cond, 9'hxxx };
  assign return_output = _1_;
endmodule

module mux_uint1_t_uint16_t_uint16_t_0clk_de264c78(cond, iftrue, iffalse, return_output);
  wire _0_;
  wire [15:0] _1_;
  wire [48:0] \:1668.read_pipe ;
  input cond;
  wire cond;
  input [15:0] iffalse;
  wire [15:0] iffalse;
  input [15:0] iftrue;
  wire [15:0] iftrue;
  output [15:0] return_output;
  wire [15:0] return_output;
  assign _0_ = cond == 1'h1;
  assign _1_ = _0_ ? iftrue : iffalse;
  assign \:1668.read_pipe  = { iffalse, iftrue, cond, 16'hxxxx };
  assign return_output = _1_;
endmodule

module mux_uint1_t_uint1_t_3_uint1_t_3_0clk_de264c78(cond, iftrue, iffalse, return_output);
  wire _0_;
  wire [2:0] _1_;
  wire [9:0] \:2360.read_pipe ;
  input cond;
  wire cond;
  input [2:0] iffalse;
  wire [2:0] iffalse;
  input [2:0] iftrue;
  wire [2:0] iftrue;
  output [2:0] return_output;
  wire [2:0] return_output;
  assign _0_ = cond == 1'h1;
  assign _1_ = _0_ ? iftrue : iffalse;
  assign \:2360.read_pipe  = { iffalse, iftrue, cond, 3'hx };
  assign return_output = _1_;
endmodule

module mux_uint1_t_uint1_t_uint1_t_0clk_de264c78(cond, iftrue, iffalse, return_output);
  wire _0_;
  wire _1_;
  wire [3:0] \:1473.read_pipe ;
  input cond;
  wire cond;
  input iffalse;
  wire iffalse;
  input iftrue;
  wire iftrue;
  output return_output;
  wire return_output;
  assign _0_ = cond == 1'h1;
  assign _1_ = _0_ ? iftrue : iffalse;
  assign \:1473.read_pipe  = { iffalse, iftrue, cond, 1'hx };
  assign return_output = _1_;
endmodule

module mux_uint1_t_uint3_t_uint3_t_0clk_de264c78(cond, iftrue, iffalse, return_output);
  wire _0_;
  wire [2:0] _1_;
  wire [9:0] \:1495.read_pipe ;
  input cond;
  wire cond;
  input [2:0] iffalse;
  wire [2:0] iffalse;
  input [2:0] iftrue;
  wire [2:0] iftrue;
  output [2:0] return_output;
  wire [2:0] return_output;
  assign _0_ = cond == 1'h1;
  assign _1_ = _0_ ? iftrue : iffalse;
  assign \:1495.read_pipe  = { iffalse, iftrue, cond, 3'hx };
  assign return_output = _1_;
endmodule

module mux_uint1_t_window_t_window_t_0clk_de264c78(cond, \iftrue[data] , \iffalse[data] , \return_output[data] );
  wire _0_;
  wire [8:0] _1_;
  wire [27:0] \:2338.read_pipe ;
  input cond;
  wire cond;
  input [8:0] \iffalse[data] ;
  wire [8:0] \iffalse[data] ;
  input [8:0] \iftrue[data] ;
  wire [8:0] \iftrue[data] ;
  output [8:0] \return_output[data] ;
  wire [8:0] \return_output[data] ;
  assign _0_ = cond == 1'h1;
  assign _1_ = _0_ ? \iftrue[data]  : \iffalse[data] ;
  assign \:2338.read_pipe  = { \iffalse[data] , \iftrue[data] , cond, 9'hxxx };
  assign \return_output[data]  = _1_;
endmodule

module pipelinec_fifo_fwft_1_7(clk, valid_in, data_in, ready_in, ready_out, valid_out, data_out);
  wire [7:0] _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire [7:0] _09_;
  wire [7:0] _10_;
  wire [7:0] _11_;
  wire _12_;
  wire _13_;
  wire _14_;
  wire _15_;
  wire _16_;
  wire [7:0] _17_;
  wire [7:0] _18_;
  wire _19_;
  wire _20_;
  wire _21_;
  wire _22_;
  wire [7:0] _23_;
  wire _24_;
  wire _25_;
  wire _26_;
  wire _27_;
  reg [7:0] _28_ = 8'h00;
  reg [7:0] _29_ = 8'h00;
  reg _30_;
  reg _31_ = 1'h0;
  reg _32_ = 1'h1;
  wire [127:0] _33_;
  wire _34_;
  input clk;
  wire clk;
  input data_in;
  wire data_in;
  output data_out;
  wire data_out;
  wire data_out_pipe;
  wire data_out_pipe_reg;
  wire empty;
  wire full;
  wire pipe_ready;
  wire por;
  wire [7:0] rd_ptr_reg;
  input ready_in;
  wire ready_in;
  output ready_out;
  wire ready_out;
  wire ready_out_internal;
  input valid_in;
  wire valid_in;
  output valid_out;
  wire valid_out;
  wire valid_out_pipe;
  wire valid_out_pipe_reg;
  wire [7:0] wr_ptr_reg;
  reg [0:0] mem [127:0];
  initial begin
    mem[0] = 1'h0;
    mem[1] = 1'h0;
    mem[2] = 1'h0;
    mem[3] = 1'h0;
    mem[4] = 1'h0;
    mem[5] = 1'h0;
    mem[6] = 1'h0;
    mem[7] = 1'h0;
    mem[8] = 1'h0;
    mem[9] = 1'h0;
    mem[10] = 1'h0;
    mem[11] = 1'h0;
    mem[12] = 1'h0;
    mem[13] = 1'h0;
    mem[14] = 1'h0;
    mem[15] = 1'h0;
    mem[16] = 1'h0;
    mem[17] = 1'h0;
    mem[18] = 1'h0;
    mem[19] = 1'h0;
    mem[20] = 1'h0;
    mem[21] = 1'h0;
    mem[22] = 1'h0;
    mem[23] = 1'h0;
    mem[24] = 1'h0;
    mem[25] = 1'h0;
    mem[26] = 1'h0;
    mem[27] = 1'h0;
    mem[28] = 1'h0;
    mem[29] = 1'h0;
    mem[30] = 1'h0;
    mem[31] = 1'h0;
    mem[32] = 1'h0;
    mem[33] = 1'h0;
    mem[34] = 1'h0;
    mem[35] = 1'h0;
    mem[36] = 1'h0;
    mem[37] = 1'h0;
    mem[38] = 1'h0;
    mem[39] = 1'h0;
    mem[40] = 1'h0;
    mem[41] = 1'h0;
    mem[42] = 1'h0;
    mem[43] = 1'h0;
    mem[44] = 1'h0;
    mem[45] = 1'h0;
    mem[46] = 1'h0;
    mem[47] = 1'h0;
    mem[48] = 1'h0;
    mem[49] = 1'h0;
    mem[50] = 1'h0;
    mem[51] = 1'h0;
    mem[52] = 1'h0;
    mem[53] = 1'h0;
    mem[54] = 1'h0;
    mem[55] = 1'h0;
    mem[56] = 1'h0;
    mem[57] = 1'h0;
    mem[58] = 1'h0;
    mem[59] = 1'h0;
    mem[60] = 1'h0;
    mem[61] = 1'h0;
    mem[62] = 1'h0;
    mem[63] = 1'h0;
    mem[64] = 1'h0;
    mem[65] = 1'h0;
    mem[66] = 1'h0;
    mem[67] = 1'h0;
    mem[68] = 1'h0;
    mem[69] = 1'h0;
    mem[70] = 1'h0;
    mem[71] = 1'h0;
    mem[72] = 1'h0;
    mem[73] = 1'h0;
    mem[74] = 1'h0;
    mem[75] = 1'h0;
    mem[76] = 1'h0;
    mem[77] = 1'h0;
    mem[78] = 1'h0;
    mem[79] = 1'h0;
    mem[80] = 1'h0;
    mem[81] = 1'h0;
    mem[82] = 1'h0;
    mem[83] = 1'h0;
    mem[84] = 1'h0;
    mem[85] = 1'h0;
    mem[86] = 1'h0;
    mem[87] = 1'h0;
    mem[88] = 1'h0;
    mem[89] = 1'h0;
    mem[90] = 1'h0;
    mem[91] = 1'h0;
    mem[92] = 1'h0;
    mem[93] = 1'h0;
    mem[94] = 1'h0;
    mem[95] = 1'h0;
    mem[96] = 1'h0;
    mem[97] = 1'h0;
    mem[98] = 1'h0;
    mem[99] = 1'h0;
    mem[100] = 1'h0;
    mem[101] = 1'h0;
    mem[102] = 1'h0;
    mem[103] = 1'h0;
    mem[104] = 1'h0;
    mem[105] = 1'h0;
    mem[106] = 1'h0;
    mem[107] = 1'h0;
    mem[108] = 1'h0;
    mem[109] = 1'h0;
    mem[110] = 1'h0;
    mem[111] = 1'h0;
    mem[112] = 1'h0;
    mem[113] = 1'h0;
    mem[114] = 1'h0;
    mem[115] = 1'h0;
    mem[116] = 1'h0;
    mem[117] = 1'h0;
    mem[118] = 1'h0;
    mem[119] = 1'h0;
    mem[120] = 1'h0;
    mem[121] = 1'h0;
    mem[122] = 1'h0;
    mem[123] = 1'h0;
    mem[124] = 1'h0;
    mem[125] = 1'h0;
    mem[126] = 1'h0;
    mem[127] = 1'h0;
  end
  always @(posedge clk) begin
    if (_27_)
      mem[wr_ptr_reg[6:0]] <= data_in;
  end
  assign _34_ = mem[rd_ptr_reg[6:0]];
  assign _00_ = rd_ptr_reg ^ 8'h80;
  assign _01_ = wr_ptr_reg == _00_;
  assign _02_ = _01_ ? 1'h1 : 1'h0;
  assign _03_ = wr_ptr_reg == rd_ptr_reg;
  assign _04_ = _03_ ? 1'h1 : 1'h0;
  assign _05_ = ~ full;
  assign _06_ = ~ por;
  assign _07_ = _05_ & _06_;
  assign _08_ = valid_in & ready_out_internal;
  assign _09_ = wr_ptr_reg + 8'h01;
  assign _10_ = _08_ ? _09_ : wr_ptr_reg;
  assign _11_ = por ? 8'h00 : _10_;
  assign _12_ = ready_in ? 1'h0 : valid_out_pipe_reg;
  assign _13_ = ~ valid_out_pipe_reg;
  assign _14_ = ready_in | _13_;
  assign _15_ = ~ empty;
  assign _16_ = pipe_ready & _15_;
  assign _17_ = rd_ptr_reg + 8'h01;
  assign _18_ = _20_ ? _17_ : rd_ptr_reg;
  assign _19_ = _16_ ? 1'h1 : 1'h0;
  assign _20_ = _16_ & _14_;
  assign _21_ = _14_ ? _34_ : data_out_pipe_reg;
  assign _22_ = _14_ ? _19_ : _12_;
  assign _23_ = por ? 8'h00 : _18_;
  assign _24_ = por ? data_out_pipe_reg : _21_;
  assign _25_ = por ? 1'h0 : _22_;
  assign _26_ = ~ por;
  assign _27_ = _26_ & _08_;
  always @(posedge clk)
    _28_ <= _11_;
  always @(posedge clk)
    _29_ <= _23_;
  always @(posedge clk)
    _30_ <= _24_;
  always @(posedge clk)
    _31_ <= _25_;
  always @(posedge clk)
    _32_ <= 1'h0;
  assign wr_ptr_reg = _28_;
  assign rd_ptr_reg = _29_;
  assign data_out_pipe_reg = _30_;
  assign valid_out_pipe_reg = _31_;
  assign full = _02_;
  assign empty = _04_;
  assign valid_out_pipe = valid_out_pipe_reg;
  assign data_out_pipe = data_out_pipe_reg;
  assign pipe_ready = 1'h1;
  assign por = _32_;
  assign ready_out_internal = _07_;
  assign ready_out = ready_out_internal;
  assign valid_out = valid_out_pipe;
  assign data_out = data_out_pipe;
endmodule

module slide_window_0clk_098d5770(\curr[data] , next_input_col, \return_output[data] );
  input [8:0] \curr[data] ;
  wire [8:0] \curr[data] ;
  input [2:0] next_input_col;
  wire [2:0] next_input_col;
  output [8:0] \return_output[data] ;
  wire [8:0] \return_output[data] ;
  assign \return_output[data]  = { \curr[data] [5:0], next_input_col };
endmodule

module sliding_window_0clk_f144350a(clk, clock_enable, data, grid_fragment_last, grid_last, data_valid, \module_to_global[done_frame_pulse] , \return_output[window] , \return_output[window_x_pos] , \return_output[window_y_pos] , \return_output[window_valid] , \return_output[ready_for_data_in] );
  wire _000_;
  wire _001_;
  wire _002_;
  wire _003_;
  wire _004_;
  wire _005_;
  wire _006_;
  wire _007_;
  wire _008_;
  wire _009_;
  wire [9:0] _010_;
  wire _011_;
  wire _012_;
  wire _013_;
  wire _014_;
  wire [9:0] _015_;
  wire _016_;
  wire _017_;
  wire _018_;
  wire _019_;
  wire [9:0] _020_;
  wire _021_;
  wire _022_;
  wire _023_;
  wire _024_;
  wire [8:0] _025_;
  wire [8:0] _026_;
  wire _027_;
  wire [8:0] _028_;
  wire _029_;
  wire [8:0] _030_;
  wire [8:0] _031_;
  wire [2:0] _032_;
  wire [8:0] _033_;
  wire [2:0] _034_;
  wire [8:0] _035_;
  wire _036_;
  wire _037_;
  wire _038_;
  wire _039_;
  wire [8:0] _040_;
  wire [8:0] _041_;
  wire _042_;
  wire [8:0] _043_;
  wire _044_;
  wire [8:0] _045_;
  wire [8:0] _046_;
  wire [2:0] _047_;
  wire [8:0] _048_;
  wire [2:0] _049_;
  wire [8:0] _050_;
  wire _051_;
  wire _052_;
  wire _053_;
  wire _054_;
  wire _055_;
  wire _056_;
  wire _057_;
  wire _058_;
  wire _059_;
  wire _060_;
  wire _061_;
  wire _062_;
  wire _063_;
  wire [9:0] _064_;
  wire [9:0] _065_;
  wire _066_;
  wire [8:0] _067_;
  wire _068_;
  wire _069_;
  wire _070_;
  wire _071_;
  wire [8:0] _072_;
  wire [8:0] _073_;
  wire _074_;
  wire [8:0] _075_;
  wire [8:0] _076_;
  wire [2:0] _077_;
  wire [8:0] _078_;
  wire [2:0] _079_;
  wire _080_;
  wire _081_;
  wire _082_;
  wire _083_;
  wire _084_;
  wire _085_;
  wire _086_;
  wire _087_;
  wire _088_;
  wire [9:0] _089_;
  wire _090_;
  wire [9:0] _091_;
  wire _092_;
  wire [9:0] _093_;
  wire _094_;
  wire [9:0] _095_;
  wire _096_;
  wire [9:0] _097_;
  wire _098_;
  wire [9:0] _099_;
  wire _100_;
  wire _101_;
  wire [8:0] _102_;
  reg [8:0] _103_ = 9'h000;
  wire _104_;
  reg _105_ = 1'h0;
  wire [8:0] _106_;
  reg [8:0] _107_ = 9'h000;
  wire [8:0] _108_;
  reg [8:0] _109_ = 9'h000;
  wire [8:0] _110_;
  reg [8:0] _111_ = 9'h080;
  wire [8:0] _112_;
  reg [8:0] _113_ = 9'h080;
  wire _114_;
  reg _115_ = 1'h0;
  wire [8:0] _116_;
  reg [8:0] _117_ = 9'h1fe;
  wire [8:0] _118_;
  reg [8:0] _119_ = 9'h1ff;
  wire [2:0] _120_;
  reg [2:0] _121_ = 3'h7;
  wire _122_;
  reg _123_ = 1'h1;
  wire _124_;
  reg _125_ = 1'h1;
  wire _126_;
  reg _127_ = 1'h1;
  wire [2:0] _128_;
  reg [2:0] _129_ = 3'h7;
  wire _130_;
  wire _131_;
  wire _132_;
  wire [8:0] _133_;
  wire [8:0] _134_;
  wire _135_;
  wire [8:0] _136_;
  wire [8:0] _137_;
  wire [9:0] _138_;
  wire [8:0] _139_;
  wire [8:0] _140_;
  wire _141_;
  wire [8:0] _142_;
  wire [8:0] _143_;
  wire [9:0] _144_;
  wire [8:0] _145_;
  wire _146_;
  wire [8:0] _147_;
  wire _148_;
  wire _149_;
  wire _150_;
  wire _151_;
  wire _152_;
  wire _153_;
  wire _154_;
  wire _155_;
  wire _156_;
  wire _157_;
  wire _158_;
  wire _159_;
  wire _160_;
  wire _161_;
  wire _162_;
  wire _163_;
  wire _164_;
  wire _165_;
  wire _166_;
  wire _167_;
  wire bin_op_and_solution_c_l153_c6_6e62_left;
  wire bin_op_and_solution_c_l153_c6_6e62_return_output;
  wire bin_op_and_solution_c_l153_c6_6e62_right;
  wire bin_op_and_solution_c_l265_c23_8238_left;
  wire bin_op_and_solution_c_l265_c23_8238_return_output;
  wire bin_op_and_solution_c_l265_c23_8238_right;
  wire bin_op_and_solution_c_l265_c23_a02b_left;
  wire bin_op_and_solution_c_l265_c23_a02b_return_output;
  wire bin_op_and_solution_c_l265_c23_a02b_right;
  wire [8:0] bin_op_gte_solution_c_l265_c23_7c1c_left;
  wire bin_op_gte_solution_c_l265_c23_7c1c_return_output;
  wire [1:0] bin_op_gte_solution_c_l265_c23_7c1c_right;
  wire [8:0] bin_op_gte_solution_c_l265_c45_7188_left;
  wire bin_op_gte_solution_c_l265_c45_7188_return_output;
  wire [1:0] bin_op_gte_solution_c_l265_c45_7188_right;
  wire [8:0] bin_op_lt_int9_t_int10_t_solution_c_l239_duplicate_354c_left;
  wire bin_op_lt_int9_t_int10_t_solution_c_l239_duplicate_354c_return_output;
  wire [9:0] bin_op_lt_int9_t_int10_t_solution_c_l239_duplicate_354c_right;
  wire [8:0] bin_op_lt_int9_t_int10_t_solution_c_l260_c12_9f27_duplicate_df5d_left;
  wire bin_op_lt_int9_t_int10_t_solution_c_l260_c12_9f27_duplicate_df5d_return_output;
  wire [9:0] bin_op_lt_int9_t_int10_t_solution_c_l260_c12_9f27_duplicate_df5d_right;
  wire [8:0] bin_op_lt_solution_c_l263_c25_b7b8_left;
  wire bin_op_lt_solution_c_l263_c25_b7b8_return_output;
  wire [9:0] bin_op_lt_solution_c_l263_c25_b7b8_right;
  wire [8:0] bin_op_lt_solution_c_l293_c30_911c_left;
  wire bin_op_lt_solution_c_l293_c30_911c_return_output;
  wire [8:0] bin_op_lt_solution_c_l293_c30_911c_right;
  wire [8:0] bin_op_lte_solution_c_l241_c25_ea4f_left;
  wire bin_op_lte_solution_c_l241_c25_ea4f_return_output;
  wire [8:0] bin_op_lte_solution_c_l241_c25_ea4f_right;
  wire [8:0] bin_op_minus_int9_t_int3_t_solution_c_l239_duplicate_9331_left;
  wire [9:0] bin_op_minus_int9_t_int3_t_solution_c_l239_duplicate_9331_return_output;
  wire [2:0] bin_op_minus_int9_t_int3_t_solution_c_l239_duplicate_9331_right;
  wire [8:0] bin_op_minus_int9_t_int3_t_solution_c_l260_c28_029e_duplicate_9a64_left;
  wire [9:0] bin_op_minus_int9_t_int3_t_solution_c_l260_c28_029e_duplicate_9a64_return_output;
  wire [2:0] bin_op_minus_int9_t_int3_t_solution_c_l260_c28_029e_duplicate_9a64_right;
  wire [8:0] bin_op_minus_solution_c_l263_c41_43fe_left;
  wire [9:0] bin_op_minus_solution_c_l263_c41_43fe_return_output;
  wire [1:0] bin_op_minus_solution_c_l263_c41_43fe_right;
  wire [8:0] bin_op_plus_solution_c_l154_c5_d98c_left;
  wire [9:0] bin_op_plus_solution_c_l154_c5_d98c_return_output;
  wire [1:0] bin_op_plus_solution_c_l154_c5_d98c_right;
  wire [8:0] bin_op_plus_solution_c_l156_c7_9c3b_left;
  wire [9:0] bin_op_plus_solution_c_l156_c7_9c3b_return_output;
  wire [1:0] bin_op_plus_solution_c_l156_c7_9c3b_right;
  wire [8:0] bin_op_plus_solution_c_l262_c7_516d_left;
  wire [9:0] bin_op_plus_solution_c_l262_c7_516d_return_output;
  wire [1:0] bin_op_plus_solution_c_l262_c7_516d_right;
  wire [8:0] bin_op_plus_solution_c_l291_c9_bc84_left;
  wire [9:0] bin_op_plus_solution_c_l291_c9_bc84_return_output;
  wire [1:0] bin_op_plus_solution_c_l291_c9_bc84_right;
  input clk;
  wire clk;
  wire clk_en_internal;
  input clock_enable;
  wire clock_enable;
  wire current_line_width_mux_solution_c_l153_c3_2e68_cond;
  wire [8:0] current_line_width_mux_solution_c_l153_c3_2e68_iffalse;
  wire [8:0] current_line_width_mux_solution_c_l153_c3_2e68_iftrue;
  wire [8:0] current_line_width_mux_solution_c_l153_c3_2e68_return_output;
  wire current_line_width_mux_solution_c_l155_c5_4943_cond;
  wire [8:0] current_line_width_mux_solution_c_l155_c5_4943_iffalse;
  wire [8:0] current_line_width_mux_solution_c_l155_c5_4943_iftrue;
  wire [8:0] current_line_width_mux_solution_c_l155_c5_4943_return_output;
  wire current_line_width_mux_solution_c_l247_c3_5f6b_cond;
  wire [8:0] current_line_width_mux_solution_c_l247_c3_5f6b_iffalse;
  wire [8:0] current_line_width_mux_solution_c_l247_c3_5f6b_iftrue;
  wire [8:0] current_line_width_mux_solution_c_l247_c3_5f6b_return_output;
  wire current_line_width_mux_solution_c_l251_c5_4213_cond;
  wire [8:0] current_line_width_mux_solution_c_l251_c5_4213_iffalse;
  wire [8:0] current_line_width_mux_solution_c_l251_c5_4213_iftrue;
  wire [8:0] current_line_width_mux_solution_c_l251_c5_4213_return_output;
  wire current_line_width_mux_solution_c_l272_c7_a3df_cond;
  wire [8:0] current_line_width_mux_solution_c_l272_c7_a3df_iffalse;
  wire [8:0] current_line_width_mux_solution_c_l272_c7_a3df_iftrue;
  wire [8:0] current_line_width_mux_solution_c_l272_c7_a3df_return_output;
  wire [8:0] current_line_width_reg;
  wire current_num_lines_mux_solution_c_l153_c3_2e68_cond;
  wire [8:0] current_num_lines_mux_solution_c_l153_c3_2e68_iffalse;
  wire [8:0] current_num_lines_mux_solution_c_l153_c3_2e68_iftrue;
  wire [8:0] current_num_lines_mux_solution_c_l153_c3_2e68_return_output;
  wire current_num_lines_mux_solution_c_l155_c5_4943_cond;
  wire [8:0] current_num_lines_mux_solution_c_l155_c5_4943_iffalse;
  wire [8:0] current_num_lines_mux_solution_c_l155_c5_4943_iftrue;
  wire [8:0] current_num_lines_mux_solution_c_l155_c5_4943_return_output;
  wire current_num_lines_mux_solution_c_l159_c7_1e67_cond;
  wire [8:0] current_num_lines_mux_solution_c_l159_c7_1e67_iffalse;
  wire [8:0] current_num_lines_mux_solution_c_l159_c7_1e67_iftrue;
  wire [8:0] current_num_lines_mux_solution_c_l159_c7_1e67_return_output;
  wire current_num_lines_mux_solution_c_l247_c3_5f6b_cond;
  wire [8:0] current_num_lines_mux_solution_c_l247_c3_5f6b_iffalse;
  wire [8:0] current_num_lines_mux_solution_c_l247_c3_5f6b_iftrue;
  wire [8:0] current_num_lines_mux_solution_c_l247_c3_5f6b_return_output;
  wire current_num_lines_mux_solution_c_l251_c5_4213_cond;
  wire [8:0] current_num_lines_mux_solution_c_l251_c5_4213_iffalse;
  wire [8:0] current_num_lines_mux_solution_c_l251_c5_4213_iftrue;
  wire [8:0] current_num_lines_mux_solution_c_l251_c5_4213_return_output;
  wire current_num_lines_mux_solution_c_l272_c7_a3df_cond;
  wire [8:0] current_num_lines_mux_solution_c_l272_c7_a3df_iffalse;
  wire [8:0] current_num_lines_mux_solution_c_l272_c7_a3df_iftrue;
  wire [8:0] current_num_lines_mux_solution_c_l272_c7_a3df_return_output;
  wire [8:0] current_num_lines_reg;
  input data;
  wire data;
  input data_valid;
  wire data_valid;
  wire done_frame_pulse_mux_solution_c_l247_c3_5f6b_cond;
  wire done_frame_pulse_mux_solution_c_l247_c3_5f6b_iffalse;
  wire done_frame_pulse_mux_solution_c_l247_c3_5f6b_iftrue;
  wire done_frame_pulse_mux_solution_c_l247_c3_5f6b_return_output;
  wire done_frame_pulse_mux_solution_c_l251_c5_4213_cond;
  wire done_frame_pulse_mux_solution_c_l251_c5_4213_iffalse;
  wire done_frame_pulse_mux_solution_c_l251_c5_4213_iftrue;
  wire done_frame_pulse_mux_solution_c_l251_c5_4213_return_output;
  wire done_frame_pulse_mux_solution_c_l272_c7_a3df_cond;
  wire done_frame_pulse_mux_solution_c_l272_c7_a3df_iffalse;
  wire done_frame_pulse_mux_solution_c_l272_c7_a3df_iftrue;
  wire done_frame_pulse_mux_solution_c_l272_c7_a3df_return_output;
  wire [11:0] feedback_vars;
  wire fifo_input_valids_0_mux_solution_c_l149_c3_b279_cond;
  wire fifo_input_valids_0_mux_solution_c_l149_c3_b279_iffalse;
  wire fifo_input_valids_0_mux_solution_c_l149_c3_b279_iftrue;
  wire fifo_input_valids_0_mux_solution_c_l149_c3_b279_return_output;
  wire for_solution_c_l168_c3_5d74_iter_0_bin_op_and_solution_c_l176_c32_ca5a_left;
  wire for_solution_c_l168_c3_5d74_iter_0_bin_op_and_solution_c_l176_c32_ca5a_return_output;
  wire for_solution_c_l168_c3_5d74_iter_0_bin_op_and_solution_c_l176_c32_ca5a_right;
  wire for_solution_c_l168_c3_5d74_iter_0_bin_op_and_solution_c_l177_c35_66a3_left;
  wire for_solution_c_l168_c3_5d74_iter_0_bin_op_and_solution_c_l177_c35_66a3_return_output;
  wire for_solution_c_l168_c3_5d74_iter_0_bin_op_and_solution_c_l177_c35_66a3_right;
  wire for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788_clock_enable;
  wire for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788_data_in;
  wire for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788_data_in_valid;
  wire for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788_ready_for_data_out;
  wire [2:0] for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788_return_output;
  wire for_solution_c_l168_c3_5d74_iter_1_bin_op_and_solution_c_l176_c32_ca5a_left;
  wire for_solution_c_l168_c3_5d74_iter_1_bin_op_and_solution_c_l176_c32_ca5a_return_output;
  wire for_solution_c_l168_c3_5d74_iter_1_bin_op_and_solution_c_l176_c32_ca5a_right;
  wire for_solution_c_l168_c3_5d74_iter_1_bin_op_and_solution_c_l177_c35_66a3_left;
  wire for_solution_c_l168_c3_5d74_iter_1_bin_op_and_solution_c_l177_c35_66a3_return_output;
  wire for_solution_c_l168_c3_5d74_iter_1_bin_op_and_solution_c_l177_c35_66a3_right;
  wire for_solution_c_l168_c3_5d74_iter_1_line_fifo_solution_c_l183_c28_1788_clock_enable;
  wire for_solution_c_l168_c3_5d74_iter_1_line_fifo_solution_c_l183_c28_1788_data_in;
  wire for_solution_c_l168_c3_5d74_iter_1_line_fifo_solution_c_l183_c28_1788_data_in_valid;
  wire for_solution_c_l168_c3_5d74_iter_1_line_fifo_solution_c_l183_c28_1788_ready_for_data_out;
  wire [2:0] for_solution_c_l168_c3_5d74_iter_1_line_fifo_solution_c_l183_c28_1788_return_output;
  wire for_solution_c_l168_c3_5d74_iter_2_line_fifo_solution_c_l183_c28_1788_clock_enable;
  wire for_solution_c_l168_c3_5d74_iter_2_line_fifo_solution_c_l183_c28_1788_data_in;
  wire for_solution_c_l168_c3_5d74_iter_2_line_fifo_solution_c_l183_c28_1788_data_in_valid;
  wire for_solution_c_l168_c3_5d74_iter_2_line_fifo_solution_c_l183_c28_1788_ready_for_data_out;
  wire [2:0] for_solution_c_l168_c3_5d74_iter_2_line_fifo_solution_c_l183_c28_1788_return_output;
  wire for_solution_c_l211_c3_1068_iter_0_bin_op_or_solution_c_l212_c32_6eba_left;
  wire for_solution_c_l211_c3_1068_iter_0_bin_op_or_solution_c_l212_c32_6eba_return_output;
  wire for_solution_c_l211_c3_1068_iter_0_bin_op_or_solution_c_l212_c32_6eba_right;
  wire for_solution_c_l211_c3_1068_iter_0_unary_op_not_solution_c_l212_c57_d4c8_expr;
  wire for_solution_c_l211_c3_1068_iter_0_unary_op_not_solution_c_l212_c57_d4c8_return_output;
  wire for_solution_c_l211_c3_1068_iter_1_bin_op_or_solution_c_l212_c32_6eba_left;
  wire for_solution_c_l211_c3_1068_iter_1_bin_op_or_solution_c_l212_c32_6eba_return_output;
  wire for_solution_c_l211_c3_1068_iter_1_bin_op_or_solution_c_l212_c32_6eba_right;
  wire for_solution_c_l211_c3_1068_iter_1_unary_op_not_solution_c_l212_c57_d4c8_expr;
  wire for_solution_c_l211_c3_1068_iter_1_unary_op_not_solution_c_l212_c57_d4c8_return_output;
  wire for_solution_c_l211_c3_1068_iter_2_bin_op_or_solution_c_l212_c32_6eba_left;
  wire for_solution_c_l211_c3_1068_iter_2_bin_op_or_solution_c_l212_c32_6eba_return_output;
  wire for_solution_c_l211_c3_1068_iter_2_bin_op_or_solution_c_l212_c32_6eba_right;
  wire for_solution_c_l211_c3_1068_iter_2_unary_op_not_solution_c_l212_c57_d4c8_expr;
  wire for_solution_c_l211_c3_1068_iter_2_unary_op_not_solution_c_l212_c57_d4c8_return_output;
  wire for_solution_c_l217_c3_08af_iter_0_bin_op_and_solution_c_l218_c34_f37f_left;
  wire for_solution_c_l217_c3_08af_iter_0_bin_op_and_solution_c_l218_c34_f37f_return_output;
  wire for_solution_c_l217_c3_08af_iter_0_bin_op_and_solution_c_l218_c34_f37f_right;
  wire for_solution_c_l217_c3_08af_iter_1_bin_op_and_solution_c_l218_c34_f37f_left;
  wire for_solution_c_l217_c3_08af_iter_1_bin_op_and_solution_c_l218_c34_f37f_return_output;
  wire for_solution_c_l217_c3_08af_iter_1_bin_op_and_solution_c_l218_c34_f37f_right;
  wire for_solution_c_l217_c3_08af_iter_2_bin_op_and_solution_c_l218_c34_f37f_left;
  wire for_solution_c_l217_c3_08af_iter_2_bin_op_and_solution_c_l218_c34_f37f_return_output;
  wire for_solution_c_l217_c3_08af_iter_2_bin_op_and_solution_c_l218_c34_f37f_right;
  wire for_solution_c_l224_c3_8683_iter_0_bin_op_and_solution_c_l227_c8_a2d7_left;
  wire for_solution_c_l224_c3_8683_iter_0_bin_op_and_solution_c_l227_c8_a2d7_return_output;
  wire for_solution_c_l224_c3_8683_iter_0_bin_op_and_solution_c_l227_c8_a2d7_right;
  wire for_solution_c_l224_c3_8683_iter_0_next_input_col_2_mux_solution_c_l227_c5_d5e1_cond;
  wire for_solution_c_l224_c3_8683_iter_0_next_input_col_2_mux_solution_c_l227_c5_d5e1_iffalse;
  wire for_solution_c_l224_c3_8683_iter_0_next_input_col_2_mux_solution_c_l227_c5_d5e1_iftrue;
  wire for_solution_c_l224_c3_8683_iter_0_next_input_col_2_mux_solution_c_l227_c5_d5e1_return_output;
  wire for_solution_c_l224_c3_8683_iter_1_bin_op_and_solution_c_l227_c8_a2d7_left;
  wire for_solution_c_l224_c3_8683_iter_1_bin_op_and_solution_c_l227_c8_a2d7_return_output;
  wire for_solution_c_l224_c3_8683_iter_1_bin_op_and_solution_c_l227_c8_a2d7_right;
  wire for_solution_c_l224_c3_8683_iter_1_next_input_col_1_mux_solution_c_l227_c5_d5e1_cond;
  wire for_solution_c_l224_c3_8683_iter_1_next_input_col_1_mux_solution_c_l227_c5_d5e1_iffalse;
  wire for_solution_c_l224_c3_8683_iter_1_next_input_col_1_mux_solution_c_l227_c5_d5e1_iftrue;
  wire for_solution_c_l224_c3_8683_iter_1_next_input_col_1_mux_solution_c_l227_c5_d5e1_return_output;
  wire for_solution_c_l224_c3_8683_iter_2_bin_op_and_solution_c_l227_c8_a2d7_left;
  wire for_solution_c_l224_c3_8683_iter_2_bin_op_and_solution_c_l227_c8_a2d7_return_output;
  wire for_solution_c_l224_c3_8683_iter_2_bin_op_and_solution_c_l227_c8_a2d7_right;
  wire for_solution_c_l224_c3_8683_iter_2_next_input_col_0_mux_solution_c_l227_c5_d5e1_cond;
  wire for_solution_c_l224_c3_8683_iter_2_next_input_col_0_mux_solution_c_l227_c5_d5e1_iffalse;
  wire for_solution_c_l224_c3_8683_iter_2_next_input_col_0_mux_solution_c_l227_c5_d5e1_iftrue;
  wire for_solution_c_l224_c3_8683_iter_2_next_input_col_0_mux_solution_c_l227_c5_d5e1_return_output;
  wire for_solution_c_l233_c3_2dcf_iter_0_bin_op_and_solution_c_l235_c8_37e4_left;
  wire for_solution_c_l233_c3_2dcf_iter_0_bin_op_and_solution_c_l235_c8_37e4_return_output;
  wire for_solution_c_l233_c3_2dcf_iter_0_bin_op_and_solution_c_l235_c8_37e4_right;
  wire for_solution_c_l233_c3_2dcf_iter_0_bin_op_and_solution_c_l235_c8_ab2a_left;
  wire for_solution_c_l233_c3_2dcf_iter_0_bin_op_and_solution_c_l235_c8_ab2a_return_output;
  wire for_solution_c_l233_c3_2dcf_iter_0_bin_op_and_solution_c_l235_c8_ab2a_right;
  wire [8:0] for_solution_c_l233_c3_2dcf_iter_0_bin_op_gte_solution_c_l235_c8_ce82_left;
  wire for_solution_c_l233_c3_2dcf_iter_0_bin_op_gte_solution_c_l235_c8_ce82_return_output;
  wire [1:0] for_solution_c_l233_c3_2dcf_iter_0_bin_op_gte_solution_c_l235_c8_ce82_right;
  wire [8:0] for_solution_c_l233_c3_2dcf_iter_0_bin_op_lte_solution_c_l236_c8_f1b1_left;
  wire for_solution_c_l233_c3_2dcf_iter_0_bin_op_lte_solution_c_l236_c8_f1b1_return_output;
  wire [9:0] for_solution_c_l233_c3_2dcf_iter_0_bin_op_lte_solution_c_l236_c8_f1b1_right;
  wire [8:0] for_solution_c_l233_c3_2dcf_iter_0_bin_op_minus_solution_c_l237_c9_090e_left;
  wire [9:0] for_solution_c_l233_c3_2dcf_iter_0_bin_op_minus_solution_c_l237_c9_090e_return_output;
  wire [2:0] for_solution_c_l233_c3_2dcf_iter_0_bin_op_minus_solution_c_l237_c9_090e_right;
  wire for_solution_c_l233_c3_2dcf_iter_1_bin_op_and_solution_c_l235_c8_37e4_left;
  wire for_solution_c_l233_c3_2dcf_iter_1_bin_op_and_solution_c_l235_c8_37e4_return_output;
  wire for_solution_c_l233_c3_2dcf_iter_1_bin_op_and_solution_c_l235_c8_37e4_right;
  wire for_solution_c_l233_c3_2dcf_iter_1_bin_op_and_solution_c_l235_c8_ab2a_left;
  wire for_solution_c_l233_c3_2dcf_iter_1_bin_op_and_solution_c_l235_c8_ab2a_return_output;
  wire for_solution_c_l233_c3_2dcf_iter_1_bin_op_and_solution_c_l235_c8_ab2a_right;
  wire [8:0] for_solution_c_l233_c3_2dcf_iter_1_bin_op_gte_solution_c_l235_c8_ce82_left;
  wire for_solution_c_l233_c3_2dcf_iter_1_bin_op_gte_solution_c_l235_c8_ce82_return_output;
  wire [1:0] for_solution_c_l233_c3_2dcf_iter_1_bin_op_gte_solution_c_l235_c8_ce82_right;
  wire [8:0] for_solution_c_l233_c3_2dcf_iter_1_bin_op_lte_solution_c_l236_c8_f1b1_left;
  wire for_solution_c_l233_c3_2dcf_iter_1_bin_op_lte_solution_c_l236_c8_f1b1_return_output;
  wire [9:0] for_solution_c_l233_c3_2dcf_iter_1_bin_op_lte_solution_c_l236_c8_f1b1_right;
  wire [8:0] for_solution_c_l233_c3_2dcf_iter_1_bin_op_minus_solution_c_l237_c9_090e_left;
  wire [9:0] for_solution_c_l233_c3_2dcf_iter_1_bin_op_minus_solution_c_l237_c9_090e_return_output;
  wire [1:0] for_solution_c_l233_c3_2dcf_iter_1_bin_op_minus_solution_c_l237_c9_090e_right;
  wire for_solution_c_l233_c3_2dcf_iter_2_bin_op_and_solution_c_l235_c8_37e4_left;
  wire for_solution_c_l233_c3_2dcf_iter_2_bin_op_and_solution_c_l235_c8_37e4_return_output;
  wire for_solution_c_l233_c3_2dcf_iter_2_bin_op_and_solution_c_l235_c8_37e4_right;
  wire for_solution_c_l233_c3_2dcf_iter_2_bin_op_and_solution_c_l235_c8_ab2a_left;
  wire for_solution_c_l233_c3_2dcf_iter_2_bin_op_and_solution_c_l235_c8_ab2a_return_output;
  wire for_solution_c_l233_c3_2dcf_iter_2_bin_op_and_solution_c_l235_c8_ab2a_right;
  wire [8:0] for_solution_c_l233_c3_2dcf_iter_2_bin_op_gte_solution_c_l235_c8_ce82_left;
  wire for_solution_c_l233_c3_2dcf_iter_2_bin_op_gte_solution_c_l235_c8_ce82_return_output;
  wire [1:0] for_solution_c_l233_c3_2dcf_iter_2_bin_op_gte_solution_c_l235_c8_ce82_right;
  wire [8:0] for_solution_c_l233_c3_2dcf_iter_2_bin_op_lte_solution_c_l236_c8_f1b1_left;
  wire for_solution_c_l233_c3_2dcf_iter_2_bin_op_lte_solution_c_l236_c8_f1b1_return_output;
  wire [9:0] for_solution_c_l233_c3_2dcf_iter_2_bin_op_lte_solution_c_l236_c8_f1b1_right;
  wire [8:0] for_solution_c_l233_c3_2dcf_iter_2_bin_op_minus_solution_c_l237_c9_090e_left;
  wire [9:0] for_solution_c_l233_c3_2dcf_iter_2_bin_op_minus_solution_c_l237_c9_090e_return_output;
  wire [1:0] for_solution_c_l233_c3_2dcf_iter_2_bin_op_minus_solution_c_l237_c9_090e_right;
  wire for_solution_c_l253_c7_deca_iter_0_bin_op_and_solution_c_l255_c12_12e3_left;
  wire for_solution_c_l253_c7_deca_iter_0_bin_op_and_solution_c_l255_c12_12e3_return_output;
  wire for_solution_c_l253_c7_deca_iter_0_bin_op_and_solution_c_l255_c12_12e3_right;
  wire for_solution_c_l253_c7_deca_iter_0_bin_op_and_solution_c_l255_c12_bcb6_left;
  wire for_solution_c_l253_c7_deca_iter_0_bin_op_and_solution_c_l255_c12_bcb6_return_output;
  wire for_solution_c_l253_c7_deca_iter_0_bin_op_and_solution_c_l255_c12_bcb6_right;
  wire [8:0] for_solution_c_l253_c7_deca_iter_0_bin_op_gte_solution_c_l255_c12_d6e8_left;
  wire for_solution_c_l253_c7_deca_iter_0_bin_op_gte_solution_c_l255_c12_d6e8_return_output;
  wire [1:0] for_solution_c_l253_c7_deca_iter_0_bin_op_gte_solution_c_l255_c12_d6e8_right;
  wire for_solution_c_l253_c7_deca_iter_1_bin_op_and_solution_c_l255_c12_12e3_left;
  wire for_solution_c_l253_c7_deca_iter_1_bin_op_and_solution_c_l255_c12_12e3_return_output;
  wire for_solution_c_l253_c7_deca_iter_1_bin_op_and_solution_c_l255_c12_12e3_right;
  wire for_solution_c_l253_c7_deca_iter_1_bin_op_and_solution_c_l255_c12_bcb6_left;
  wire for_solution_c_l253_c7_deca_iter_1_bin_op_and_solution_c_l255_c12_bcb6_return_output;
  wire for_solution_c_l253_c7_deca_iter_1_bin_op_and_solution_c_l255_c12_bcb6_right;
  wire [8:0] for_solution_c_l253_c7_deca_iter_1_bin_op_gte_solution_c_l255_c12_d6e8_left;
  wire for_solution_c_l253_c7_deca_iter_1_bin_op_gte_solution_c_l255_c12_d6e8_return_output;
  wire [1:0] for_solution_c_l253_c7_deca_iter_1_bin_op_gte_solution_c_l255_c12_d6e8_right;
  wire for_solution_c_l253_c7_deca_iter_2_bin_op_and_solution_c_l255_c12_12e3_left;
  wire for_solution_c_l253_c7_deca_iter_2_bin_op_and_solution_c_l255_c12_12e3_return_output;
  wire for_solution_c_l253_c7_deca_iter_2_bin_op_and_solution_c_l255_c12_12e3_right;
  wire for_solution_c_l253_c7_deca_iter_2_bin_op_and_solution_c_l255_c12_bcb6_left;
  wire for_solution_c_l253_c7_deca_iter_2_bin_op_and_solution_c_l255_c12_bcb6_return_output;
  wire for_solution_c_l253_c7_deca_iter_2_bin_op_and_solution_c_l255_c12_bcb6_right;
  wire [8:0] for_solution_c_l253_c7_deca_iter_2_bin_op_gte_solution_c_l255_c12_d6e8_left;
  wire for_solution_c_l253_c7_deca_iter_2_bin_op_gte_solution_c_l255_c12_d6e8_return_output;
  wire [1:0] for_solution_c_l253_c7_deca_iter_2_bin_op_gte_solution_c_l255_c12_d6e8_right;
  wire for_solution_c_l279_c9_6774_iter_0_bin_op_and_solution_c_l281_c14_4bb1_left;
  wire for_solution_c_l279_c9_6774_iter_0_bin_op_and_solution_c_l281_c14_4bb1_return_output;
  wire for_solution_c_l279_c9_6774_iter_0_bin_op_and_solution_c_l281_c14_4bb1_right;
  wire [8:0] for_solution_c_l279_c9_6774_iter_0_bin_op_gte_solution_c_l281_c14_efaa_left;
  wire for_solution_c_l279_c9_6774_iter_0_bin_op_gte_solution_c_l281_c14_efaa_return_output;
  wire [2:0] for_solution_c_l279_c9_6774_iter_0_bin_op_gte_solution_c_l281_c14_efaa_right;
  wire for_solution_c_l279_c9_6774_iter_1_bin_op_and_solution_c_l281_c14_4bb1_left;
  wire for_solution_c_l279_c9_6774_iter_1_bin_op_and_solution_c_l281_c14_4bb1_return_output;
  wire for_solution_c_l279_c9_6774_iter_1_bin_op_and_solution_c_l281_c14_4bb1_right;
  wire [8:0] for_solution_c_l279_c9_6774_iter_1_bin_op_gte_solution_c_l281_c14_efaa_left;
  wire for_solution_c_l279_c9_6774_iter_1_bin_op_gte_solution_c_l281_c14_efaa_return_output;
  wire [1:0] for_solution_c_l279_c9_6774_iter_1_bin_op_gte_solution_c_l281_c14_efaa_right;
  wire for_solution_c_l279_c9_6774_iter_2_bin_op_and_solution_c_l281_c14_4bb1_left;
  wire for_solution_c_l279_c9_6774_iter_2_bin_op_and_solution_c_l281_c14_4bb1_return_output;
  wire for_solution_c_l279_c9_6774_iter_2_bin_op_and_solution_c_l281_c14_4bb1_right;
  wire [8:0] for_solution_c_l279_c9_6774_iter_2_bin_op_gte_solution_c_l281_c14_efaa_left;
  wire for_solution_c_l279_c9_6774_iter_2_bin_op_gte_solution_c_l281_c14_efaa_return_output;
  wire [1:0] for_solution_c_l279_c9_6774_iter_2_bin_op_gte_solution_c_l281_c14_efaa_right;
  wire [8:0] for_solution_c_l286_c9_23c6_iter_0_bin_op_lte_solution_c_l287_c44_bc34_left;
  wire for_solution_c_l286_c9_23c6_iter_0_bin_op_lte_solution_c_l287_c44_bc34_return_output;
  wire [9:0] for_solution_c_l286_c9_23c6_iter_0_bin_op_lte_solution_c_l287_c44_bc34_right;
  wire [8:0] for_solution_c_l286_c9_23c6_iter_0_bin_op_minus_solution_c_l288_c23_7c02_left;
  wire [9:0] for_solution_c_l286_c9_23c6_iter_0_bin_op_minus_solution_c_l288_c23_7c02_return_output;
  wire [2:0] for_solution_c_l286_c9_23c6_iter_0_bin_op_minus_solution_c_l288_c23_7c02_right;
  wire [8:0] for_solution_c_l286_c9_23c6_iter_1_bin_op_lte_solution_c_l287_c44_bc34_left;
  wire for_solution_c_l286_c9_23c6_iter_1_bin_op_lte_solution_c_l287_c44_bc34_return_output;
  wire [9:0] for_solution_c_l286_c9_23c6_iter_1_bin_op_lte_solution_c_l287_c44_bc34_right;
  wire [8:0] for_solution_c_l286_c9_23c6_iter_1_bin_op_minus_solution_c_l288_c23_7c02_left;
  wire [9:0] for_solution_c_l286_c9_23c6_iter_1_bin_op_minus_solution_c_l288_c23_7c02_return_output;
  wire [2:0] for_solution_c_l286_c9_23c6_iter_1_bin_op_minus_solution_c_l288_c23_7c02_right;
  wire [8:0] for_solution_c_l286_c9_23c6_iter_2_bin_op_lte_solution_c_l287_c44_bc34_left;
  wire for_solution_c_l286_c9_23c6_iter_2_bin_op_lte_solution_c_l287_c44_bc34_return_output;
  wire [9:0] for_solution_c_l286_c9_23c6_iter_2_bin_op_lte_solution_c_l287_c44_bc34_right;
  wire [8:0] for_solution_c_l286_c9_23c6_iter_2_bin_op_minus_solution_c_l288_c23_7c02_left;
  wire [9:0] for_solution_c_l286_c9_23c6_iter_2_bin_op_minus_solution_c_l288_c23_7c02_return_output;
  wire [1:0] for_solution_c_l286_c9_23c6_iter_2_bin_op_minus_solution_c_l288_c23_7c02_right;
  input grid_fragment_last;
  wire grid_fragment_last;
  input grid_last;
  wire grid_last;
  wire input_side_in_end_of_frame;
  wire input_side_in_end_of_frame_mux_solution_c_l153_c3_2e68_cond;
  wire input_side_in_end_of_frame_mux_solution_c_l153_c3_2e68_iffalse;
  wire input_side_in_end_of_frame_mux_solution_c_l153_c3_2e68_iftrue;
  wire input_side_in_end_of_frame_mux_solution_c_l153_c3_2e68_return_output;
  wire input_side_in_end_of_frame_mux_solution_c_l155_c5_4943_cond;
  wire input_side_in_end_of_frame_mux_solution_c_l155_c5_4943_iffalse;
  wire input_side_in_end_of_frame_mux_solution_c_l155_c5_4943_iftrue;
  wire input_side_in_end_of_frame_mux_solution_c_l155_c5_4943_return_output;
  wire input_side_in_end_of_frame_mux_solution_c_l159_c7_1e67_cond;
  wire input_side_in_end_of_frame_mux_solution_c_l159_c7_1e67_iffalse;
  wire input_side_in_end_of_frame_mux_solution_c_l159_c7_1e67_iftrue;
  wire input_side_in_end_of_frame_mux_solution_c_l159_c7_1e67_return_output;
  wire input_side_in_end_of_frame_mux_solution_c_l247_c3_5f6b_cond;
  wire input_side_in_end_of_frame_mux_solution_c_l247_c3_5f6b_iffalse;
  wire input_side_in_end_of_frame_mux_solution_c_l247_c3_5f6b_iftrue;
  wire input_side_in_end_of_frame_mux_solution_c_l247_c3_5f6b_return_output;
  wire input_side_in_end_of_frame_mux_solution_c_l251_c5_4213_cond;
  wire input_side_in_end_of_frame_mux_solution_c_l251_c5_4213_iffalse;
  wire input_side_in_end_of_frame_mux_solution_c_l251_c5_4213_iftrue;
  wire input_side_in_end_of_frame_mux_solution_c_l251_c5_4213_return_output;
  wire input_side_in_end_of_frame_mux_solution_c_l272_c7_a3df_cond;
  wire input_side_in_end_of_frame_mux_solution_c_l272_c7_a3df_iffalse;
  wire input_side_in_end_of_frame_mux_solution_c_l272_c7_a3df_iftrue;
  wire input_side_in_end_of_frame_mux_solution_c_l272_c7_a3df_return_output;
  wire [8:0] line_width_counter;
  wire line_width_counter_mux_solution_c_l153_c3_2e68_cond;
  wire [8:0] line_width_counter_mux_solution_c_l153_c3_2e68_iffalse;
  wire [8:0] line_width_counter_mux_solution_c_l153_c3_2e68_iftrue;
  wire [8:0] line_width_counter_mux_solution_c_l153_c3_2e68_return_output;
  wire line_width_counter_mux_solution_c_l155_c5_4943_cond;
  wire [8:0] line_width_counter_mux_solution_c_l155_c5_4943_iffalse;
  wire [8:0] line_width_counter_mux_solution_c_l155_c5_4943_iftrue;
  wire [8:0] line_width_counter_mux_solution_c_l155_c5_4943_return_output;
  wire line_width_counter_mux_solution_c_l247_c3_5f6b_cond;
  wire [8:0] line_width_counter_mux_solution_c_l247_c3_5f6b_iffalse;
  wire [8:0] line_width_counter_mux_solution_c_l247_c3_5f6b_iftrue;
  wire [8:0] line_width_counter_mux_solution_c_l247_c3_5f6b_return_output;
  wire line_width_counter_mux_solution_c_l251_c5_4213_cond;
  wire [8:0] line_width_counter_mux_solution_c_l251_c5_4213_iffalse;
  wire [8:0] line_width_counter_mux_solution_c_l251_c5_4213_iftrue;
  wire [8:0] line_width_counter_mux_solution_c_l251_c5_4213_return_output;
  wire line_width_counter_mux_solution_c_l272_c7_a3df_cond;
  wire [8:0] line_width_counter_mux_solution_c_l272_c7_a3df_iffalse;
  wire [8:0] line_width_counter_mux_solution_c_l272_c7_a3df_iftrue;
  wire [8:0] line_width_counter_mux_solution_c_l272_c7_a3df_return_output;
  output \module_to_global[done_frame_pulse] ;
  wire \module_to_global[done_frame_pulse] ;
  wire [8:0] num_lines_counter;
  wire num_lines_counter_mux_solution_c_l153_c3_2e68_cond;
  wire [8:0] num_lines_counter_mux_solution_c_l153_c3_2e68_iffalse;
  wire [8:0] num_lines_counter_mux_solution_c_l153_c3_2e68_iftrue;
  wire [8:0] num_lines_counter_mux_solution_c_l153_c3_2e68_return_output;
  wire num_lines_counter_mux_solution_c_l155_c5_4943_cond;
  wire [8:0] num_lines_counter_mux_solution_c_l155_c5_4943_iffalse;
  wire [8:0] num_lines_counter_mux_solution_c_l155_c5_4943_iftrue;
  wire [8:0] num_lines_counter_mux_solution_c_l155_c5_4943_return_output;
  wire num_lines_counter_mux_solution_c_l159_c7_1e67_cond;
  wire [8:0] num_lines_counter_mux_solution_c_l159_c7_1e67_iffalse;
  wire [8:0] num_lines_counter_mux_solution_c_l159_c7_1e67_iftrue;
  wire [8:0] num_lines_counter_mux_solution_c_l159_c7_1e67_return_output;
  wire num_lines_counter_mux_solution_c_l247_c3_5f6b_cond;
  wire [8:0] num_lines_counter_mux_solution_c_l247_c3_5f6b_iffalse;
  wire [8:0] num_lines_counter_mux_solution_c_l247_c3_5f6b_iftrue;
  wire [8:0] num_lines_counter_mux_solution_c_l247_c3_5f6b_return_output;
  wire num_lines_counter_mux_solution_c_l251_c5_4213_cond;
  wire [8:0] num_lines_counter_mux_solution_c_l251_c5_4213_iffalse;
  wire [8:0] num_lines_counter_mux_solution_c_l251_c5_4213_iftrue;
  wire [8:0] num_lines_counter_mux_solution_c_l251_c5_4213_return_output;
  wire num_lines_counter_mux_solution_c_l272_c7_a3df_cond;
  wire [8:0] num_lines_counter_mux_solution_c_l272_c7_a3df_iffalse;
  wire [8:0] num_lines_counter_mux_solution_c_l272_c7_a3df_iftrue;
  wire [8:0] num_lines_counter_mux_solution_c_l272_c7_a3df_return_output;
  wire o_ready_for_data_in_mux_solution_c_l149_c3_b279_cond;
  wire o_ready_for_data_in_mux_solution_c_l149_c3_b279_iffalse;
  wire o_ready_for_data_in_mux_solution_c_l149_c3_b279_iftrue;
  wire o_ready_for_data_in_mux_solution_c_l149_c3_b279_return_output;
  wire [8:0] reg_comb_current_line_width_reg;
  wire [8:0] reg_comb_current_num_lines_reg;
  wire reg_comb_input_side_in_end_of_frame;
  wire [8:0] reg_comb_line_width_counter;
  wire [8:0] reg_comb_num_lines_counter;
  wire [2:0] reg_comb_want_data_from_fifo;
  wire reg_comb_win_x_lte_width;
  wire reg_comb_win_y_lt_num_lines;
  wire reg_comb_win_y_lte_num_lines;
  wire [2:0] reg_comb_win_y_lte_num_lines_minus_i;
  wire [8:0] reg_comb_window;
  wire reg_comb_window_valid;
  wire [8:0] reg_comb_window_x_pos;
  wire [8:0] reg_comb_window_y_pos;
  output \return_output[ready_for_data_in] ;
  wire \return_output[ready_for_data_in] ;
  output [8:0] \return_output[window] ;
  wire [8:0] \return_output[window] ;
  output \return_output[window_valid] ;
  wire \return_output[window_valid] ;
  output [8:0] \return_output[window_x_pos] ;
  wire [8:0] \return_output[window_x_pos] ;
  output [8:0] \return_output[window_y_pos] ;
  wire [8:0] \return_output[window_y_pos] ;
  wire [8:0] slide_window_solution_c_l264_c16_6c14_curr;
  wire [2:0] slide_window_solution_c_l264_c16_6c14_next_input_col;
  wire [8:0] slide_window_solution_c_l264_c16_6c14_return_output;
  wire uint1_array_and4_solution_c_l214_c28_4b75_return_output;
  wire [3:0] uint1_array_and4_solution_c_l214_c28_4b75_x;
  wire [2:0] want_data_from_fifo;
  wire want_data_from_fifo_mux_solution_c_l247_c3_5f6b_cond;
  wire [2:0] want_data_from_fifo_mux_solution_c_l247_c3_5f6b_iffalse;
  wire [2:0] want_data_from_fifo_mux_solution_c_l247_c3_5f6b_iftrue;
  wire [2:0] want_data_from_fifo_mux_solution_c_l247_c3_5f6b_return_output;
  wire want_data_from_fifo_mux_solution_c_l251_c5_4213_cond;
  wire [2:0] want_data_from_fifo_mux_solution_c_l251_c5_4213_iffalse;
  wire [2:0] want_data_from_fifo_mux_solution_c_l251_c5_4213_iftrue;
  wire [2:0] want_data_from_fifo_mux_solution_c_l251_c5_4213_return_output;
  wire want_data_from_fifo_mux_solution_c_l272_c7_a3df_cond;
  wire [2:0] want_data_from_fifo_mux_solution_c_l272_c7_a3df_iffalse;
  wire [2:0] want_data_from_fifo_mux_solution_c_l272_c7_a3df_iftrue;
  wire [2:0] want_data_from_fifo_mux_solution_c_l272_c7_a3df_return_output;
  wire win_x_lte_width;
  wire win_x_lte_width_mux_solution_c_l247_c3_5f6b_cond;
  wire win_x_lte_width_mux_solution_c_l247_c3_5f6b_iffalse;
  wire win_x_lte_width_mux_solution_c_l247_c3_5f6b_iftrue;
  wire win_x_lte_width_mux_solution_c_l247_c3_5f6b_return_output;
  wire win_x_lte_width_mux_solution_c_l251_c5_4213_cond;
  wire win_x_lte_width_mux_solution_c_l251_c5_4213_iffalse;
  wire win_x_lte_width_mux_solution_c_l251_c5_4213_iftrue;
  wire win_x_lte_width_mux_solution_c_l251_c5_4213_return_output;
  wire win_y_lt_num_lines;
  wire win_y_lt_num_lines_mux_solution_c_l247_c3_5f6b_cond;
  wire win_y_lt_num_lines_mux_solution_c_l247_c3_5f6b_iffalse;
  wire win_y_lt_num_lines_mux_solution_c_l247_c3_5f6b_iftrue;
  wire win_y_lt_num_lines_mux_solution_c_l247_c3_5f6b_return_output;
  wire win_y_lt_num_lines_mux_solution_c_l251_c5_4213_cond;
  wire win_y_lt_num_lines_mux_solution_c_l251_c5_4213_iffalse;
  wire win_y_lt_num_lines_mux_solution_c_l251_c5_4213_iftrue;
  wire win_y_lt_num_lines_mux_solution_c_l251_c5_4213_return_output;
  wire win_y_lt_num_lines_mux_solution_c_l272_c7_a3df_cond;
  wire win_y_lt_num_lines_mux_solution_c_l272_c7_a3df_iffalse;
  wire win_y_lt_num_lines_mux_solution_c_l272_c7_a3df_iftrue;
  wire win_y_lt_num_lines_mux_solution_c_l272_c7_a3df_return_output;
  wire win_y_lte_num_lines;
  wire [2:0] win_y_lte_num_lines_minus_i;
  wire win_y_lte_num_lines_minus_i_mux_solution_c_l247_c3_5f6b_cond;
  wire [2:0] win_y_lte_num_lines_minus_i_mux_solution_c_l247_c3_5f6b_iffalse;
  wire [2:0] win_y_lte_num_lines_minus_i_mux_solution_c_l247_c3_5f6b_iftrue;
  wire [2:0] win_y_lte_num_lines_minus_i_mux_solution_c_l247_c3_5f6b_return_output;
  wire win_y_lte_num_lines_minus_i_mux_solution_c_l251_c5_4213_cond;
  wire [2:0] win_y_lte_num_lines_minus_i_mux_solution_c_l251_c5_4213_iffalse;
  wire [2:0] win_y_lte_num_lines_minus_i_mux_solution_c_l251_c5_4213_iftrue;
  wire [2:0] win_y_lte_num_lines_minus_i_mux_solution_c_l251_c5_4213_return_output;
  wire win_y_lte_num_lines_minus_i_mux_solution_c_l272_c7_a3df_cond;
  wire [2:0] win_y_lte_num_lines_minus_i_mux_solution_c_l272_c7_a3df_iffalse;
  wire [2:0] win_y_lte_num_lines_minus_i_mux_solution_c_l272_c7_a3df_iftrue;
  wire [2:0] win_y_lte_num_lines_minus_i_mux_solution_c_l272_c7_a3df_return_output;
  wire win_y_lte_num_lines_mux_solution_c_l247_c3_5f6b_cond;
  wire win_y_lte_num_lines_mux_solution_c_l247_c3_5f6b_iffalse;
  wire win_y_lte_num_lines_mux_solution_c_l247_c3_5f6b_iftrue;
  wire win_y_lte_num_lines_mux_solution_c_l247_c3_5f6b_return_output;
  wire win_y_lte_num_lines_mux_solution_c_l251_c5_4213_cond;
  wire win_y_lte_num_lines_mux_solution_c_l251_c5_4213_iffalse;
  wire win_y_lte_num_lines_mux_solution_c_l251_c5_4213_iftrue;
  wire win_y_lte_num_lines_mux_solution_c_l251_c5_4213_return_output;
  wire win_y_lte_num_lines_mux_solution_c_l272_c7_a3df_cond;
  wire win_y_lte_num_lines_mux_solution_c_l272_c7_a3df_iffalse;
  wire win_y_lte_num_lines_mux_solution_c_l272_c7_a3df_iftrue;
  wire win_y_lte_num_lines_mux_solution_c_l272_c7_a3df_return_output;
  wire [8:0] window;
  wire window_mux_solution_c_l247_c3_5f6b_cond;
  wire [8:0] window_mux_solution_c_l247_c3_5f6b_iffalse;
  wire [8:0] window_mux_solution_c_l247_c3_5f6b_iftrue;
  wire [8:0] window_mux_solution_c_l247_c3_5f6b_return_output;
  wire window_mux_solution_c_l251_c5_4213_cond;
  wire [8:0] window_mux_solution_c_l251_c5_4213_iffalse;
  wire [8:0] window_mux_solution_c_l251_c5_4213_iftrue;
  wire [8:0] window_mux_solution_c_l251_c5_4213_return_output;
  wire window_valid;
  wire window_valid_mux_solution_c_l247_c3_5f6b_cond;
  wire window_valid_mux_solution_c_l247_c3_5f6b_iffalse;
  wire window_valid_mux_solution_c_l247_c3_5f6b_iftrue;
  wire window_valid_mux_solution_c_l247_c3_5f6b_return_output;
  wire window_valid_mux_solution_c_l251_c5_4213_cond;
  wire window_valid_mux_solution_c_l251_c5_4213_iffalse;
  wire window_valid_mux_solution_c_l251_c5_4213_iftrue;
  wire window_valid_mux_solution_c_l251_c5_4213_return_output;
  wire [8:0] window_x_pos;
  wire window_x_pos_mux_solution_c_l247_c3_5f6b_cond;
  wire [8:0] window_x_pos_mux_solution_c_l247_c3_5f6b_iffalse;
  wire [8:0] window_x_pos_mux_solution_c_l247_c3_5f6b_iftrue;
  wire [8:0] window_x_pos_mux_solution_c_l247_c3_5f6b_return_output;
  wire window_x_pos_mux_solution_c_l251_c5_4213_cond;
  wire [8:0] window_x_pos_mux_solution_c_l251_c5_4213_iffalse;
  wire [8:0] window_x_pos_mux_solution_c_l251_c5_4213_iftrue;
  wire [8:0] window_x_pos_mux_solution_c_l251_c5_4213_return_output;
  wire [8:0] window_y_pos;
  wire window_y_pos_mux_solution_c_l247_c3_5f6b_cond;
  wire [8:0] window_y_pos_mux_solution_c_l247_c3_5f6b_iffalse;
  wire [8:0] window_y_pos_mux_solution_c_l247_c3_5f6b_iftrue;
  wire [8:0] window_y_pos_mux_solution_c_l247_c3_5f6b_return_output;
  wire window_y_pos_mux_solution_c_l251_c5_4213_cond;
  wire [8:0] window_y_pos_mux_solution_c_l251_c5_4213_iffalse;
  wire [8:0] window_y_pos_mux_solution_c_l251_c5_4213_iftrue;
  wire [8:0] window_y_pos_mux_solution_c_l251_c5_4213_return_output;
  wire window_y_pos_mux_solution_c_l272_c7_a3df_cond;
  wire [8:0] window_y_pos_mux_solution_c_l272_c7_a3df_iffalse;
  wire [8:0] window_y_pos_mux_solution_c_l272_c7_a3df_iftrue;
  wire [8:0] window_y_pos_mux_solution_c_l272_c7_a3df_return_output;
  assign _101_ = clk_en_internal ? done_frame_pulse_mux_solution_c_l247_c3_5f6b_return_output : 1'h0;
  assign _102_ = clk_en_internal ? reg_comb_window : window;
  always @(posedge clk)
    _103_ <= _102_;
  assign _104_ = clk_en_internal ? reg_comb_window_valid : window_valid;
  always @(posedge clk)
    _105_ <= _104_;
  assign _106_ = clk_en_internal ? reg_comb_line_width_counter : line_width_counter;
  always @(posedge clk)
    _107_ <= _106_;
  assign _108_ = clk_en_internal ? reg_comb_num_lines_counter : num_lines_counter;
  always @(posedge clk)
    _109_ <= _108_;
  assign _110_ = clk_en_internal ? reg_comb_current_line_width_reg : current_line_width_reg;
  always @(posedge clk)
    _111_ <= _110_;
  assign _112_ = clk_en_internal ? reg_comb_current_num_lines_reg : current_num_lines_reg;
  always @(posedge clk)
    _113_ <= _112_;
  assign _114_ = clk_en_internal ? reg_comb_input_side_in_end_of_frame : input_side_in_end_of_frame;
  always @(posedge clk)
    _115_ <= _114_;
  assign _116_ = clk_en_internal ? reg_comb_window_x_pos : window_x_pos;
  always @(posedge clk)
    _117_ <= _116_;
  assign _118_ = clk_en_internal ? reg_comb_window_y_pos : window_y_pos;
  always @(posedge clk)
    _119_ <= _118_;
  assign _120_ = clk_en_internal ? reg_comb_want_data_from_fifo : want_data_from_fifo;
  always @(posedge clk)
    _121_ <= _120_;
  assign _122_ = clk_en_internal ? reg_comb_win_y_lte_num_lines : win_y_lte_num_lines;
  always @(posedge clk)
    _123_ <= _122_;
  assign _124_ = clk_en_internal ? reg_comb_win_y_lt_num_lines : win_y_lt_num_lines;
  always @(posedge clk)
    _125_ <= _124_;
  assign _126_ = clk_en_internal ? reg_comb_win_x_lte_width : win_x_lte_width;
  always @(posedge clk)
    _127_ <= _126_;
  assign _128_ = clk_en_internal ? reg_comb_win_y_lte_num_lines_minus_i : win_y_lte_num_lines_minus_i;
  always @(posedge clk)
    _129_ <= _128_;
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 bin_op_and_solution_c_l153_c6_6e62 (
    .left(bin_op_and_solution_c_l153_c6_6e62_left),
    .return_output(_132_),
    .right(bin_op_and_solution_c_l153_c6_6e62_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 bin_op_and_solution_c_l265_c23_8238 (
    .left(bin_op_and_solution_c_l265_c23_8238_left),
    .return_output(_071_),
    .right(bin_op_and_solution_c_l265_c23_8238_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 bin_op_and_solution_c_l265_c23_a02b (
    .left(bin_op_and_solution_c_l265_c23_a02b_left),
    .return_output(_070_),
    .right(bin_op_and_solution_c_l265_c23_a02b_right)
  );
  bin_op_gte_int9_t_int2_t_0clk_6b4fb28a bin_op_gte_solution_c_l265_c23_7c1c (
    .left(bin_op_gte_solution_c_l265_c23_7c1c_left),
    .return_output(_068_),
    .right(bin_op_gte_solution_c_l265_c23_7c1c_right)
  );
  bin_op_gte_int9_t_int2_t_0clk_6b4fb28a bin_op_gte_solution_c_l265_c45_7188 (
    .left(bin_op_gte_solution_c_l265_c45_7188_left),
    .return_output(_069_),
    .right(bin_op_gte_solution_c_l265_c45_7188_right)
  );
  bin_op_lt_int9_t_int10_t_0clk_1aac2328 bin_op_lt_int9_t_int10_t_solution_c_l239_duplicate_354c (
    .left(bin_op_lt_int9_t_int10_t_solution_c_l239_duplicate_354c_left),
    .return_output(_098_),
    .right(bin_op_lt_int9_t_int10_t_solution_c_l239_duplicate_354c_right)
  );
  bin_op_lt_int9_t_int10_t_0clk_1aac2328 bin_op_lt_int9_t_int10_t_solution_c_l260_c12_9f27_duplicate_df5d (
    .left(bin_op_lt_int9_t_int10_t_solution_c_l260_c12_9f27_duplicate_df5d_left),
    .return_output(_100_),
    .right(bin_op_lt_int9_t_int10_t_solution_c_l260_c12_9f27_duplicate_df5d_right)
  );
  bin_op_lt_int9_t_int10_t_0clk_1aac2328 bin_op_lt_solution_c_l263_c25_b7b8 (
    .left(bin_op_lt_solution_c_l263_c25_b7b8_left),
    .return_output(_066_),
    .right(bin_op_lt_solution_c_l263_c25_b7b8_right)
  );
  bin_op_lt_int9_t_int9_t_0clk_794ce60a bin_op_lt_solution_c_l293_c30_911c (
    .left(bin_op_lt_solution_c_l293_c30_911c_left),
    .return_output(_096_),
    .right(bin_op_lt_solution_c_l293_c30_911c_right)
  );
  bin_op_lte_int9_t_int9_t_0clk_4f202194 bin_op_lte_solution_c_l241_c25_ea4f (
    .left(bin_op_lte_solution_c_l241_c25_ea4f_left),
    .return_output(_024_),
    .right(bin_op_lte_solution_c_l241_c25_ea4f_right)
  );
  bin_op_minus_int9_t_int3_t_0clk_de264c78 bin_op_minus_int9_t_int3_t_solution_c_l239_duplicate_9331 (
    .left(bin_op_minus_int9_t_int3_t_solution_c_l239_duplicate_9331_left),
    .return_output(_097_),
    .right(bin_op_minus_int9_t_int3_t_solution_c_l239_duplicate_9331_right)
  );
  bin_op_minus_int9_t_int3_t_0clk_de264c78 bin_op_minus_int9_t_int3_t_solution_c_l260_c28_029e_duplicate_9a64 (
    .left(bin_op_minus_int9_t_int3_t_solution_c_l260_c28_029e_duplicate_9a64_left),
    .return_output(_099_),
    .right(bin_op_minus_int9_t_int3_t_solution_c_l260_c28_029e_duplicate_9a64_right)
  );
  bin_op_minus_int9_t_int2_t_0clk_de264c78 bin_op_minus_solution_c_l263_c41_43fe (
    .left(bin_op_minus_solution_c_l263_c41_43fe_left),
    .return_output(_065_),
    .right(bin_op_minus_solution_c_l263_c41_43fe_right)
  );
  bin_op_plus_int9_t_int2_t_0clk_de264c78 bin_op_plus_solution_c_l154_c5_d98c (
    .left(bin_op_plus_solution_c_l154_c5_d98c_left),
    .return_output(_138_),
    .right(bin_op_plus_solution_c_l154_c5_d98c_right)
  );
  bin_op_plus_int9_t_int2_t_0clk_de264c78 bin_op_plus_solution_c_l156_c7_9c3b (
    .left(bin_op_plus_solution_c_l156_c7_9c3b_left),
    .return_output(_144_),
    .right(bin_op_plus_solution_c_l156_c7_9c3b_right)
  );
  bin_op_plus_int9_t_int2_t_0clk_de264c78 bin_op_plus_solution_c_l262_c7_516d (
    .left(bin_op_plus_solution_c_l262_c7_516d_left),
    .return_output(_064_),
    .right(bin_op_plus_solution_c_l262_c7_516d_right)
  );
  bin_op_plus_int9_t_int2_t_0clk_de264c78 bin_op_plus_solution_c_l291_c9_bc84 (
    .left(bin_op_plus_solution_c_l291_c9_bc84_left),
    .return_output(_095_),
    .right(bin_op_plus_solution_c_l291_c9_bc84_right)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 current_line_width_mux_solution_c_l153_c3_2e68 (
    .cond(current_line_width_mux_solution_c_l153_c3_2e68_cond),
    .iffalse(current_line_width_mux_solution_c_l153_c3_2e68_iffalse),
    .iftrue(current_line_width_mux_solution_c_l153_c3_2e68_iftrue),
    .return_output(_136_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 current_line_width_mux_solution_c_l155_c5_4943 (
    .cond(current_line_width_mux_solution_c_l155_c5_4943_cond),
    .iffalse(current_line_width_mux_solution_c_l155_c5_4943_iffalse),
    .iftrue(current_line_width_mux_solution_c_l155_c5_4943_iftrue),
    .return_output(_142_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 current_line_width_mux_solution_c_l247_c3_5f6b (
    .cond(current_line_width_mux_solution_c_l247_c3_5f6b_cond),
    .iffalse(current_line_width_mux_solution_c_l247_c3_5f6b_iffalse),
    .iftrue(current_line_width_mux_solution_c_l247_c3_5f6b_iftrue),
    .return_output(_031_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 current_line_width_mux_solution_c_l251_c5_4213 (
    .cond(current_line_width_mux_solution_c_l251_c5_4213_cond),
    .iffalse(current_line_width_mux_solution_c_l251_c5_4213_iffalse),
    .iftrue(current_line_width_mux_solution_c_l251_c5_4213_iftrue),
    .return_output(_046_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 current_line_width_mux_solution_c_l272_c7_a3df (
    .cond(current_line_width_mux_solution_c_l272_c7_a3df_cond),
    .iffalse(current_line_width_mux_solution_c_l272_c7_a3df_iffalse),
    .iftrue(current_line_width_mux_solution_c_l272_c7_a3df_iftrue),
    .return_output(_076_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 current_num_lines_mux_solution_c_l153_c3_2e68 (
    .cond(current_num_lines_mux_solution_c_l153_c3_2e68_cond),
    .iffalse(current_num_lines_mux_solution_c_l153_c3_2e68_iffalse),
    .iftrue(current_num_lines_mux_solution_c_l153_c3_2e68_iftrue),
    .return_output(_137_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 current_num_lines_mux_solution_c_l155_c5_4943 (
    .cond(current_num_lines_mux_solution_c_l155_c5_4943_cond),
    .iffalse(current_num_lines_mux_solution_c_l155_c5_4943_iffalse),
    .iftrue(current_num_lines_mux_solution_c_l155_c5_4943_iftrue),
    .return_output(_143_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 current_num_lines_mux_solution_c_l159_c7_1e67 (
    .cond(current_num_lines_mux_solution_c_l159_c7_1e67_cond),
    .iffalse(current_num_lines_mux_solution_c_l159_c7_1e67_iffalse),
    .iftrue(current_num_lines_mux_solution_c_l159_c7_1e67_iftrue),
    .return_output(_147_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 current_num_lines_mux_solution_c_l247_c3_5f6b (
    .cond(current_num_lines_mux_solution_c_l247_c3_5f6b_cond),
    .iffalse(current_num_lines_mux_solution_c_l247_c3_5f6b_iffalse),
    .iftrue(current_num_lines_mux_solution_c_l247_c3_5f6b_iftrue),
    .return_output(_033_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 current_num_lines_mux_solution_c_l251_c5_4213 (
    .cond(current_num_lines_mux_solution_c_l251_c5_4213_cond),
    .iffalse(current_num_lines_mux_solution_c_l251_c5_4213_iffalse),
    .iftrue(current_num_lines_mux_solution_c_l251_c5_4213_iftrue),
    .return_output(_048_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 current_num_lines_mux_solution_c_l272_c7_a3df (
    .cond(current_num_lines_mux_solution_c_l272_c7_a3df_cond),
    .iffalse(current_num_lines_mux_solution_c_l272_c7_a3df_iffalse),
    .iftrue(current_num_lines_mux_solution_c_l272_c7_a3df_iftrue),
    .return_output(_078_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 done_frame_pulse_mux_solution_c_l247_c3_5f6b (
    .cond(done_frame_pulse_mux_solution_c_l247_c3_5f6b_cond),
    .iffalse(done_frame_pulse_mux_solution_c_l247_c3_5f6b_iffalse),
    .iftrue(done_frame_pulse_mux_solution_c_l247_c3_5f6b_iftrue),
    .return_output(_036_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 done_frame_pulse_mux_solution_c_l251_c5_4213 (
    .cond(done_frame_pulse_mux_solution_c_l251_c5_4213_cond),
    .iffalse(done_frame_pulse_mux_solution_c_l251_c5_4213_iffalse),
    .iftrue(done_frame_pulse_mux_solution_c_l251_c5_4213_iftrue),
    .return_output(_051_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 done_frame_pulse_mux_solution_c_l272_c7_a3df (
    .cond(done_frame_pulse_mux_solution_c_l272_c7_a3df_cond),
    .iffalse(done_frame_pulse_mux_solution_c_l272_c7_a3df_iffalse),
    .iftrue(done_frame_pulse_mux_solution_c_l272_c7_a3df_iftrue),
    .return_output(_080_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 fifo_input_valids_0_mux_solution_c_l149_c3_b279 (
    .cond(fifo_input_valids_0_mux_solution_c_l149_c3_b279_cond),
    .iffalse(fifo_input_valids_0_mux_solution_c_l149_c3_b279_iffalse),
    .iftrue(fifo_input_valids_0_mux_solution_c_l149_c3_b279_iftrue),
    .return_output(_131_)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l168_c3_5d74_iter_0_bin_op_and_solution_c_l176_c32_ca5a (
    .left(for_solution_c_l168_c3_5d74_iter_0_bin_op_and_solution_c_l176_c32_ca5a_left),
    .return_output(_148_),
    .right(for_solution_c_l168_c3_5d74_iter_0_bin_op_and_solution_c_l176_c32_ca5a_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l168_c3_5d74_iter_0_bin_op_and_solution_c_l177_c35_66a3 (
    .left(for_solution_c_l168_c3_5d74_iter_0_bin_op_and_solution_c_l177_c35_66a3_left),
    .return_output(_149_),
    .right(for_solution_c_l168_c3_5d74_iter_0_bin_op_and_solution_c_l177_c35_66a3_right)
  );
  line_fifo_0clk_b45f1687 for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788 (
    .clk(clk),
    .clock_enable(for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788_clock_enable),
    .data_in(for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788_data_in),
    .data_in_valid(for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788_data_in_valid),
    .ready_for_data_out(for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788_ready_for_data_out),
    .\return_output[data_in_ready] (_152_),
    .\return_output[data_out] (_150_),
    .\return_output[data_out_valid] (_151_)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l168_c3_5d74_iter_1_bin_op_and_solution_c_l176_c32_ca5a (
    .left(for_solution_c_l168_c3_5d74_iter_1_bin_op_and_solution_c_l176_c32_ca5a_left),
    .return_output(_153_),
    .right(for_solution_c_l168_c3_5d74_iter_1_bin_op_and_solution_c_l176_c32_ca5a_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l168_c3_5d74_iter_1_bin_op_and_solution_c_l177_c35_66a3 (
    .left(for_solution_c_l168_c3_5d74_iter_1_bin_op_and_solution_c_l177_c35_66a3_left),
    .return_output(_154_),
    .right(for_solution_c_l168_c3_5d74_iter_1_bin_op_and_solution_c_l177_c35_66a3_right)
  );
  line_fifo_0clk_b45f1687 for_solution_c_l168_c3_5d74_iter_1_line_fifo_solution_c_l183_c28_1788 (
    .clk(clk),
    .clock_enable(for_solution_c_l168_c3_5d74_iter_1_line_fifo_solution_c_l183_c28_1788_clock_enable),
    .data_in(for_solution_c_l168_c3_5d74_iter_1_line_fifo_solution_c_l183_c28_1788_data_in),
    .data_in_valid(for_solution_c_l168_c3_5d74_iter_1_line_fifo_solution_c_l183_c28_1788_data_in_valid),
    .ready_for_data_out(for_solution_c_l168_c3_5d74_iter_1_line_fifo_solution_c_l183_c28_1788_ready_for_data_out),
    .\return_output[data_in_ready] (_157_),
    .\return_output[data_out] (_155_),
    .\return_output[data_out_valid] (_156_)
  );
  line_fifo_0clk_b45f1687 for_solution_c_l168_c3_5d74_iter_2_line_fifo_solution_c_l183_c28_1788 (
    .clk(clk),
    .clock_enable(for_solution_c_l168_c3_5d74_iter_2_line_fifo_solution_c_l183_c28_1788_clock_enable),
    .data_in(for_solution_c_l168_c3_5d74_iter_2_line_fifo_solution_c_l183_c28_1788_data_in),
    .data_in_valid(for_solution_c_l168_c3_5d74_iter_2_line_fifo_solution_c_l183_c28_1788_data_in_valid),
    .ready_for_data_out(for_solution_c_l168_c3_5d74_iter_2_line_fifo_solution_c_l183_c28_1788_ready_for_data_out),
    .\return_output[data_in_ready] (_160_),
    .\return_output[data_out] (_158_),
    .\return_output[data_out_valid] (_159_)
  );
  bin_op_or_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l211_c3_1068_iter_0_bin_op_or_solution_c_l212_c32_6eba (
    .left(for_solution_c_l211_c3_1068_iter_0_bin_op_or_solution_c_l212_c32_6eba_left),
    .return_output(_162_),
    .right(for_solution_c_l211_c3_1068_iter_0_bin_op_or_solution_c_l212_c32_6eba_right)
  );
  unary_op_not_uint1_t_0clk_de264c78 for_solution_c_l211_c3_1068_iter_0_unary_op_not_solution_c_l212_c57_d4c8 (
    .expr(for_solution_c_l211_c3_1068_iter_0_unary_op_not_solution_c_l212_c57_d4c8_expr),
    .return_output(_161_)
  );
  bin_op_or_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l211_c3_1068_iter_1_bin_op_or_solution_c_l212_c32_6eba (
    .left(for_solution_c_l211_c3_1068_iter_1_bin_op_or_solution_c_l212_c32_6eba_left),
    .return_output(_164_),
    .right(for_solution_c_l211_c3_1068_iter_1_bin_op_or_solution_c_l212_c32_6eba_right)
  );
  unary_op_not_uint1_t_0clk_de264c78 for_solution_c_l211_c3_1068_iter_1_unary_op_not_solution_c_l212_c57_d4c8 (
    .expr(for_solution_c_l211_c3_1068_iter_1_unary_op_not_solution_c_l212_c57_d4c8_expr),
    .return_output(_163_)
  );
  bin_op_or_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l211_c3_1068_iter_2_bin_op_or_solution_c_l212_c32_6eba (
    .left(for_solution_c_l211_c3_1068_iter_2_bin_op_or_solution_c_l212_c32_6eba_left),
    .return_output(_166_),
    .right(for_solution_c_l211_c3_1068_iter_2_bin_op_or_solution_c_l212_c32_6eba_right)
  );
  unary_op_not_uint1_t_0clk_de264c78 for_solution_c_l211_c3_1068_iter_2_unary_op_not_solution_c_l212_c57_d4c8 (
    .expr(for_solution_c_l211_c3_1068_iter_2_unary_op_not_solution_c_l212_c57_d4c8_expr),
    .return_output(_165_)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l217_c3_08af_iter_0_bin_op_and_solution_c_l218_c34_f37f (
    .left(for_solution_c_l217_c3_08af_iter_0_bin_op_and_solution_c_l218_c34_f37f_left),
    .return_output(_000_),
    .right(for_solution_c_l217_c3_08af_iter_0_bin_op_and_solution_c_l218_c34_f37f_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l217_c3_08af_iter_1_bin_op_and_solution_c_l218_c34_f37f (
    .left(for_solution_c_l217_c3_08af_iter_1_bin_op_and_solution_c_l218_c34_f37f_left),
    .return_output(_001_),
    .right(for_solution_c_l217_c3_08af_iter_1_bin_op_and_solution_c_l218_c34_f37f_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l217_c3_08af_iter_2_bin_op_and_solution_c_l218_c34_f37f (
    .left(for_solution_c_l217_c3_08af_iter_2_bin_op_and_solution_c_l218_c34_f37f_left),
    .return_output(_002_),
    .right(for_solution_c_l217_c3_08af_iter_2_bin_op_and_solution_c_l218_c34_f37f_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l224_c3_8683_iter_0_bin_op_and_solution_c_l227_c8_a2d7 (
    .left(for_solution_c_l224_c3_8683_iter_0_bin_op_and_solution_c_l227_c8_a2d7_left),
    .return_output(_003_),
    .right(for_solution_c_l224_c3_8683_iter_0_bin_op_and_solution_c_l227_c8_a2d7_right)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l224_c3_8683_iter_0_next_input_col_2_mux_solution_c_l227_c5_d5e1 (
    .cond(for_solution_c_l224_c3_8683_iter_0_next_input_col_2_mux_solution_c_l227_c5_d5e1_cond),
    .iffalse(for_solution_c_l224_c3_8683_iter_0_next_input_col_2_mux_solution_c_l227_c5_d5e1_iffalse),
    .iftrue(for_solution_c_l224_c3_8683_iter_0_next_input_col_2_mux_solution_c_l227_c5_d5e1_iftrue),
    .return_output(_004_)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l224_c3_8683_iter_1_bin_op_and_solution_c_l227_c8_a2d7 (
    .left(for_solution_c_l224_c3_8683_iter_1_bin_op_and_solution_c_l227_c8_a2d7_left),
    .return_output(_005_),
    .right(for_solution_c_l224_c3_8683_iter_1_bin_op_and_solution_c_l227_c8_a2d7_right)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l224_c3_8683_iter_1_next_input_col_1_mux_solution_c_l227_c5_d5e1 (
    .cond(for_solution_c_l224_c3_8683_iter_1_next_input_col_1_mux_solution_c_l227_c5_d5e1_cond),
    .iffalse(for_solution_c_l224_c3_8683_iter_1_next_input_col_1_mux_solution_c_l227_c5_d5e1_iffalse),
    .iftrue(for_solution_c_l224_c3_8683_iter_1_next_input_col_1_mux_solution_c_l227_c5_d5e1_iftrue),
    .return_output(_006_)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l224_c3_8683_iter_2_bin_op_and_solution_c_l227_c8_a2d7 (
    .left(for_solution_c_l224_c3_8683_iter_2_bin_op_and_solution_c_l227_c8_a2d7_left),
    .return_output(_007_),
    .right(for_solution_c_l224_c3_8683_iter_2_bin_op_and_solution_c_l227_c8_a2d7_right)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l224_c3_8683_iter_2_next_input_col_0_mux_solution_c_l227_c5_d5e1 (
    .cond(for_solution_c_l224_c3_8683_iter_2_next_input_col_0_mux_solution_c_l227_c5_d5e1_cond),
    .iffalse(for_solution_c_l224_c3_8683_iter_2_next_input_col_0_mux_solution_c_l227_c5_d5e1_iffalse),
    .iftrue(for_solution_c_l224_c3_8683_iter_2_next_input_col_0_mux_solution_c_l227_c5_d5e1_iftrue),
    .return_output(_008_)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l233_c3_2dcf_iter_0_bin_op_and_solution_c_l235_c8_37e4 (
    .left(for_solution_c_l233_c3_2dcf_iter_0_bin_op_and_solution_c_l235_c8_37e4_left),
    .return_output(_013_),
    .right(for_solution_c_l233_c3_2dcf_iter_0_bin_op_and_solution_c_l235_c8_37e4_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l233_c3_2dcf_iter_0_bin_op_and_solution_c_l235_c8_ab2a (
    .left(for_solution_c_l233_c3_2dcf_iter_0_bin_op_and_solution_c_l235_c8_ab2a_left),
    .return_output(_012_),
    .right(for_solution_c_l233_c3_2dcf_iter_0_bin_op_and_solution_c_l235_c8_ab2a_right)
  );
  bin_op_gte_int9_t_int2_t_0clk_6b4fb28a for_solution_c_l233_c3_2dcf_iter_0_bin_op_gte_solution_c_l235_c8_ce82 (
    .left(for_solution_c_l233_c3_2dcf_iter_0_bin_op_gte_solution_c_l235_c8_ce82_left),
    .return_output(_009_),
    .right(for_solution_c_l233_c3_2dcf_iter_0_bin_op_gte_solution_c_l235_c8_ce82_right)
  );
  bin_op_lte_int9_t_int10_t_0clk_6b4fb28a for_solution_c_l233_c3_2dcf_iter_0_bin_op_lte_solution_c_l236_c8_f1b1 (
    .left(for_solution_c_l233_c3_2dcf_iter_0_bin_op_lte_solution_c_l236_c8_f1b1_left),
    .return_output(_011_),
    .right(for_solution_c_l233_c3_2dcf_iter_0_bin_op_lte_solution_c_l236_c8_f1b1_right)
  );
  bin_op_minus_int9_t_int3_t_0clk_de264c78 for_solution_c_l233_c3_2dcf_iter_0_bin_op_minus_solution_c_l237_c9_090e (
    .left(for_solution_c_l233_c3_2dcf_iter_0_bin_op_minus_solution_c_l237_c9_090e_left),
    .return_output(_010_),
    .right(for_solution_c_l233_c3_2dcf_iter_0_bin_op_minus_solution_c_l237_c9_090e_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l233_c3_2dcf_iter_1_bin_op_and_solution_c_l235_c8_37e4 (
    .left(for_solution_c_l233_c3_2dcf_iter_1_bin_op_and_solution_c_l235_c8_37e4_left),
    .return_output(_018_),
    .right(for_solution_c_l233_c3_2dcf_iter_1_bin_op_and_solution_c_l235_c8_37e4_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l233_c3_2dcf_iter_1_bin_op_and_solution_c_l235_c8_ab2a (
    .left(for_solution_c_l233_c3_2dcf_iter_1_bin_op_and_solution_c_l235_c8_ab2a_left),
    .return_output(_017_),
    .right(for_solution_c_l233_c3_2dcf_iter_1_bin_op_and_solution_c_l235_c8_ab2a_right)
  );
  bin_op_gte_int9_t_int2_t_0clk_6b4fb28a for_solution_c_l233_c3_2dcf_iter_1_bin_op_gte_solution_c_l235_c8_ce82 (
    .left(for_solution_c_l233_c3_2dcf_iter_1_bin_op_gte_solution_c_l235_c8_ce82_left),
    .return_output(_014_),
    .right(for_solution_c_l233_c3_2dcf_iter_1_bin_op_gte_solution_c_l235_c8_ce82_right)
  );
  bin_op_lte_int9_t_int10_t_0clk_6b4fb28a for_solution_c_l233_c3_2dcf_iter_1_bin_op_lte_solution_c_l236_c8_f1b1 (
    .left(for_solution_c_l233_c3_2dcf_iter_1_bin_op_lte_solution_c_l236_c8_f1b1_left),
    .return_output(_016_),
    .right(for_solution_c_l233_c3_2dcf_iter_1_bin_op_lte_solution_c_l236_c8_f1b1_right)
  );
  bin_op_minus_int9_t_int2_t_0clk_de264c78 for_solution_c_l233_c3_2dcf_iter_1_bin_op_minus_solution_c_l237_c9_090e (
    .left(for_solution_c_l233_c3_2dcf_iter_1_bin_op_minus_solution_c_l237_c9_090e_left),
    .return_output(_015_),
    .right(for_solution_c_l233_c3_2dcf_iter_1_bin_op_minus_solution_c_l237_c9_090e_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l233_c3_2dcf_iter_2_bin_op_and_solution_c_l235_c8_37e4 (
    .left(for_solution_c_l233_c3_2dcf_iter_2_bin_op_and_solution_c_l235_c8_37e4_left),
    .return_output(_023_),
    .right(for_solution_c_l233_c3_2dcf_iter_2_bin_op_and_solution_c_l235_c8_37e4_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l233_c3_2dcf_iter_2_bin_op_and_solution_c_l235_c8_ab2a (
    .left(for_solution_c_l233_c3_2dcf_iter_2_bin_op_and_solution_c_l235_c8_ab2a_left),
    .return_output(_022_),
    .right(for_solution_c_l233_c3_2dcf_iter_2_bin_op_and_solution_c_l235_c8_ab2a_right)
  );
  bin_op_gte_int9_t_int2_t_0clk_6b4fb28a for_solution_c_l233_c3_2dcf_iter_2_bin_op_gte_solution_c_l235_c8_ce82 (
    .left(for_solution_c_l233_c3_2dcf_iter_2_bin_op_gte_solution_c_l235_c8_ce82_left),
    .return_output(_019_),
    .right(for_solution_c_l233_c3_2dcf_iter_2_bin_op_gte_solution_c_l235_c8_ce82_right)
  );
  bin_op_lte_int9_t_int10_t_0clk_6b4fb28a for_solution_c_l233_c3_2dcf_iter_2_bin_op_lte_solution_c_l236_c8_f1b1 (
    .left(for_solution_c_l233_c3_2dcf_iter_2_bin_op_lte_solution_c_l236_c8_f1b1_left),
    .return_output(_021_),
    .right(for_solution_c_l233_c3_2dcf_iter_2_bin_op_lte_solution_c_l236_c8_f1b1_right)
  );
  bin_op_minus_int9_t_int2_t_0clk_de264c78 for_solution_c_l233_c3_2dcf_iter_2_bin_op_minus_solution_c_l237_c9_090e (
    .left(for_solution_c_l233_c3_2dcf_iter_2_bin_op_minus_solution_c_l237_c9_090e_left),
    .return_output(_020_),
    .right(for_solution_c_l233_c3_2dcf_iter_2_bin_op_minus_solution_c_l237_c9_090e_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l253_c7_deca_iter_0_bin_op_and_solution_c_l255_c12_12e3 (
    .left(for_solution_c_l253_c7_deca_iter_0_bin_op_and_solution_c_l255_c12_12e3_left),
    .return_output(_056_),
    .right(for_solution_c_l253_c7_deca_iter_0_bin_op_and_solution_c_l255_c12_12e3_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l253_c7_deca_iter_0_bin_op_and_solution_c_l255_c12_bcb6 (
    .left(for_solution_c_l253_c7_deca_iter_0_bin_op_and_solution_c_l255_c12_bcb6_left),
    .return_output(_057_),
    .right(for_solution_c_l253_c7_deca_iter_0_bin_op_and_solution_c_l255_c12_bcb6_right)
  );
  bin_op_gte_int9_t_int2_t_0clk_6b4fb28a for_solution_c_l253_c7_deca_iter_0_bin_op_gte_solution_c_l255_c12_d6e8 (
    .left(for_solution_c_l253_c7_deca_iter_0_bin_op_gte_solution_c_l255_c12_d6e8_left),
    .return_output(_055_),
    .right(for_solution_c_l253_c7_deca_iter_0_bin_op_gte_solution_c_l255_c12_d6e8_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l253_c7_deca_iter_1_bin_op_and_solution_c_l255_c12_12e3 (
    .left(for_solution_c_l253_c7_deca_iter_1_bin_op_and_solution_c_l255_c12_12e3_left),
    .return_output(_059_),
    .right(for_solution_c_l253_c7_deca_iter_1_bin_op_and_solution_c_l255_c12_12e3_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l253_c7_deca_iter_1_bin_op_and_solution_c_l255_c12_bcb6 (
    .left(for_solution_c_l253_c7_deca_iter_1_bin_op_and_solution_c_l255_c12_bcb6_left),
    .return_output(_060_),
    .right(for_solution_c_l253_c7_deca_iter_1_bin_op_and_solution_c_l255_c12_bcb6_right)
  );
  bin_op_gte_int9_t_int2_t_0clk_6b4fb28a for_solution_c_l253_c7_deca_iter_1_bin_op_gte_solution_c_l255_c12_d6e8 (
    .left(for_solution_c_l253_c7_deca_iter_1_bin_op_gte_solution_c_l255_c12_d6e8_left),
    .return_output(_058_),
    .right(for_solution_c_l253_c7_deca_iter_1_bin_op_gte_solution_c_l255_c12_d6e8_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l253_c7_deca_iter_2_bin_op_and_solution_c_l255_c12_12e3 (
    .left(for_solution_c_l253_c7_deca_iter_2_bin_op_and_solution_c_l255_c12_12e3_left),
    .return_output(_062_),
    .right(for_solution_c_l253_c7_deca_iter_2_bin_op_and_solution_c_l255_c12_12e3_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l253_c7_deca_iter_2_bin_op_and_solution_c_l255_c12_bcb6 (
    .left(for_solution_c_l253_c7_deca_iter_2_bin_op_and_solution_c_l255_c12_bcb6_left),
    .return_output(_063_),
    .right(for_solution_c_l253_c7_deca_iter_2_bin_op_and_solution_c_l255_c12_bcb6_right)
  );
  bin_op_gte_int9_t_int2_t_0clk_6b4fb28a for_solution_c_l253_c7_deca_iter_2_bin_op_gte_solution_c_l255_c12_d6e8 (
    .left(for_solution_c_l253_c7_deca_iter_2_bin_op_gte_solution_c_l255_c12_d6e8_left),
    .return_output(_061_),
    .right(for_solution_c_l253_c7_deca_iter_2_bin_op_gte_solution_c_l255_c12_d6e8_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l279_c9_6774_iter_0_bin_op_and_solution_c_l281_c14_4bb1 (
    .left(for_solution_c_l279_c9_6774_iter_0_bin_op_and_solution_c_l281_c14_4bb1_left),
    .return_output(_084_),
    .right(for_solution_c_l279_c9_6774_iter_0_bin_op_and_solution_c_l281_c14_4bb1_right)
  );
  bin_op_gte_int9_t_int3_t_0clk_6b4fb28a for_solution_c_l279_c9_6774_iter_0_bin_op_gte_solution_c_l281_c14_efaa (
    .left(for_solution_c_l279_c9_6774_iter_0_bin_op_gte_solution_c_l281_c14_efaa_left),
    .return_output(_083_),
    .right(for_solution_c_l279_c9_6774_iter_0_bin_op_gte_solution_c_l281_c14_efaa_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l279_c9_6774_iter_1_bin_op_and_solution_c_l281_c14_4bb1 (
    .left(for_solution_c_l279_c9_6774_iter_1_bin_op_and_solution_c_l281_c14_4bb1_left),
    .return_output(_086_),
    .right(for_solution_c_l279_c9_6774_iter_1_bin_op_and_solution_c_l281_c14_4bb1_right)
  );
  bin_op_gte_int9_t_int2_t_0clk_6b4fb28a for_solution_c_l279_c9_6774_iter_1_bin_op_gte_solution_c_l281_c14_efaa (
    .left(for_solution_c_l279_c9_6774_iter_1_bin_op_gte_solution_c_l281_c14_efaa_left),
    .return_output(_085_),
    .right(for_solution_c_l279_c9_6774_iter_1_bin_op_gte_solution_c_l281_c14_efaa_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 for_solution_c_l279_c9_6774_iter_2_bin_op_and_solution_c_l281_c14_4bb1 (
    .left(for_solution_c_l279_c9_6774_iter_2_bin_op_and_solution_c_l281_c14_4bb1_left),
    .return_output(_088_),
    .right(for_solution_c_l279_c9_6774_iter_2_bin_op_and_solution_c_l281_c14_4bb1_right)
  );
  bin_op_gte_int9_t_int2_t_0clk_6b4fb28a for_solution_c_l279_c9_6774_iter_2_bin_op_gte_solution_c_l281_c14_efaa (
    .left(for_solution_c_l279_c9_6774_iter_2_bin_op_gte_solution_c_l281_c14_efaa_left),
    .return_output(_087_),
    .right(for_solution_c_l279_c9_6774_iter_2_bin_op_gte_solution_c_l281_c14_efaa_right)
  );
  bin_op_lte_int9_t_int10_t_0clk_6b4fb28a for_solution_c_l286_c9_23c6_iter_0_bin_op_lte_solution_c_l287_c44_bc34 (
    .left(for_solution_c_l286_c9_23c6_iter_0_bin_op_lte_solution_c_l287_c44_bc34_left),
    .return_output(_090_),
    .right(for_solution_c_l286_c9_23c6_iter_0_bin_op_lte_solution_c_l287_c44_bc34_right)
  );
  bin_op_minus_int9_t_int3_t_0clk_de264c78 for_solution_c_l286_c9_23c6_iter_0_bin_op_minus_solution_c_l288_c23_7c02 (
    .left(for_solution_c_l286_c9_23c6_iter_0_bin_op_minus_solution_c_l288_c23_7c02_left),
    .return_output(_089_),
    .right(for_solution_c_l286_c9_23c6_iter_0_bin_op_minus_solution_c_l288_c23_7c02_right)
  );
  bin_op_lte_int9_t_int10_t_0clk_6b4fb28a for_solution_c_l286_c9_23c6_iter_1_bin_op_lte_solution_c_l287_c44_bc34 (
    .left(for_solution_c_l286_c9_23c6_iter_1_bin_op_lte_solution_c_l287_c44_bc34_left),
    .return_output(_092_),
    .right(for_solution_c_l286_c9_23c6_iter_1_bin_op_lte_solution_c_l287_c44_bc34_right)
  );
  bin_op_minus_int9_t_int3_t_0clk_de264c78 for_solution_c_l286_c9_23c6_iter_1_bin_op_minus_solution_c_l288_c23_7c02 (
    .left(for_solution_c_l286_c9_23c6_iter_1_bin_op_minus_solution_c_l288_c23_7c02_left),
    .return_output(_091_),
    .right(for_solution_c_l286_c9_23c6_iter_1_bin_op_minus_solution_c_l288_c23_7c02_right)
  );
  bin_op_lte_int9_t_int10_t_0clk_6b4fb28a for_solution_c_l286_c9_23c6_iter_2_bin_op_lte_solution_c_l287_c44_bc34 (
    .left(for_solution_c_l286_c9_23c6_iter_2_bin_op_lte_solution_c_l287_c44_bc34_left),
    .return_output(_094_),
    .right(for_solution_c_l286_c9_23c6_iter_2_bin_op_lte_solution_c_l287_c44_bc34_right)
  );
  bin_op_minus_int9_t_int2_t_0clk_de264c78 for_solution_c_l286_c9_23c6_iter_2_bin_op_minus_solution_c_l288_c23_7c02 (
    .left(for_solution_c_l286_c9_23c6_iter_2_bin_op_minus_solution_c_l288_c23_7c02_left),
    .return_output(_093_),
    .right(for_solution_c_l286_c9_23c6_iter_2_bin_op_minus_solution_c_l288_c23_7c02_right)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 input_side_in_end_of_frame_mux_solution_c_l153_c3_2e68 (
    .cond(input_side_in_end_of_frame_mux_solution_c_l153_c3_2e68_cond),
    .iffalse(input_side_in_end_of_frame_mux_solution_c_l153_c3_2e68_iffalse),
    .iftrue(input_side_in_end_of_frame_mux_solution_c_l153_c3_2e68_iftrue),
    .return_output(_135_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 input_side_in_end_of_frame_mux_solution_c_l155_c5_4943 (
    .cond(input_side_in_end_of_frame_mux_solution_c_l155_c5_4943_cond),
    .iffalse(input_side_in_end_of_frame_mux_solution_c_l155_c5_4943_iffalse),
    .iftrue(input_side_in_end_of_frame_mux_solution_c_l155_c5_4943_iftrue),
    .return_output(_141_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 input_side_in_end_of_frame_mux_solution_c_l159_c7_1e67 (
    .cond(input_side_in_end_of_frame_mux_solution_c_l159_c7_1e67_cond),
    .iffalse(input_side_in_end_of_frame_mux_solution_c_l159_c7_1e67_iffalse),
    .iftrue(input_side_in_end_of_frame_mux_solution_c_l159_c7_1e67_iftrue),
    .return_output(_146_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 input_side_in_end_of_frame_mux_solution_c_l247_c3_5f6b (
    .cond(input_side_in_end_of_frame_mux_solution_c_l247_c3_5f6b_cond),
    .iffalse(input_side_in_end_of_frame_mux_solution_c_l247_c3_5f6b_iffalse),
    .iftrue(input_side_in_end_of_frame_mux_solution_c_l247_c3_5f6b_iftrue),
    .return_output(_029_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 input_side_in_end_of_frame_mux_solution_c_l251_c5_4213 (
    .cond(input_side_in_end_of_frame_mux_solution_c_l251_c5_4213_cond),
    .iffalse(input_side_in_end_of_frame_mux_solution_c_l251_c5_4213_iffalse),
    .iftrue(input_side_in_end_of_frame_mux_solution_c_l251_c5_4213_iftrue),
    .return_output(_044_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 input_side_in_end_of_frame_mux_solution_c_l272_c7_a3df (
    .cond(input_side_in_end_of_frame_mux_solution_c_l272_c7_a3df_cond),
    .iffalse(input_side_in_end_of_frame_mux_solution_c_l272_c7_a3df_iffalse),
    .iftrue(input_side_in_end_of_frame_mux_solution_c_l272_c7_a3df_iftrue),
    .return_output(_074_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 line_width_counter_mux_solution_c_l153_c3_2e68 (
    .cond(line_width_counter_mux_solution_c_l153_c3_2e68_cond),
    .iffalse(line_width_counter_mux_solution_c_l153_c3_2e68_iffalse),
    .iftrue(line_width_counter_mux_solution_c_l153_c3_2e68_iftrue),
    .return_output(_134_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 line_width_counter_mux_solution_c_l155_c5_4943 (
    .cond(line_width_counter_mux_solution_c_l155_c5_4943_cond),
    .iffalse(line_width_counter_mux_solution_c_l155_c5_4943_iffalse),
    .iftrue(line_width_counter_mux_solution_c_l155_c5_4943_iftrue),
    .return_output(_140_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 line_width_counter_mux_solution_c_l247_c3_5f6b (
    .cond(line_width_counter_mux_solution_c_l247_c3_5f6b_cond),
    .iffalse(line_width_counter_mux_solution_c_l247_c3_5f6b_iffalse),
    .iftrue(line_width_counter_mux_solution_c_l247_c3_5f6b_iftrue),
    .return_output(_026_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 line_width_counter_mux_solution_c_l251_c5_4213 (
    .cond(line_width_counter_mux_solution_c_l251_c5_4213_cond),
    .iffalse(line_width_counter_mux_solution_c_l251_c5_4213_iffalse),
    .iftrue(line_width_counter_mux_solution_c_l251_c5_4213_iftrue),
    .return_output(_041_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 line_width_counter_mux_solution_c_l272_c7_a3df (
    .cond(line_width_counter_mux_solution_c_l272_c7_a3df_cond),
    .iffalse(line_width_counter_mux_solution_c_l272_c7_a3df_iffalse),
    .iftrue(line_width_counter_mux_solution_c_l272_c7_a3df_iftrue),
    .return_output(_073_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 num_lines_counter_mux_solution_c_l153_c3_2e68 (
    .cond(num_lines_counter_mux_solution_c_l153_c3_2e68_cond),
    .iffalse(num_lines_counter_mux_solution_c_l153_c3_2e68_iffalse),
    .iftrue(num_lines_counter_mux_solution_c_l153_c3_2e68_iftrue),
    .return_output(_133_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 num_lines_counter_mux_solution_c_l155_c5_4943 (
    .cond(num_lines_counter_mux_solution_c_l155_c5_4943_cond),
    .iffalse(num_lines_counter_mux_solution_c_l155_c5_4943_iffalse),
    .iftrue(num_lines_counter_mux_solution_c_l155_c5_4943_iftrue),
    .return_output(_139_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 num_lines_counter_mux_solution_c_l159_c7_1e67 (
    .cond(num_lines_counter_mux_solution_c_l159_c7_1e67_cond),
    .iffalse(num_lines_counter_mux_solution_c_l159_c7_1e67_iffalse),
    .iftrue(num_lines_counter_mux_solution_c_l159_c7_1e67_iftrue),
    .return_output(_145_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 num_lines_counter_mux_solution_c_l247_c3_5f6b (
    .cond(num_lines_counter_mux_solution_c_l247_c3_5f6b_cond),
    .iffalse(num_lines_counter_mux_solution_c_l247_c3_5f6b_iffalse),
    .iftrue(num_lines_counter_mux_solution_c_l247_c3_5f6b_iftrue),
    .return_output(_025_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 num_lines_counter_mux_solution_c_l251_c5_4213 (
    .cond(num_lines_counter_mux_solution_c_l251_c5_4213_cond),
    .iffalse(num_lines_counter_mux_solution_c_l251_c5_4213_iffalse),
    .iftrue(num_lines_counter_mux_solution_c_l251_c5_4213_iftrue),
    .return_output(_040_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 num_lines_counter_mux_solution_c_l272_c7_a3df (
    .cond(num_lines_counter_mux_solution_c_l272_c7_a3df_cond),
    .iffalse(num_lines_counter_mux_solution_c_l272_c7_a3df_iffalse),
    .iftrue(num_lines_counter_mux_solution_c_l272_c7_a3df_iftrue),
    .return_output(_072_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 o_ready_for_data_in_mux_solution_c_l149_c3_b279 (
    .cond(o_ready_for_data_in_mux_solution_c_l149_c3_b279_cond),
    .iffalse(o_ready_for_data_in_mux_solution_c_l149_c3_b279_iffalse),
    .iftrue(o_ready_for_data_in_mux_solution_c_l149_c3_b279_iftrue),
    .return_output(_130_)
  );
  slide_window_0clk_098d5770 slide_window_solution_c_l264_c16_6c14 (
    .\curr[data] (slide_window_solution_c_l264_c16_6c14_curr),
    .next_input_col(slide_window_solution_c_l264_c16_6c14_next_input_col),
    .\return_output[data] (_067_)
  );
  uint1_array_and4_0clk_e595f783 uint1_array_and4_solution_c_l214_c28_4b75 (
    .return_output(_167_),
    .x(uint1_array_and4_solution_c_l214_c28_4b75_x)
  );
  mux_uint1_t_uint1_t_3_uint1_t_3_0clk_de264c78 want_data_from_fifo_mux_solution_c_l247_c3_5f6b (
    .cond(want_data_from_fifo_mux_solution_c_l247_c3_5f6b_cond),
    .iffalse(want_data_from_fifo_mux_solution_c_l247_c3_5f6b_iffalse),
    .iftrue(want_data_from_fifo_mux_solution_c_l247_c3_5f6b_iftrue),
    .return_output(_032_)
  );
  mux_uint1_t_uint1_t_3_uint1_t_3_0clk_de264c78 want_data_from_fifo_mux_solution_c_l251_c5_4213 (
    .cond(want_data_from_fifo_mux_solution_c_l251_c5_4213_cond),
    .iffalse(want_data_from_fifo_mux_solution_c_l251_c5_4213_iffalse),
    .iftrue(want_data_from_fifo_mux_solution_c_l251_c5_4213_iftrue),
    .return_output(_047_)
  );
  mux_uint1_t_uint1_t_3_uint1_t_3_0clk_de264c78 want_data_from_fifo_mux_solution_c_l272_c7_a3df (
    .cond(want_data_from_fifo_mux_solution_c_l272_c7_a3df_cond),
    .iffalse(want_data_from_fifo_mux_solution_c_l272_c7_a3df_iffalse),
    .iftrue(want_data_from_fifo_mux_solution_c_l272_c7_a3df_iftrue),
    .return_output(_077_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 win_x_lte_width_mux_solution_c_l247_c3_5f6b (
    .cond(win_x_lte_width_mux_solution_c_l247_c3_5f6b_cond),
    .iffalse(win_x_lte_width_mux_solution_c_l247_c3_5f6b_iffalse),
    .iftrue(win_x_lte_width_mux_solution_c_l247_c3_5f6b_iftrue),
    .return_output(_038_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 win_x_lte_width_mux_solution_c_l251_c5_4213 (
    .cond(win_x_lte_width_mux_solution_c_l251_c5_4213_cond),
    .iffalse(win_x_lte_width_mux_solution_c_l251_c5_4213_iffalse),
    .iftrue(win_x_lte_width_mux_solution_c_l251_c5_4213_iftrue),
    .return_output(_053_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 win_y_lt_num_lines_mux_solution_c_l247_c3_5f6b (
    .cond(win_y_lt_num_lines_mux_solution_c_l247_c3_5f6b_cond),
    .iffalse(win_y_lt_num_lines_mux_solution_c_l247_c3_5f6b_iffalse),
    .iftrue(win_y_lt_num_lines_mux_solution_c_l247_c3_5f6b_iftrue),
    .return_output(_039_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 win_y_lt_num_lines_mux_solution_c_l251_c5_4213 (
    .cond(win_y_lt_num_lines_mux_solution_c_l251_c5_4213_cond),
    .iffalse(win_y_lt_num_lines_mux_solution_c_l251_c5_4213_iffalse),
    .iftrue(win_y_lt_num_lines_mux_solution_c_l251_c5_4213_iftrue),
    .return_output(_054_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 win_y_lt_num_lines_mux_solution_c_l272_c7_a3df (
    .cond(win_y_lt_num_lines_mux_solution_c_l272_c7_a3df_cond),
    .iffalse(win_y_lt_num_lines_mux_solution_c_l272_c7_a3df_iffalse),
    .iftrue(win_y_lt_num_lines_mux_solution_c_l272_c7_a3df_iftrue),
    .return_output(_082_)
  );
  mux_uint1_t_uint1_t_3_uint1_t_3_0clk_de264c78 win_y_lte_num_lines_minus_i_mux_solution_c_l247_c3_5f6b (
    .cond(win_y_lte_num_lines_minus_i_mux_solution_c_l247_c3_5f6b_cond),
    .iffalse(win_y_lte_num_lines_minus_i_mux_solution_c_l247_c3_5f6b_iffalse),
    .iftrue(win_y_lte_num_lines_minus_i_mux_solution_c_l247_c3_5f6b_iftrue),
    .return_output(_034_)
  );
  mux_uint1_t_uint1_t_3_uint1_t_3_0clk_de264c78 win_y_lte_num_lines_minus_i_mux_solution_c_l251_c5_4213 (
    .cond(win_y_lte_num_lines_minus_i_mux_solution_c_l251_c5_4213_cond),
    .iffalse(win_y_lte_num_lines_minus_i_mux_solution_c_l251_c5_4213_iffalse),
    .iftrue(win_y_lte_num_lines_minus_i_mux_solution_c_l251_c5_4213_iftrue),
    .return_output(_049_)
  );
  mux_uint1_t_uint1_t_3_uint1_t_3_0clk_de264c78 win_y_lte_num_lines_minus_i_mux_solution_c_l272_c7_a3df (
    .cond(win_y_lte_num_lines_minus_i_mux_solution_c_l272_c7_a3df_cond),
    .iffalse(win_y_lte_num_lines_minus_i_mux_solution_c_l272_c7_a3df_iffalse),
    .iftrue(win_y_lte_num_lines_minus_i_mux_solution_c_l272_c7_a3df_iftrue),
    .return_output(_079_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 win_y_lte_num_lines_mux_solution_c_l247_c3_5f6b (
    .cond(win_y_lte_num_lines_mux_solution_c_l247_c3_5f6b_cond),
    .iffalse(win_y_lte_num_lines_mux_solution_c_l247_c3_5f6b_iffalse),
    .iftrue(win_y_lte_num_lines_mux_solution_c_l247_c3_5f6b_iftrue),
    .return_output(_037_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 win_y_lte_num_lines_mux_solution_c_l251_c5_4213 (
    .cond(win_y_lte_num_lines_mux_solution_c_l251_c5_4213_cond),
    .iffalse(win_y_lte_num_lines_mux_solution_c_l251_c5_4213_iffalse),
    .iftrue(win_y_lte_num_lines_mux_solution_c_l251_c5_4213_iftrue),
    .return_output(_052_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 win_y_lte_num_lines_mux_solution_c_l272_c7_a3df (
    .cond(win_y_lte_num_lines_mux_solution_c_l272_c7_a3df_cond),
    .iffalse(win_y_lte_num_lines_mux_solution_c_l272_c7_a3df_iffalse),
    .iftrue(win_y_lte_num_lines_mux_solution_c_l272_c7_a3df_iftrue),
    .return_output(_081_)
  );
  mux_uint1_t_window_t_window_t_0clk_de264c78 window_mux_solution_c_l247_c3_5f6b (
    .cond(window_mux_solution_c_l247_c3_5f6b_cond),
    .\iffalse[data] (window_mux_solution_c_l247_c3_5f6b_iffalse),
    .\iftrue[data] (window_mux_solution_c_l247_c3_5f6b_iftrue),
    .\return_output[data] (_028_)
  );
  mux_uint1_t_window_t_window_t_0clk_de264c78 window_mux_solution_c_l251_c5_4213 (
    .cond(window_mux_solution_c_l251_c5_4213_cond),
    .\iffalse[data] (window_mux_solution_c_l251_c5_4213_iffalse),
    .\iftrue[data] (window_mux_solution_c_l251_c5_4213_iftrue),
    .\return_output[data] (_043_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 window_valid_mux_solution_c_l247_c3_5f6b (
    .cond(window_valid_mux_solution_c_l247_c3_5f6b_cond),
    .iffalse(window_valid_mux_solution_c_l247_c3_5f6b_iffalse),
    .iftrue(window_valid_mux_solution_c_l247_c3_5f6b_iftrue),
    .return_output(_027_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 window_valid_mux_solution_c_l251_c5_4213 (
    .cond(window_valid_mux_solution_c_l251_c5_4213_cond),
    .iffalse(window_valid_mux_solution_c_l251_c5_4213_iffalse),
    .iftrue(window_valid_mux_solution_c_l251_c5_4213_iftrue),
    .return_output(_042_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 window_x_pos_mux_solution_c_l247_c3_5f6b (
    .cond(window_x_pos_mux_solution_c_l247_c3_5f6b_cond),
    .iffalse(window_x_pos_mux_solution_c_l247_c3_5f6b_iffalse),
    .iftrue(window_x_pos_mux_solution_c_l247_c3_5f6b_iftrue),
    .return_output(_035_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 window_x_pos_mux_solution_c_l251_c5_4213 (
    .cond(window_x_pos_mux_solution_c_l251_c5_4213_cond),
    .iffalse(window_x_pos_mux_solution_c_l251_c5_4213_iffalse),
    .iftrue(window_x_pos_mux_solution_c_l251_c5_4213_iftrue),
    .return_output(_050_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 window_y_pos_mux_solution_c_l247_c3_5f6b (
    .cond(window_y_pos_mux_solution_c_l247_c3_5f6b_cond),
    .iffalse(window_y_pos_mux_solution_c_l247_c3_5f6b_iffalse),
    .iftrue(window_y_pos_mux_solution_c_l247_c3_5f6b_iftrue),
    .return_output(_030_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 window_y_pos_mux_solution_c_l251_c5_4213 (
    .cond(window_y_pos_mux_solution_c_l251_c5_4213_cond),
    .iffalse(window_y_pos_mux_solution_c_l251_c5_4213_iffalse),
    .iftrue(window_y_pos_mux_solution_c_l251_c5_4213_iftrue),
    .return_output(_045_)
  );
  mux_uint1_t_int9_t_int9_t_0clk_de264c78 window_y_pos_mux_solution_c_l272_c7_a3df (
    .cond(window_y_pos_mux_solution_c_l272_c7_a3df_cond),
    .iffalse(window_y_pos_mux_solution_c_l272_c7_a3df_iffalse),
    .iftrue(window_y_pos_mux_solution_c_l272_c7_a3df_iftrue),
    .return_output(_075_)
  );
  assign window = _103_;
  assign window_valid = _105_;
  assign line_width_counter = _107_;
  assign num_lines_counter = _109_;
  assign current_line_width_reg = _111_;
  assign current_num_lines_reg = _113_;
  assign input_side_in_end_of_frame = _115_;
  assign window_x_pos = _117_;
  assign window_y_pos = _119_;
  assign want_data_from_fifo = _121_;
  assign win_y_lte_num_lines = _123_;
  assign win_y_lt_num_lines = _125_;
  assign win_x_lte_width = _127_;
  assign win_y_lte_num_lines_minus_i = _129_;
  assign reg_comb_window = window_mux_solution_c_l247_c3_5f6b_return_output;
  assign reg_comb_window_valid = window_valid_mux_solution_c_l247_c3_5f6b_return_output;
  assign reg_comb_line_width_counter = line_width_counter_mux_solution_c_l247_c3_5f6b_return_output;
  assign reg_comb_num_lines_counter = num_lines_counter_mux_solution_c_l247_c3_5f6b_return_output;
  assign reg_comb_current_line_width_reg = current_line_width_mux_solution_c_l247_c3_5f6b_return_output;
  assign reg_comb_current_num_lines_reg = current_num_lines_mux_solution_c_l247_c3_5f6b_return_output;
  assign reg_comb_input_side_in_end_of_frame = input_side_in_end_of_frame_mux_solution_c_l247_c3_5f6b_return_output;
  assign reg_comb_window_x_pos = window_x_pos_mux_solution_c_l247_c3_5f6b_return_output;
  assign reg_comb_window_y_pos = window_y_pos_mux_solution_c_l247_c3_5f6b_return_output;
  assign reg_comb_want_data_from_fifo = want_data_from_fifo_mux_solution_c_l247_c3_5f6b_return_output;
  assign reg_comb_win_y_lte_num_lines = win_y_lte_num_lines_mux_solution_c_l247_c3_5f6b_return_output;
  assign reg_comb_win_y_lt_num_lines = win_y_lt_num_lines_mux_solution_c_l247_c3_5f6b_return_output;
  assign reg_comb_win_x_lte_width = win_x_lte_width_mux_solution_c_l247_c3_5f6b_return_output;
  assign reg_comb_win_y_lte_num_lines_minus_i = win_y_lte_num_lines_minus_i_mux_solution_c_l247_c3_5f6b_return_output;
  assign clk_en_internal = clock_enable;
  assign feedback_vars = { for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788_return_output[0], for_solution_c_l168_c3_5d74_iter_1_line_fifo_solution_c_l183_c28_1788_return_output[0], for_solution_c_l168_c3_5d74_iter_2_line_fifo_solution_c_l183_c28_1788_return_output[0], for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788_return_output[1], for_solution_c_l168_c3_5d74_iter_1_line_fifo_solution_c_l183_c28_1788_return_output[1], for_solution_c_l168_c3_5d74_iter_2_line_fifo_solution_c_l183_c28_1788_return_output[1], for_solution_c_l217_c3_08af_iter_0_bin_op_and_solution_c_l218_c34_f37f_return_output, for_solution_c_l217_c3_08af_iter_1_bin_op_and_solution_c_l218_c34_f37f_return_output, for_solution_c_l217_c3_08af_iter_2_bin_op_and_solution_c_l218_c34_f37f_return_output, for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788_return_output[2], for_solution_c_l168_c3_5d74_iter_1_line_fifo_solution_c_l183_c28_1788_return_output[2], for_solution_c_l168_c3_5d74_iter_2_line_fifo_solution_c_l183_c28_1788_return_output[2] };
  assign o_ready_for_data_in_mux_solution_c_l149_c3_b279_cond = input_side_in_end_of_frame;
  assign o_ready_for_data_in_mux_solution_c_l149_c3_b279_iftrue = 1'h0;
  assign o_ready_for_data_in_mux_solution_c_l149_c3_b279_iffalse = feedback_vars[2];
  assign o_ready_for_data_in_mux_solution_c_l149_c3_b279_return_output = _130_;
  assign fifo_input_valids_0_mux_solution_c_l149_c3_b279_cond = input_side_in_end_of_frame;
  assign fifo_input_valids_0_mux_solution_c_l149_c3_b279_iftrue = 1'h0;
  assign fifo_input_valids_0_mux_solution_c_l149_c3_b279_iffalse = data_valid;
  assign fifo_input_valids_0_mux_solution_c_l149_c3_b279_return_output = _131_;
  assign bin_op_and_solution_c_l153_c6_6e62_left = data_valid;
  assign bin_op_and_solution_c_l153_c6_6e62_right = o_ready_for_data_in_mux_solution_c_l149_c3_b279_return_output;
  assign bin_op_and_solution_c_l153_c6_6e62_return_output = _132_;
  assign num_lines_counter_mux_solution_c_l153_c3_2e68_cond = bin_op_and_solution_c_l153_c6_6e62_return_output;
  assign num_lines_counter_mux_solution_c_l153_c3_2e68_iftrue = num_lines_counter_mux_solution_c_l155_c5_4943_return_output;
  assign num_lines_counter_mux_solution_c_l153_c3_2e68_iffalse = num_lines_counter;
  assign num_lines_counter_mux_solution_c_l153_c3_2e68_return_output = _133_;
  assign line_width_counter_mux_solution_c_l153_c3_2e68_cond = bin_op_and_solution_c_l153_c6_6e62_return_output;
  assign line_width_counter_mux_solution_c_l153_c3_2e68_iftrue = line_width_counter_mux_solution_c_l155_c5_4943_return_output;
  assign line_width_counter_mux_solution_c_l153_c3_2e68_iffalse = line_width_counter;
  assign line_width_counter_mux_solution_c_l153_c3_2e68_return_output = _134_;
  assign input_side_in_end_of_frame_mux_solution_c_l153_c3_2e68_cond = bin_op_and_solution_c_l153_c6_6e62_return_output;
  assign input_side_in_end_of_frame_mux_solution_c_l153_c3_2e68_iftrue = input_side_in_end_of_frame_mux_solution_c_l155_c5_4943_return_output;
  assign input_side_in_end_of_frame_mux_solution_c_l153_c3_2e68_iffalse = input_side_in_end_of_frame;
  assign input_side_in_end_of_frame_mux_solution_c_l153_c3_2e68_return_output = _135_;
  assign current_line_width_mux_solution_c_l153_c3_2e68_cond = bin_op_and_solution_c_l153_c6_6e62_return_output;
  assign current_line_width_mux_solution_c_l153_c3_2e68_iftrue = current_line_width_mux_solution_c_l155_c5_4943_return_output;
  assign current_line_width_mux_solution_c_l153_c3_2e68_iffalse = current_line_width_reg;
  assign current_line_width_mux_solution_c_l153_c3_2e68_return_output = _136_;
  assign current_num_lines_mux_solution_c_l153_c3_2e68_cond = bin_op_and_solution_c_l153_c6_6e62_return_output;
  assign current_num_lines_mux_solution_c_l153_c3_2e68_iftrue = current_num_lines_mux_solution_c_l155_c5_4943_return_output;
  assign current_num_lines_mux_solution_c_l153_c3_2e68_iffalse = current_num_lines_reg;
  assign current_num_lines_mux_solution_c_l153_c3_2e68_return_output = _137_;
  assign bin_op_plus_solution_c_l154_c5_d98c_left = line_width_counter;
  assign bin_op_plus_solution_c_l154_c5_d98c_right = 2'h1;
  assign bin_op_plus_solution_c_l154_c5_d98c_return_output = _138_;
  assign num_lines_counter_mux_solution_c_l155_c5_4943_cond = grid_fragment_last;
  assign num_lines_counter_mux_solution_c_l155_c5_4943_iftrue = num_lines_counter_mux_solution_c_l159_c7_1e67_return_output;
  assign num_lines_counter_mux_solution_c_l155_c5_4943_iffalse = num_lines_counter;
  assign num_lines_counter_mux_solution_c_l155_c5_4943_return_output = _139_;
  assign line_width_counter_mux_solution_c_l155_c5_4943_cond = grid_fragment_last;
  assign line_width_counter_mux_solution_c_l155_c5_4943_iftrue = 9'h000;
  assign line_width_counter_mux_solution_c_l155_c5_4943_iffalse = bin_op_plus_solution_c_l154_c5_d98c_return_output[8:0];
  assign line_width_counter_mux_solution_c_l155_c5_4943_return_output = _140_;
  assign input_side_in_end_of_frame_mux_solution_c_l155_c5_4943_cond = grid_fragment_last;
  assign input_side_in_end_of_frame_mux_solution_c_l155_c5_4943_iftrue = input_side_in_end_of_frame_mux_solution_c_l159_c7_1e67_return_output;
  assign input_side_in_end_of_frame_mux_solution_c_l155_c5_4943_iffalse = input_side_in_end_of_frame;
  assign input_side_in_end_of_frame_mux_solution_c_l155_c5_4943_return_output = _141_;
  assign current_line_width_mux_solution_c_l155_c5_4943_cond = grid_fragment_last;
  assign current_line_width_mux_solution_c_l155_c5_4943_iftrue = bin_op_plus_solution_c_l154_c5_d98c_return_output[8:0];
  assign current_line_width_mux_solution_c_l155_c5_4943_iffalse = current_line_width_reg;
  assign current_line_width_mux_solution_c_l155_c5_4943_return_output = _142_;
  assign current_num_lines_mux_solution_c_l155_c5_4943_cond = grid_fragment_last;
  assign current_num_lines_mux_solution_c_l155_c5_4943_iftrue = current_num_lines_mux_solution_c_l159_c7_1e67_return_output;
  assign current_num_lines_mux_solution_c_l155_c5_4943_iffalse = current_num_lines_reg;
  assign current_num_lines_mux_solution_c_l155_c5_4943_return_output = _143_;
  assign bin_op_plus_solution_c_l156_c7_9c3b_left = num_lines_counter;
  assign bin_op_plus_solution_c_l156_c7_9c3b_right = 2'h1;
  assign bin_op_plus_solution_c_l156_c7_9c3b_return_output = _144_;
  assign num_lines_counter_mux_solution_c_l159_c7_1e67_cond = grid_last;
  assign num_lines_counter_mux_solution_c_l159_c7_1e67_iftrue = 9'h000;
  assign num_lines_counter_mux_solution_c_l159_c7_1e67_iffalse = bin_op_plus_solution_c_l156_c7_9c3b_return_output[8:0];
  assign num_lines_counter_mux_solution_c_l159_c7_1e67_return_output = _145_;
  assign input_side_in_end_of_frame_mux_solution_c_l159_c7_1e67_cond = grid_last;
  assign input_side_in_end_of_frame_mux_solution_c_l159_c7_1e67_iftrue = 1'h1;
  assign input_side_in_end_of_frame_mux_solution_c_l159_c7_1e67_iffalse = input_side_in_end_of_frame;
  assign input_side_in_end_of_frame_mux_solution_c_l159_c7_1e67_return_output = _146_;
  assign current_num_lines_mux_solution_c_l159_c7_1e67_cond = grid_last;
  assign current_num_lines_mux_solution_c_l159_c7_1e67_iftrue = bin_op_plus_solution_c_l156_c7_9c3b_return_output[8:0];
  assign current_num_lines_mux_solution_c_l159_c7_1e67_iffalse = current_num_lines_reg;
  assign current_num_lines_mux_solution_c_l159_c7_1e67_return_output = _147_;
  assign for_solution_c_l168_c3_5d74_iter_0_bin_op_and_solution_c_l176_c32_ca5a_left = feedback_vars[8];
  assign for_solution_c_l168_c3_5d74_iter_0_bin_op_and_solution_c_l176_c32_ca5a_right = feedback_vars[5];
  assign for_solution_c_l168_c3_5d74_iter_0_bin_op_and_solution_c_l176_c32_ca5a_return_output = _148_;
  assign for_solution_c_l168_c3_5d74_iter_0_bin_op_and_solution_c_l177_c35_66a3_left = feedback_vars[1];
  assign for_solution_c_l168_c3_5d74_iter_0_bin_op_and_solution_c_l177_c35_66a3_right = feedback_vars[5];
  assign for_solution_c_l168_c3_5d74_iter_0_bin_op_and_solution_c_l177_c35_66a3_return_output = _149_;
  assign for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788_clock_enable = clk_en_internal;
  assign for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788_ready_for_data_out = for_solution_c_l168_c3_5d74_iter_0_bin_op_and_solution_c_l177_c35_66a3_return_output;
  assign for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788_data_in = data;
  assign for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788_data_in_valid = fifo_input_valids_0_mux_solution_c_l149_c3_b279_return_output;
  assign for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788_return_output = { _152_, _151_, _150_ };
  assign for_solution_c_l168_c3_5d74_iter_1_bin_op_and_solution_c_l176_c32_ca5a_left = feedback_vars[7];
  assign for_solution_c_l168_c3_5d74_iter_1_bin_op_and_solution_c_l176_c32_ca5a_right = feedback_vars[4];
  assign for_solution_c_l168_c3_5d74_iter_1_bin_op_and_solution_c_l176_c32_ca5a_return_output = _153_;
  assign for_solution_c_l168_c3_5d74_iter_1_bin_op_and_solution_c_l177_c35_66a3_left = feedback_vars[0];
  assign for_solution_c_l168_c3_5d74_iter_1_bin_op_and_solution_c_l177_c35_66a3_right = feedback_vars[4];
  assign for_solution_c_l168_c3_5d74_iter_1_bin_op_and_solution_c_l177_c35_66a3_return_output = _154_;
  assign for_solution_c_l168_c3_5d74_iter_1_line_fifo_solution_c_l183_c28_1788_clock_enable = clk_en_internal;
  assign for_solution_c_l168_c3_5d74_iter_1_line_fifo_solution_c_l183_c28_1788_ready_for_data_out = for_solution_c_l168_c3_5d74_iter_1_bin_op_and_solution_c_l177_c35_66a3_return_output;
  assign for_solution_c_l168_c3_5d74_iter_1_line_fifo_solution_c_l183_c28_1788_data_in = feedback_vars[11];
  assign for_solution_c_l168_c3_5d74_iter_1_line_fifo_solution_c_l183_c28_1788_data_in_valid = for_solution_c_l168_c3_5d74_iter_0_bin_op_and_solution_c_l176_c32_ca5a_return_output;
  assign for_solution_c_l168_c3_5d74_iter_1_line_fifo_solution_c_l183_c28_1788_return_output = { _157_, _156_, _155_ };
  assign for_solution_c_l168_c3_5d74_iter_2_line_fifo_solution_c_l183_c28_1788_clock_enable = clk_en_internal;
  assign for_solution_c_l168_c3_5d74_iter_2_line_fifo_solution_c_l183_c28_1788_ready_for_data_out = feedback_vars[3];
  assign for_solution_c_l168_c3_5d74_iter_2_line_fifo_solution_c_l183_c28_1788_data_in = feedback_vars[10];
  assign for_solution_c_l168_c3_5d74_iter_2_line_fifo_solution_c_l183_c28_1788_data_in_valid = for_solution_c_l168_c3_5d74_iter_1_bin_op_and_solution_c_l176_c32_ca5a_return_output;
  assign for_solution_c_l168_c3_5d74_iter_2_line_fifo_solution_c_l183_c28_1788_return_output = { _160_, _159_, _158_ };
  assign for_solution_c_l211_c3_1068_iter_0_unary_op_not_solution_c_l212_c57_d4c8_expr = want_data_from_fifo[2];
  assign for_solution_c_l211_c3_1068_iter_0_unary_op_not_solution_c_l212_c57_d4c8_return_output = _161_;
  assign for_solution_c_l211_c3_1068_iter_0_bin_op_or_solution_c_l212_c32_6eba_left = for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788_return_output[1];
  assign for_solution_c_l211_c3_1068_iter_0_bin_op_or_solution_c_l212_c32_6eba_right = for_solution_c_l211_c3_1068_iter_0_unary_op_not_solution_c_l212_c57_d4c8_return_output;
  assign for_solution_c_l211_c3_1068_iter_0_bin_op_or_solution_c_l212_c32_6eba_return_output = _162_;
  assign for_solution_c_l211_c3_1068_iter_1_unary_op_not_solution_c_l212_c57_d4c8_expr = want_data_from_fifo[1];
  assign for_solution_c_l211_c3_1068_iter_1_unary_op_not_solution_c_l212_c57_d4c8_return_output = _163_;
  assign for_solution_c_l211_c3_1068_iter_1_bin_op_or_solution_c_l212_c32_6eba_left = for_solution_c_l168_c3_5d74_iter_1_line_fifo_solution_c_l183_c28_1788_return_output[1];
  assign for_solution_c_l211_c3_1068_iter_1_bin_op_or_solution_c_l212_c32_6eba_right = for_solution_c_l211_c3_1068_iter_1_unary_op_not_solution_c_l212_c57_d4c8_return_output;
  assign for_solution_c_l211_c3_1068_iter_1_bin_op_or_solution_c_l212_c32_6eba_return_output = _164_;
  assign for_solution_c_l211_c3_1068_iter_2_unary_op_not_solution_c_l212_c57_d4c8_expr = want_data_from_fifo[0];
  assign for_solution_c_l211_c3_1068_iter_2_unary_op_not_solution_c_l212_c57_d4c8_return_output = _165_;
  assign for_solution_c_l211_c3_1068_iter_2_bin_op_or_solution_c_l212_c32_6eba_left = for_solution_c_l168_c3_5d74_iter_2_line_fifo_solution_c_l183_c28_1788_return_output[1];
  assign for_solution_c_l211_c3_1068_iter_2_bin_op_or_solution_c_l212_c32_6eba_right = for_solution_c_l211_c3_1068_iter_2_unary_op_not_solution_c_l212_c57_d4c8_return_output;
  assign for_solution_c_l211_c3_1068_iter_2_bin_op_or_solution_c_l212_c32_6eba_return_output = _166_;
  assign uint1_array_and4_solution_c_l214_c28_4b75_x = { for_solution_c_l211_c3_1068_iter_0_bin_op_or_solution_c_l212_c32_6eba_return_output, for_solution_c_l211_c3_1068_iter_1_bin_op_or_solution_c_l212_c32_6eba_return_output, for_solution_c_l211_c3_1068_iter_2_bin_op_or_solution_c_l212_c32_6eba_return_output, win_y_lte_num_lines };
  assign uint1_array_and4_solution_c_l214_c28_4b75_return_output = _167_;
  assign for_solution_c_l217_c3_08af_iter_0_bin_op_and_solution_c_l218_c34_f37f_left = want_data_from_fifo[2];
  assign for_solution_c_l217_c3_08af_iter_0_bin_op_and_solution_c_l218_c34_f37f_right = uint1_array_and4_solution_c_l214_c28_4b75_return_output;
  assign for_solution_c_l217_c3_08af_iter_0_bin_op_and_solution_c_l218_c34_f37f_return_output = _000_;
  assign for_solution_c_l217_c3_08af_iter_1_bin_op_and_solution_c_l218_c34_f37f_left = want_data_from_fifo[1];
  assign for_solution_c_l217_c3_08af_iter_1_bin_op_and_solution_c_l218_c34_f37f_right = uint1_array_and4_solution_c_l214_c28_4b75_return_output;
  assign for_solution_c_l217_c3_08af_iter_1_bin_op_and_solution_c_l218_c34_f37f_return_output = _001_;
  assign for_solution_c_l217_c3_08af_iter_2_bin_op_and_solution_c_l218_c34_f37f_left = want_data_from_fifo[0];
  assign for_solution_c_l217_c3_08af_iter_2_bin_op_and_solution_c_l218_c34_f37f_right = uint1_array_and4_solution_c_l214_c28_4b75_return_output;
  assign for_solution_c_l217_c3_08af_iter_2_bin_op_and_solution_c_l218_c34_f37f_return_output = _002_;
  assign for_solution_c_l224_c3_8683_iter_0_bin_op_and_solution_c_l227_c8_a2d7_left = for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788_return_output[1];
  assign for_solution_c_l224_c3_8683_iter_0_bin_op_and_solution_c_l227_c8_a2d7_right = for_solution_c_l168_c3_5d74_iter_0_bin_op_and_solution_c_l177_c35_66a3_return_output;
  assign for_solution_c_l224_c3_8683_iter_0_bin_op_and_solution_c_l227_c8_a2d7_return_output = _003_;
  assign for_solution_c_l224_c3_8683_iter_0_next_input_col_2_mux_solution_c_l227_c5_d5e1_cond = for_solution_c_l224_c3_8683_iter_0_bin_op_and_solution_c_l227_c8_a2d7_return_output;
  assign for_solution_c_l224_c3_8683_iter_0_next_input_col_2_mux_solution_c_l227_c5_d5e1_iftrue = for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788_return_output[0];
  assign for_solution_c_l224_c3_8683_iter_0_next_input_col_2_mux_solution_c_l227_c5_d5e1_iffalse = 1'h0;
  assign for_solution_c_l224_c3_8683_iter_0_next_input_col_2_mux_solution_c_l227_c5_d5e1_return_output = _004_;
  assign for_solution_c_l224_c3_8683_iter_1_bin_op_and_solution_c_l227_c8_a2d7_left = for_solution_c_l168_c3_5d74_iter_1_line_fifo_solution_c_l183_c28_1788_return_output[1];
  assign for_solution_c_l224_c3_8683_iter_1_bin_op_and_solution_c_l227_c8_a2d7_right = for_solution_c_l168_c3_5d74_iter_1_bin_op_and_solution_c_l177_c35_66a3_return_output;
  assign for_solution_c_l224_c3_8683_iter_1_bin_op_and_solution_c_l227_c8_a2d7_return_output = _005_;
  assign for_solution_c_l224_c3_8683_iter_1_next_input_col_1_mux_solution_c_l227_c5_d5e1_cond = for_solution_c_l224_c3_8683_iter_1_bin_op_and_solution_c_l227_c8_a2d7_return_output;
  assign for_solution_c_l224_c3_8683_iter_1_next_input_col_1_mux_solution_c_l227_c5_d5e1_iftrue = for_solution_c_l168_c3_5d74_iter_1_line_fifo_solution_c_l183_c28_1788_return_output[0];
  assign for_solution_c_l224_c3_8683_iter_1_next_input_col_1_mux_solution_c_l227_c5_d5e1_iffalse = 1'h0;
  assign for_solution_c_l224_c3_8683_iter_1_next_input_col_1_mux_solution_c_l227_c5_d5e1_return_output = _006_;
  assign for_solution_c_l224_c3_8683_iter_2_bin_op_and_solution_c_l227_c8_a2d7_left = for_solution_c_l168_c3_5d74_iter_2_line_fifo_solution_c_l183_c28_1788_return_output[1];
  assign for_solution_c_l224_c3_8683_iter_2_bin_op_and_solution_c_l227_c8_a2d7_right = feedback_vars[3];
  assign for_solution_c_l224_c3_8683_iter_2_bin_op_and_solution_c_l227_c8_a2d7_return_output = _007_;
  assign for_solution_c_l224_c3_8683_iter_2_next_input_col_0_mux_solution_c_l227_c5_d5e1_cond = for_solution_c_l224_c3_8683_iter_2_bin_op_and_solution_c_l227_c8_a2d7_return_output;
  assign for_solution_c_l224_c3_8683_iter_2_next_input_col_0_mux_solution_c_l227_c5_d5e1_iftrue = for_solution_c_l168_c3_5d74_iter_2_line_fifo_solution_c_l183_c28_1788_return_output[0];
  assign for_solution_c_l224_c3_8683_iter_2_next_input_col_0_mux_solution_c_l227_c5_d5e1_iffalse = 1'h0;
  assign for_solution_c_l224_c3_8683_iter_2_next_input_col_0_mux_solution_c_l227_c5_d5e1_return_output = _008_;
  assign for_solution_c_l233_c3_2dcf_iter_0_bin_op_gte_solution_c_l235_c8_ce82_left = window_y_pos;
  assign for_solution_c_l233_c3_2dcf_iter_0_bin_op_gte_solution_c_l235_c8_ce82_right = 2'h3;
  assign for_solution_c_l233_c3_2dcf_iter_0_bin_op_gte_solution_c_l235_c8_ce82_return_output = _009_;
  assign for_solution_c_l233_c3_2dcf_iter_0_bin_op_minus_solution_c_l237_c9_090e_left = current_num_lines_reg;
  assign for_solution_c_l233_c3_2dcf_iter_0_bin_op_minus_solution_c_l237_c9_090e_right = 3'h2;
  assign for_solution_c_l233_c3_2dcf_iter_0_bin_op_minus_solution_c_l237_c9_090e_return_output = _010_;
  assign for_solution_c_l233_c3_2dcf_iter_0_bin_op_lte_solution_c_l236_c8_f1b1_left = window_y_pos;
  assign for_solution_c_l233_c3_2dcf_iter_0_bin_op_lte_solution_c_l236_c8_f1b1_right = for_solution_c_l233_c3_2dcf_iter_0_bin_op_minus_solution_c_l237_c9_090e_return_output;
  assign for_solution_c_l233_c3_2dcf_iter_0_bin_op_lte_solution_c_l236_c8_f1b1_return_output = _011_;
  assign for_solution_c_l233_c3_2dcf_iter_0_bin_op_and_solution_c_l235_c8_ab2a_left = for_solution_c_l233_c3_2dcf_iter_0_bin_op_gte_solution_c_l235_c8_ce82_return_output;
  assign for_solution_c_l233_c3_2dcf_iter_0_bin_op_and_solution_c_l235_c8_ab2a_right = for_solution_c_l233_c3_2dcf_iter_0_bin_op_lte_solution_c_l236_c8_f1b1_return_output;
  assign for_solution_c_l233_c3_2dcf_iter_0_bin_op_and_solution_c_l235_c8_ab2a_return_output = _012_;
  assign for_solution_c_l233_c3_2dcf_iter_0_bin_op_and_solution_c_l235_c8_37e4_left = for_solution_c_l233_c3_2dcf_iter_0_bin_op_and_solution_c_l235_c8_ab2a_return_output;
  assign for_solution_c_l233_c3_2dcf_iter_0_bin_op_and_solution_c_l235_c8_37e4_right = bin_op_lt_int9_t_int10_t_solution_c_l239_duplicate_354c_return_output;
  assign for_solution_c_l233_c3_2dcf_iter_0_bin_op_and_solution_c_l235_c8_37e4_return_output = _013_;
  assign for_solution_c_l233_c3_2dcf_iter_1_bin_op_gte_solution_c_l235_c8_ce82_left = window_y_pos;
  assign for_solution_c_l233_c3_2dcf_iter_1_bin_op_gte_solution_c_l235_c8_ce82_right = 2'h0;
  assign for_solution_c_l233_c3_2dcf_iter_1_bin_op_gte_solution_c_l235_c8_ce82_return_output = _014_;
  assign for_solution_c_l233_c3_2dcf_iter_1_bin_op_minus_solution_c_l237_c9_090e_left = current_num_lines_reg;
  assign for_solution_c_l233_c3_2dcf_iter_1_bin_op_minus_solution_c_l237_c9_090e_right = 2'h1;
  assign for_solution_c_l233_c3_2dcf_iter_1_bin_op_minus_solution_c_l237_c9_090e_return_output = _015_;
  assign for_solution_c_l233_c3_2dcf_iter_1_bin_op_lte_solution_c_l236_c8_f1b1_left = window_y_pos;
  assign for_solution_c_l233_c3_2dcf_iter_1_bin_op_lte_solution_c_l236_c8_f1b1_right = for_solution_c_l233_c3_2dcf_iter_1_bin_op_minus_solution_c_l237_c9_090e_return_output;
  assign for_solution_c_l233_c3_2dcf_iter_1_bin_op_lte_solution_c_l236_c8_f1b1_return_output = _016_;
  assign for_solution_c_l233_c3_2dcf_iter_1_bin_op_and_solution_c_l235_c8_ab2a_left = for_solution_c_l233_c3_2dcf_iter_1_bin_op_gte_solution_c_l235_c8_ce82_return_output;
  assign for_solution_c_l233_c3_2dcf_iter_1_bin_op_and_solution_c_l235_c8_ab2a_right = for_solution_c_l233_c3_2dcf_iter_1_bin_op_lte_solution_c_l236_c8_f1b1_return_output;
  assign for_solution_c_l233_c3_2dcf_iter_1_bin_op_and_solution_c_l235_c8_ab2a_return_output = _017_;
  assign for_solution_c_l233_c3_2dcf_iter_1_bin_op_and_solution_c_l235_c8_37e4_left = for_solution_c_l233_c3_2dcf_iter_1_bin_op_and_solution_c_l235_c8_ab2a_return_output;
  assign for_solution_c_l233_c3_2dcf_iter_1_bin_op_and_solution_c_l235_c8_37e4_right = bin_op_lt_int9_t_int10_t_solution_c_l239_duplicate_354c_return_output;
  assign for_solution_c_l233_c3_2dcf_iter_1_bin_op_and_solution_c_l235_c8_37e4_return_output = _018_;
  assign for_solution_c_l233_c3_2dcf_iter_2_bin_op_gte_solution_c_l235_c8_ce82_left = window_y_pos;
  assign for_solution_c_l233_c3_2dcf_iter_2_bin_op_gte_solution_c_l235_c8_ce82_right = 2'h1;
  assign for_solution_c_l233_c3_2dcf_iter_2_bin_op_gte_solution_c_l235_c8_ce82_return_output = _019_;
  assign for_solution_c_l233_c3_2dcf_iter_2_bin_op_minus_solution_c_l237_c9_090e_left = current_num_lines_reg;
  assign for_solution_c_l233_c3_2dcf_iter_2_bin_op_minus_solution_c_l237_c9_090e_right = 2'h0;
  assign for_solution_c_l233_c3_2dcf_iter_2_bin_op_minus_solution_c_l237_c9_090e_return_output = _020_;
  assign for_solution_c_l233_c3_2dcf_iter_2_bin_op_lte_solution_c_l236_c8_f1b1_left = window_y_pos;
  assign for_solution_c_l233_c3_2dcf_iter_2_bin_op_lte_solution_c_l236_c8_f1b1_right = for_solution_c_l233_c3_2dcf_iter_2_bin_op_minus_solution_c_l237_c9_090e_return_output;
  assign for_solution_c_l233_c3_2dcf_iter_2_bin_op_lte_solution_c_l236_c8_f1b1_return_output = _021_;
  assign for_solution_c_l233_c3_2dcf_iter_2_bin_op_and_solution_c_l235_c8_ab2a_left = for_solution_c_l233_c3_2dcf_iter_2_bin_op_gte_solution_c_l235_c8_ce82_return_output;
  assign for_solution_c_l233_c3_2dcf_iter_2_bin_op_and_solution_c_l235_c8_ab2a_right = for_solution_c_l233_c3_2dcf_iter_2_bin_op_lte_solution_c_l236_c8_f1b1_return_output;
  assign for_solution_c_l233_c3_2dcf_iter_2_bin_op_and_solution_c_l235_c8_ab2a_return_output = _022_;
  assign for_solution_c_l233_c3_2dcf_iter_2_bin_op_and_solution_c_l235_c8_37e4_left = for_solution_c_l233_c3_2dcf_iter_2_bin_op_and_solution_c_l235_c8_ab2a_return_output;
  assign for_solution_c_l233_c3_2dcf_iter_2_bin_op_and_solution_c_l235_c8_37e4_right = bin_op_lt_int9_t_int10_t_solution_c_l239_duplicate_354c_return_output;
  assign for_solution_c_l233_c3_2dcf_iter_2_bin_op_and_solution_c_l235_c8_37e4_return_output = _023_;
  assign bin_op_lte_solution_c_l241_c25_ea4f_left = window_y_pos;
  assign bin_op_lte_solution_c_l241_c25_ea4f_right = current_num_lines_reg;
  assign bin_op_lte_solution_c_l241_c25_ea4f_return_output = _024_;
  assign num_lines_counter_mux_solution_c_l247_c3_5f6b_cond = uint1_array_and4_solution_c_l214_c28_4b75_return_output;
  assign num_lines_counter_mux_solution_c_l247_c3_5f6b_iftrue = num_lines_counter_mux_solution_c_l251_c5_4213_return_output;
  assign num_lines_counter_mux_solution_c_l247_c3_5f6b_iffalse = num_lines_counter_mux_solution_c_l153_c3_2e68_return_output;
  assign num_lines_counter_mux_solution_c_l247_c3_5f6b_return_output = _025_;
  assign line_width_counter_mux_solution_c_l247_c3_5f6b_cond = uint1_array_and4_solution_c_l214_c28_4b75_return_output;
  assign line_width_counter_mux_solution_c_l247_c3_5f6b_iftrue = line_width_counter_mux_solution_c_l251_c5_4213_return_output;
  assign line_width_counter_mux_solution_c_l247_c3_5f6b_iffalse = line_width_counter_mux_solution_c_l153_c3_2e68_return_output;
  assign line_width_counter_mux_solution_c_l247_c3_5f6b_return_output = _026_;
  assign window_valid_mux_solution_c_l247_c3_5f6b_cond = uint1_array_and4_solution_c_l214_c28_4b75_return_output;
  assign window_valid_mux_solution_c_l247_c3_5f6b_iftrue = window_valid_mux_solution_c_l251_c5_4213_return_output;
  assign window_valid_mux_solution_c_l247_c3_5f6b_iffalse = 1'h0;
  assign window_valid_mux_solution_c_l247_c3_5f6b_return_output = _027_;
  assign window_mux_solution_c_l247_c3_5f6b_cond = uint1_array_and4_solution_c_l214_c28_4b75_return_output;
  assign window_mux_solution_c_l247_c3_5f6b_iftrue = window_mux_solution_c_l251_c5_4213_return_output;
  assign window_mux_solution_c_l247_c3_5f6b_iffalse = window;
  assign window_mux_solution_c_l247_c3_5f6b_return_output = _028_;
  assign input_side_in_end_of_frame_mux_solution_c_l247_c3_5f6b_cond = uint1_array_and4_solution_c_l214_c28_4b75_return_output;
  assign input_side_in_end_of_frame_mux_solution_c_l247_c3_5f6b_iftrue = input_side_in_end_of_frame_mux_solution_c_l251_c5_4213_return_output;
  assign input_side_in_end_of_frame_mux_solution_c_l247_c3_5f6b_iffalse = input_side_in_end_of_frame_mux_solution_c_l153_c3_2e68_return_output;
  assign input_side_in_end_of_frame_mux_solution_c_l247_c3_5f6b_return_output = _029_;
  assign window_y_pos_mux_solution_c_l247_c3_5f6b_cond = uint1_array_and4_solution_c_l214_c28_4b75_return_output;
  assign window_y_pos_mux_solution_c_l247_c3_5f6b_iftrue = window_y_pos_mux_solution_c_l251_c5_4213_return_output;
  assign window_y_pos_mux_solution_c_l247_c3_5f6b_iffalse = window_y_pos;
  assign window_y_pos_mux_solution_c_l247_c3_5f6b_return_output = _030_;
  assign current_line_width_mux_solution_c_l247_c3_5f6b_cond = uint1_array_and4_solution_c_l214_c28_4b75_return_output;
  assign current_line_width_mux_solution_c_l247_c3_5f6b_iftrue = current_line_width_mux_solution_c_l251_c5_4213_return_output;
  assign current_line_width_mux_solution_c_l247_c3_5f6b_iffalse = current_line_width_mux_solution_c_l153_c3_2e68_return_output;
  assign current_line_width_mux_solution_c_l247_c3_5f6b_return_output = _031_;
  assign want_data_from_fifo_mux_solution_c_l247_c3_5f6b_cond = uint1_array_and4_solution_c_l214_c28_4b75_return_output;
  assign want_data_from_fifo_mux_solution_c_l247_c3_5f6b_iftrue = want_data_from_fifo_mux_solution_c_l251_c5_4213_return_output;
  assign want_data_from_fifo_mux_solution_c_l247_c3_5f6b_iffalse = { for_solution_c_l233_c3_2dcf_iter_0_bin_op_and_solution_c_l235_c8_37e4_return_output, for_solution_c_l233_c3_2dcf_iter_1_bin_op_and_solution_c_l235_c8_37e4_return_output, for_solution_c_l233_c3_2dcf_iter_2_bin_op_and_solution_c_l235_c8_37e4_return_output };
  assign want_data_from_fifo_mux_solution_c_l247_c3_5f6b_return_output = _032_;
  assign current_num_lines_mux_solution_c_l247_c3_5f6b_cond = uint1_array_and4_solution_c_l214_c28_4b75_return_output;
  assign current_num_lines_mux_solution_c_l247_c3_5f6b_iftrue = current_num_lines_mux_solution_c_l251_c5_4213_return_output;
  assign current_num_lines_mux_solution_c_l247_c3_5f6b_iffalse = current_num_lines_mux_solution_c_l153_c3_2e68_return_output;
  assign current_num_lines_mux_solution_c_l247_c3_5f6b_return_output = _033_;
  assign win_y_lte_num_lines_minus_i_mux_solution_c_l247_c3_5f6b_cond = uint1_array_and4_solution_c_l214_c28_4b75_return_output;
  assign win_y_lte_num_lines_minus_i_mux_solution_c_l247_c3_5f6b_iftrue = win_y_lte_num_lines_minus_i_mux_solution_c_l251_c5_4213_return_output;
  assign win_y_lte_num_lines_minus_i_mux_solution_c_l247_c3_5f6b_iffalse = win_y_lte_num_lines_minus_i;
  assign win_y_lte_num_lines_minus_i_mux_solution_c_l247_c3_5f6b_return_output = _034_;
  assign window_x_pos_mux_solution_c_l247_c3_5f6b_cond = uint1_array_and4_solution_c_l214_c28_4b75_return_output;
  assign window_x_pos_mux_solution_c_l247_c3_5f6b_iftrue = window_x_pos_mux_solution_c_l251_c5_4213_return_output;
  assign window_x_pos_mux_solution_c_l247_c3_5f6b_iffalse = window_x_pos;
  assign window_x_pos_mux_solution_c_l247_c3_5f6b_return_output = _035_;
  assign done_frame_pulse_mux_solution_c_l247_c3_5f6b_cond = uint1_array_and4_solution_c_l214_c28_4b75_return_output;
  assign done_frame_pulse_mux_solution_c_l247_c3_5f6b_iftrue = done_frame_pulse_mux_solution_c_l251_c5_4213_return_output;
  assign done_frame_pulse_mux_solution_c_l247_c3_5f6b_iffalse = 1'h0;
  assign done_frame_pulse_mux_solution_c_l247_c3_5f6b_return_output = _036_;
  assign win_y_lte_num_lines_mux_solution_c_l247_c3_5f6b_cond = uint1_array_and4_solution_c_l214_c28_4b75_return_output;
  assign win_y_lte_num_lines_mux_solution_c_l247_c3_5f6b_iftrue = win_y_lte_num_lines_mux_solution_c_l251_c5_4213_return_output;
  assign win_y_lte_num_lines_mux_solution_c_l247_c3_5f6b_iffalse = bin_op_lte_solution_c_l241_c25_ea4f_return_output;
  assign win_y_lte_num_lines_mux_solution_c_l247_c3_5f6b_return_output = _037_;
  assign win_x_lte_width_mux_solution_c_l247_c3_5f6b_cond = uint1_array_and4_solution_c_l214_c28_4b75_return_output;
  assign win_x_lte_width_mux_solution_c_l247_c3_5f6b_iftrue = win_x_lte_width_mux_solution_c_l251_c5_4213_return_output;
  assign win_x_lte_width_mux_solution_c_l247_c3_5f6b_iffalse = win_x_lte_width;
  assign win_x_lte_width_mux_solution_c_l247_c3_5f6b_return_output = _038_;
  assign win_y_lt_num_lines_mux_solution_c_l247_c3_5f6b_cond = uint1_array_and4_solution_c_l214_c28_4b75_return_output;
  assign win_y_lt_num_lines_mux_solution_c_l247_c3_5f6b_iftrue = win_y_lt_num_lines_mux_solution_c_l251_c5_4213_return_output;
  assign win_y_lt_num_lines_mux_solution_c_l247_c3_5f6b_iffalse = win_y_lt_num_lines;
  assign win_y_lt_num_lines_mux_solution_c_l247_c3_5f6b_return_output = _039_;
  assign num_lines_counter_mux_solution_c_l251_c5_4213_cond = win_x_lte_width;
  assign num_lines_counter_mux_solution_c_l251_c5_4213_iftrue = num_lines_counter_mux_solution_c_l153_c3_2e68_return_output;
  assign num_lines_counter_mux_solution_c_l251_c5_4213_iffalse = num_lines_counter_mux_solution_c_l272_c7_a3df_return_output;
  assign num_lines_counter_mux_solution_c_l251_c5_4213_return_output = _040_;
  assign line_width_counter_mux_solution_c_l251_c5_4213_cond = win_x_lte_width;
  assign line_width_counter_mux_solution_c_l251_c5_4213_iftrue = line_width_counter_mux_solution_c_l153_c3_2e68_return_output;
  assign line_width_counter_mux_solution_c_l251_c5_4213_iffalse = line_width_counter_mux_solution_c_l272_c7_a3df_return_output;
  assign line_width_counter_mux_solution_c_l251_c5_4213_return_output = _041_;
  assign window_valid_mux_solution_c_l251_c5_4213_cond = win_x_lte_width;
  assign window_valid_mux_solution_c_l251_c5_4213_iftrue = bin_op_and_solution_c_l265_c23_8238_return_output;
  assign window_valid_mux_solution_c_l251_c5_4213_iffalse = 1'h0;
  assign window_valid_mux_solution_c_l251_c5_4213_return_output = _042_;
  assign window_mux_solution_c_l251_c5_4213_cond = win_x_lte_width;
  assign window_mux_solution_c_l251_c5_4213_iftrue = slide_window_solution_c_l264_c16_6c14_return_output;
  assign window_mux_solution_c_l251_c5_4213_iffalse = 9'h000;
  assign window_mux_solution_c_l251_c5_4213_return_output = _043_;
  assign input_side_in_end_of_frame_mux_solution_c_l251_c5_4213_cond = win_x_lte_width;
  assign input_side_in_end_of_frame_mux_solution_c_l251_c5_4213_iftrue = input_side_in_end_of_frame_mux_solution_c_l153_c3_2e68_return_output;
  assign input_side_in_end_of_frame_mux_solution_c_l251_c5_4213_iffalse = input_side_in_end_of_frame_mux_solution_c_l272_c7_a3df_return_output;
  assign input_side_in_end_of_frame_mux_solution_c_l251_c5_4213_return_output = _044_;
  assign window_y_pos_mux_solution_c_l251_c5_4213_cond = win_x_lte_width;
  assign window_y_pos_mux_solution_c_l251_c5_4213_iftrue = window_y_pos;
  assign window_y_pos_mux_solution_c_l251_c5_4213_iffalse = window_y_pos_mux_solution_c_l272_c7_a3df_return_output;
  assign window_y_pos_mux_solution_c_l251_c5_4213_return_output = _045_;
  assign current_line_width_mux_solution_c_l251_c5_4213_cond = win_x_lte_width;
  assign current_line_width_mux_solution_c_l251_c5_4213_iftrue = current_line_width_mux_solution_c_l153_c3_2e68_return_output;
  assign current_line_width_mux_solution_c_l251_c5_4213_iffalse = current_line_width_mux_solution_c_l272_c7_a3df_return_output;
  assign current_line_width_mux_solution_c_l251_c5_4213_return_output = _046_;
  assign want_data_from_fifo_mux_solution_c_l251_c5_4213_cond = win_x_lte_width;
  assign want_data_from_fifo_mux_solution_c_l251_c5_4213_iftrue = { for_solution_c_l253_c7_deca_iter_0_bin_op_and_solution_c_l255_c12_bcb6_return_output, for_solution_c_l253_c7_deca_iter_1_bin_op_and_solution_c_l255_c12_bcb6_return_output, for_solution_c_l253_c7_deca_iter_2_bin_op_and_solution_c_l255_c12_bcb6_return_output };
  assign want_data_from_fifo_mux_solution_c_l251_c5_4213_iffalse = want_data_from_fifo_mux_solution_c_l272_c7_a3df_return_output;
  assign want_data_from_fifo_mux_solution_c_l251_c5_4213_return_output = _047_;
  assign current_num_lines_mux_solution_c_l251_c5_4213_cond = win_x_lte_width;
  assign current_num_lines_mux_solution_c_l251_c5_4213_iftrue = current_num_lines_mux_solution_c_l153_c3_2e68_return_output;
  assign current_num_lines_mux_solution_c_l251_c5_4213_iffalse = current_num_lines_mux_solution_c_l272_c7_a3df_return_output;
  assign current_num_lines_mux_solution_c_l251_c5_4213_return_output = _048_;
  assign win_y_lte_num_lines_minus_i_mux_solution_c_l251_c5_4213_cond = win_x_lte_width;
  assign win_y_lte_num_lines_minus_i_mux_solution_c_l251_c5_4213_iftrue = win_y_lte_num_lines_minus_i;
  assign win_y_lte_num_lines_minus_i_mux_solution_c_l251_c5_4213_iffalse = win_y_lte_num_lines_minus_i_mux_solution_c_l272_c7_a3df_return_output;
  assign win_y_lte_num_lines_minus_i_mux_solution_c_l251_c5_4213_return_output = _049_;
  assign window_x_pos_mux_solution_c_l251_c5_4213_cond = win_x_lte_width;
  assign window_x_pos_mux_solution_c_l251_c5_4213_iftrue = bin_op_plus_solution_c_l262_c7_516d_return_output[8:0];
  assign window_x_pos_mux_solution_c_l251_c5_4213_iffalse = 9'h1fe;
  assign window_x_pos_mux_solution_c_l251_c5_4213_return_output = _050_;
  assign done_frame_pulse_mux_solution_c_l251_c5_4213_cond = win_x_lte_width;
  assign done_frame_pulse_mux_solution_c_l251_c5_4213_iftrue = 1'h0;
  assign done_frame_pulse_mux_solution_c_l251_c5_4213_iffalse = done_frame_pulse_mux_solution_c_l272_c7_a3df_return_output;
  assign done_frame_pulse_mux_solution_c_l251_c5_4213_return_output = _051_;
  assign win_y_lte_num_lines_mux_solution_c_l251_c5_4213_cond = win_x_lte_width;
  assign win_y_lte_num_lines_mux_solution_c_l251_c5_4213_iftrue = bin_op_lte_solution_c_l241_c25_ea4f_return_output;
  assign win_y_lte_num_lines_mux_solution_c_l251_c5_4213_iffalse = win_y_lte_num_lines_mux_solution_c_l272_c7_a3df_return_output;
  assign win_y_lte_num_lines_mux_solution_c_l251_c5_4213_return_output = _052_;
  assign win_x_lte_width_mux_solution_c_l251_c5_4213_cond = win_x_lte_width;
  assign win_x_lte_width_mux_solution_c_l251_c5_4213_iftrue = bin_op_lt_solution_c_l263_c25_b7b8_return_output;
  assign win_x_lte_width_mux_solution_c_l251_c5_4213_iffalse = 1'h1;
  assign win_x_lte_width_mux_solution_c_l251_c5_4213_return_output = _053_;
  assign win_y_lt_num_lines_mux_solution_c_l251_c5_4213_cond = win_x_lte_width;
  assign win_y_lt_num_lines_mux_solution_c_l251_c5_4213_iftrue = win_y_lt_num_lines;
  assign win_y_lt_num_lines_mux_solution_c_l251_c5_4213_iffalse = win_y_lt_num_lines_mux_solution_c_l272_c7_a3df_return_output;
  assign win_y_lt_num_lines_mux_solution_c_l251_c5_4213_return_output = _054_;
  assign for_solution_c_l253_c7_deca_iter_0_bin_op_gte_solution_c_l255_c12_d6e8_left = window_y_pos;
  assign for_solution_c_l253_c7_deca_iter_0_bin_op_gte_solution_c_l255_c12_d6e8_right = 2'h3;
  assign for_solution_c_l253_c7_deca_iter_0_bin_op_gte_solution_c_l255_c12_d6e8_return_output = _055_;
  assign for_solution_c_l253_c7_deca_iter_0_bin_op_and_solution_c_l255_c12_12e3_left = for_solution_c_l253_c7_deca_iter_0_bin_op_gte_solution_c_l255_c12_d6e8_return_output;
  assign for_solution_c_l253_c7_deca_iter_0_bin_op_and_solution_c_l255_c12_12e3_right = win_y_lte_num_lines_minus_i[2];
  assign for_solution_c_l253_c7_deca_iter_0_bin_op_and_solution_c_l255_c12_12e3_return_output = _056_;
  assign for_solution_c_l253_c7_deca_iter_0_bin_op_and_solution_c_l255_c12_bcb6_left = for_solution_c_l253_c7_deca_iter_0_bin_op_and_solution_c_l255_c12_12e3_return_output;
  assign for_solution_c_l253_c7_deca_iter_0_bin_op_and_solution_c_l255_c12_bcb6_right = bin_op_lt_int9_t_int10_t_solution_c_l260_c12_9f27_duplicate_df5d_return_output;
  assign for_solution_c_l253_c7_deca_iter_0_bin_op_and_solution_c_l255_c12_bcb6_return_output = _057_;
  assign for_solution_c_l253_c7_deca_iter_1_bin_op_gte_solution_c_l255_c12_d6e8_left = window_y_pos;
  assign for_solution_c_l253_c7_deca_iter_1_bin_op_gte_solution_c_l255_c12_d6e8_right = 2'h0;
  assign for_solution_c_l253_c7_deca_iter_1_bin_op_gte_solution_c_l255_c12_d6e8_return_output = _058_;
  assign for_solution_c_l253_c7_deca_iter_1_bin_op_and_solution_c_l255_c12_12e3_left = for_solution_c_l253_c7_deca_iter_1_bin_op_gte_solution_c_l255_c12_d6e8_return_output;
  assign for_solution_c_l253_c7_deca_iter_1_bin_op_and_solution_c_l255_c12_12e3_right = win_y_lte_num_lines_minus_i[1];
  assign for_solution_c_l253_c7_deca_iter_1_bin_op_and_solution_c_l255_c12_12e3_return_output = _059_;
  assign for_solution_c_l253_c7_deca_iter_1_bin_op_and_solution_c_l255_c12_bcb6_left = for_solution_c_l253_c7_deca_iter_1_bin_op_and_solution_c_l255_c12_12e3_return_output;
  assign for_solution_c_l253_c7_deca_iter_1_bin_op_and_solution_c_l255_c12_bcb6_right = bin_op_lt_int9_t_int10_t_solution_c_l260_c12_9f27_duplicate_df5d_return_output;
  assign for_solution_c_l253_c7_deca_iter_1_bin_op_and_solution_c_l255_c12_bcb6_return_output = _060_;
  assign for_solution_c_l253_c7_deca_iter_2_bin_op_gte_solution_c_l255_c12_d6e8_left = window_y_pos;
  assign for_solution_c_l253_c7_deca_iter_2_bin_op_gte_solution_c_l255_c12_d6e8_right = 2'h1;
  assign for_solution_c_l253_c7_deca_iter_2_bin_op_gte_solution_c_l255_c12_d6e8_return_output = _061_;
  assign for_solution_c_l253_c7_deca_iter_2_bin_op_and_solution_c_l255_c12_12e3_left = for_solution_c_l253_c7_deca_iter_2_bin_op_gte_solution_c_l255_c12_d6e8_return_output;
  assign for_solution_c_l253_c7_deca_iter_2_bin_op_and_solution_c_l255_c12_12e3_right = win_y_lte_num_lines_minus_i[0];
  assign for_solution_c_l253_c7_deca_iter_2_bin_op_and_solution_c_l255_c12_12e3_return_output = _062_;
  assign for_solution_c_l253_c7_deca_iter_2_bin_op_and_solution_c_l255_c12_bcb6_left = for_solution_c_l253_c7_deca_iter_2_bin_op_and_solution_c_l255_c12_12e3_return_output;
  assign for_solution_c_l253_c7_deca_iter_2_bin_op_and_solution_c_l255_c12_bcb6_right = bin_op_lt_int9_t_int10_t_solution_c_l260_c12_9f27_duplicate_df5d_return_output;
  assign for_solution_c_l253_c7_deca_iter_2_bin_op_and_solution_c_l255_c12_bcb6_return_output = _063_;
  assign bin_op_plus_solution_c_l262_c7_516d_left = window_x_pos;
  assign bin_op_plus_solution_c_l262_c7_516d_right = 2'h1;
  assign bin_op_plus_solution_c_l262_c7_516d_return_output = _064_;
  assign bin_op_minus_solution_c_l263_c41_43fe_left = current_line_width_reg;
  assign bin_op_minus_solution_c_l263_c41_43fe_right = 2'h1;
  assign bin_op_minus_solution_c_l263_c41_43fe_return_output = _065_;
  assign bin_op_lt_solution_c_l263_c25_b7b8_left = bin_op_plus_solution_c_l262_c7_516d_return_output[8:0];
  assign bin_op_lt_solution_c_l263_c25_b7b8_right = bin_op_minus_solution_c_l263_c41_43fe_return_output;
  assign bin_op_lt_solution_c_l263_c25_b7b8_return_output = _066_;
  assign slide_window_solution_c_l264_c16_6c14_curr = window;
  assign slide_window_solution_c_l264_c16_6c14_next_input_col = { for_solution_c_l224_c3_8683_iter_2_next_input_col_0_mux_solution_c_l227_c5_d5e1_return_output, for_solution_c_l224_c3_8683_iter_1_next_input_col_1_mux_solution_c_l227_c5_d5e1_return_output, for_solution_c_l224_c3_8683_iter_0_next_input_col_2_mux_solution_c_l227_c5_d5e1_return_output };
  assign slide_window_solution_c_l264_c16_6c14_return_output = _067_;
  assign bin_op_gte_solution_c_l265_c23_7c1c_left = bin_op_plus_solution_c_l262_c7_516d_return_output[8:0];
  assign bin_op_gte_solution_c_l265_c23_7c1c_right = 2'h0;
  assign bin_op_gte_solution_c_l265_c23_7c1c_return_output = _068_;
  assign bin_op_gte_solution_c_l265_c45_7188_left = window_y_pos;
  assign bin_op_gte_solution_c_l265_c45_7188_right = 2'h0;
  assign bin_op_gte_solution_c_l265_c45_7188_return_output = _069_;
  assign bin_op_and_solution_c_l265_c23_a02b_left = bin_op_gte_solution_c_l265_c23_7c1c_return_output;
  assign bin_op_and_solution_c_l265_c23_a02b_right = bin_op_gte_solution_c_l265_c45_7188_return_output;
  assign bin_op_and_solution_c_l265_c23_a02b_return_output = _070_;
  assign bin_op_and_solution_c_l265_c23_8238_left = bin_op_and_solution_c_l265_c23_a02b_return_output;
  assign bin_op_and_solution_c_l265_c23_8238_right = win_y_lt_num_lines;
  assign bin_op_and_solution_c_l265_c23_8238_return_output = _071_;
  assign num_lines_counter_mux_solution_c_l272_c7_a3df_cond = win_y_lt_num_lines;
  assign num_lines_counter_mux_solution_c_l272_c7_a3df_iftrue = num_lines_counter_mux_solution_c_l153_c3_2e68_return_output;
  assign num_lines_counter_mux_solution_c_l272_c7_a3df_iffalse = 9'h000;
  assign num_lines_counter_mux_solution_c_l272_c7_a3df_return_output = _072_;
  assign line_width_counter_mux_solution_c_l272_c7_a3df_cond = win_y_lt_num_lines;
  assign line_width_counter_mux_solution_c_l272_c7_a3df_iftrue = line_width_counter_mux_solution_c_l153_c3_2e68_return_output;
  assign line_width_counter_mux_solution_c_l272_c7_a3df_iffalse = 9'h000;
  assign line_width_counter_mux_solution_c_l272_c7_a3df_return_output = _073_;
  assign input_side_in_end_of_frame_mux_solution_c_l272_c7_a3df_cond = win_y_lt_num_lines;
  assign input_side_in_end_of_frame_mux_solution_c_l272_c7_a3df_iftrue = input_side_in_end_of_frame_mux_solution_c_l153_c3_2e68_return_output;
  assign input_side_in_end_of_frame_mux_solution_c_l272_c7_a3df_iffalse = 1'h0;
  assign input_side_in_end_of_frame_mux_solution_c_l272_c7_a3df_return_output = _074_;
  assign window_y_pos_mux_solution_c_l272_c7_a3df_cond = win_y_lt_num_lines;
  assign window_y_pos_mux_solution_c_l272_c7_a3df_iftrue = bin_op_plus_solution_c_l291_c9_bc84_return_output[8:0];
  assign window_y_pos_mux_solution_c_l272_c7_a3df_iffalse = 9'h1ff;
  assign window_y_pos_mux_solution_c_l272_c7_a3df_return_output = _075_;
  assign current_line_width_mux_solution_c_l272_c7_a3df_cond = win_y_lt_num_lines;
  assign current_line_width_mux_solution_c_l272_c7_a3df_iftrue = current_line_width_mux_solution_c_l153_c3_2e68_return_output;
  assign current_line_width_mux_solution_c_l272_c7_a3df_iffalse = 9'h080;
  assign current_line_width_mux_solution_c_l272_c7_a3df_return_output = _076_;
  assign want_data_from_fifo_mux_solution_c_l272_c7_a3df_cond = win_y_lt_num_lines;
  assign want_data_from_fifo_mux_solution_c_l272_c7_a3df_iftrue = { for_solution_c_l279_c9_6774_iter_0_bin_op_and_solution_c_l281_c14_4bb1_return_output, for_solution_c_l279_c9_6774_iter_1_bin_op_and_solution_c_l281_c14_4bb1_return_output, for_solution_c_l279_c9_6774_iter_2_bin_op_and_solution_c_l281_c14_4bb1_return_output };
  assign want_data_from_fifo_mux_solution_c_l272_c7_a3df_iffalse = 3'h7;
  assign want_data_from_fifo_mux_solution_c_l272_c7_a3df_return_output = _077_;
  assign current_num_lines_mux_solution_c_l272_c7_a3df_cond = win_y_lt_num_lines;
  assign current_num_lines_mux_solution_c_l272_c7_a3df_iftrue = current_num_lines_mux_solution_c_l153_c3_2e68_return_output;
  assign current_num_lines_mux_solution_c_l272_c7_a3df_iffalse = 9'h080;
  assign current_num_lines_mux_solution_c_l272_c7_a3df_return_output = _078_;
  assign win_y_lte_num_lines_minus_i_mux_solution_c_l272_c7_a3df_cond = win_y_lt_num_lines;
  assign win_y_lte_num_lines_minus_i_mux_solution_c_l272_c7_a3df_iftrue = { for_solution_c_l286_c9_23c6_iter_0_bin_op_lte_solution_c_l287_c44_bc34_return_output, for_solution_c_l286_c9_23c6_iter_1_bin_op_lte_solution_c_l287_c44_bc34_return_output, for_solution_c_l286_c9_23c6_iter_2_bin_op_lte_solution_c_l287_c44_bc34_return_output };
  assign win_y_lte_num_lines_minus_i_mux_solution_c_l272_c7_a3df_iffalse = 3'h7;
  assign win_y_lte_num_lines_minus_i_mux_solution_c_l272_c7_a3df_return_output = _079_;
  assign done_frame_pulse_mux_solution_c_l272_c7_a3df_cond = win_y_lt_num_lines;
  assign done_frame_pulse_mux_solution_c_l272_c7_a3df_iftrue = 1'h0;
  assign done_frame_pulse_mux_solution_c_l272_c7_a3df_iffalse = 1'h1;
  assign done_frame_pulse_mux_solution_c_l272_c7_a3df_return_output = _080_;
  assign win_y_lte_num_lines_mux_solution_c_l272_c7_a3df_cond = win_y_lt_num_lines;
  assign win_y_lte_num_lines_mux_solution_c_l272_c7_a3df_iftrue = win_y_lt_num_lines;
  assign win_y_lte_num_lines_mux_solution_c_l272_c7_a3df_iffalse = 1'h1;
  assign win_y_lte_num_lines_mux_solution_c_l272_c7_a3df_return_output = _081_;
  assign win_y_lt_num_lines_mux_solution_c_l272_c7_a3df_cond = win_y_lt_num_lines;
  assign win_y_lt_num_lines_mux_solution_c_l272_c7_a3df_iftrue = bin_op_lt_solution_c_l293_c30_911c_return_output;
  assign win_y_lt_num_lines_mux_solution_c_l272_c7_a3df_iffalse = 1'h1;
  assign win_y_lt_num_lines_mux_solution_c_l272_c7_a3df_return_output = _082_;
  assign for_solution_c_l279_c9_6774_iter_0_bin_op_gte_solution_c_l281_c14_efaa_left = window_y_pos;
  assign for_solution_c_l279_c9_6774_iter_0_bin_op_gte_solution_c_l281_c14_efaa_right = 3'h6;
  assign for_solution_c_l279_c9_6774_iter_0_bin_op_gte_solution_c_l281_c14_efaa_return_output = _083_;
  assign for_solution_c_l279_c9_6774_iter_0_bin_op_and_solution_c_l281_c14_4bb1_left = for_solution_c_l279_c9_6774_iter_0_bin_op_gte_solution_c_l281_c14_efaa_return_output;
  assign for_solution_c_l279_c9_6774_iter_0_bin_op_and_solution_c_l281_c14_4bb1_right = win_y_lte_num_lines_minus_i[2];
  assign for_solution_c_l279_c9_6774_iter_0_bin_op_and_solution_c_l281_c14_4bb1_return_output = _084_;
  assign for_solution_c_l279_c9_6774_iter_1_bin_op_gte_solution_c_l281_c14_efaa_left = window_y_pos;
  assign for_solution_c_l279_c9_6774_iter_1_bin_op_gte_solution_c_l281_c14_efaa_right = 2'h3;
  assign for_solution_c_l279_c9_6774_iter_1_bin_op_gte_solution_c_l281_c14_efaa_return_output = _085_;
  assign for_solution_c_l279_c9_6774_iter_1_bin_op_and_solution_c_l281_c14_4bb1_left = for_solution_c_l279_c9_6774_iter_1_bin_op_gte_solution_c_l281_c14_efaa_return_output;
  assign for_solution_c_l279_c9_6774_iter_1_bin_op_and_solution_c_l281_c14_4bb1_right = win_y_lte_num_lines_minus_i[1];
  assign for_solution_c_l279_c9_6774_iter_1_bin_op_and_solution_c_l281_c14_4bb1_return_output = _086_;
  assign for_solution_c_l279_c9_6774_iter_2_bin_op_gte_solution_c_l281_c14_efaa_left = window_y_pos;
  assign for_solution_c_l279_c9_6774_iter_2_bin_op_gte_solution_c_l281_c14_efaa_right = 2'h0;
  assign for_solution_c_l279_c9_6774_iter_2_bin_op_gte_solution_c_l281_c14_efaa_return_output = _087_;
  assign for_solution_c_l279_c9_6774_iter_2_bin_op_and_solution_c_l281_c14_4bb1_left = for_solution_c_l279_c9_6774_iter_2_bin_op_gte_solution_c_l281_c14_efaa_return_output;
  assign for_solution_c_l279_c9_6774_iter_2_bin_op_and_solution_c_l281_c14_4bb1_right = win_y_lte_num_lines_minus_i[0];
  assign for_solution_c_l279_c9_6774_iter_2_bin_op_and_solution_c_l281_c14_4bb1_return_output = _088_;
  assign for_solution_c_l286_c9_23c6_iter_0_bin_op_minus_solution_c_l288_c23_7c02_left = current_num_lines_reg;
  assign for_solution_c_l286_c9_23c6_iter_0_bin_op_minus_solution_c_l288_c23_7c02_right = 3'h3;
  assign for_solution_c_l286_c9_23c6_iter_0_bin_op_minus_solution_c_l288_c23_7c02_return_output = _089_;
  assign for_solution_c_l286_c9_23c6_iter_0_bin_op_lte_solution_c_l287_c44_bc34_left = window_y_pos;
  assign for_solution_c_l286_c9_23c6_iter_0_bin_op_lte_solution_c_l287_c44_bc34_right = for_solution_c_l286_c9_23c6_iter_0_bin_op_minus_solution_c_l288_c23_7c02_return_output;
  assign for_solution_c_l286_c9_23c6_iter_0_bin_op_lte_solution_c_l287_c44_bc34_return_output = _090_;
  assign for_solution_c_l286_c9_23c6_iter_1_bin_op_minus_solution_c_l288_c23_7c02_left = current_num_lines_reg;
  assign for_solution_c_l286_c9_23c6_iter_1_bin_op_minus_solution_c_l288_c23_7c02_right = 3'h2;
  assign for_solution_c_l286_c9_23c6_iter_1_bin_op_minus_solution_c_l288_c23_7c02_return_output = _091_;
  assign for_solution_c_l286_c9_23c6_iter_1_bin_op_lte_solution_c_l287_c44_bc34_left = window_y_pos;
  assign for_solution_c_l286_c9_23c6_iter_1_bin_op_lte_solution_c_l287_c44_bc34_right = for_solution_c_l286_c9_23c6_iter_1_bin_op_minus_solution_c_l288_c23_7c02_return_output;
  assign for_solution_c_l286_c9_23c6_iter_1_bin_op_lte_solution_c_l287_c44_bc34_return_output = _092_;
  assign for_solution_c_l286_c9_23c6_iter_2_bin_op_minus_solution_c_l288_c23_7c02_left = current_num_lines_reg;
  assign for_solution_c_l286_c9_23c6_iter_2_bin_op_minus_solution_c_l288_c23_7c02_right = 2'h1;
  assign for_solution_c_l286_c9_23c6_iter_2_bin_op_minus_solution_c_l288_c23_7c02_return_output = _093_;
  assign for_solution_c_l286_c9_23c6_iter_2_bin_op_lte_solution_c_l287_c44_bc34_left = window_y_pos;
  assign for_solution_c_l286_c9_23c6_iter_2_bin_op_lte_solution_c_l287_c44_bc34_right = for_solution_c_l286_c9_23c6_iter_2_bin_op_minus_solution_c_l288_c23_7c02_return_output;
  assign for_solution_c_l286_c9_23c6_iter_2_bin_op_lte_solution_c_l287_c44_bc34_return_output = _094_;
  assign bin_op_plus_solution_c_l291_c9_bc84_left = window_y_pos;
  assign bin_op_plus_solution_c_l291_c9_bc84_right = 2'h1;
  assign bin_op_plus_solution_c_l291_c9_bc84_return_output = _095_;
  assign bin_op_lt_solution_c_l293_c30_911c_left = bin_op_plus_solution_c_l291_c9_bc84_return_output[8:0];
  assign bin_op_lt_solution_c_l293_c30_911c_right = current_num_lines_reg;
  assign bin_op_lt_solution_c_l293_c30_911c_return_output = _096_;
  assign bin_op_minus_int9_t_int3_t_solution_c_l239_duplicate_9331_left = current_line_width_reg;
  assign bin_op_minus_int9_t_int3_t_solution_c_l239_duplicate_9331_right = 3'h2;
  assign bin_op_minus_int9_t_int3_t_solution_c_l239_duplicate_9331_return_output = _097_;
  assign bin_op_lt_int9_t_int10_t_solution_c_l239_duplicate_354c_left = window_x_pos;
  assign bin_op_lt_int9_t_int10_t_solution_c_l239_duplicate_354c_right = bin_op_minus_int9_t_int3_t_solution_c_l239_duplicate_9331_return_output;
  assign bin_op_lt_int9_t_int10_t_solution_c_l239_duplicate_354c_return_output = _098_;
  assign bin_op_minus_int9_t_int3_t_solution_c_l260_c28_029e_duplicate_9a64_left = current_line_width_reg;
  assign bin_op_minus_int9_t_int3_t_solution_c_l260_c28_029e_duplicate_9a64_right = 3'h3;
  assign bin_op_minus_int9_t_int3_t_solution_c_l260_c28_029e_duplicate_9a64_return_output = _099_;
  assign bin_op_lt_int9_t_int10_t_solution_c_l260_c12_9f27_duplicate_df5d_left = window_x_pos;
  assign bin_op_lt_int9_t_int10_t_solution_c_l260_c12_9f27_duplicate_df5d_right = bin_op_minus_int9_t_int3_t_solution_c_l260_c28_029e_duplicate_9a64_return_output;
  assign bin_op_lt_int9_t_int10_t_solution_c_l260_c12_9f27_duplicate_df5d_return_output = _100_;
  assign \module_to_global[done_frame_pulse]  = _101_;
  assign \return_output[window]  = window;
  assign \return_output[window_x_pos]  = window_x_pos;
  assign \return_output[window_y_pos]  = window_y_pos;
  assign \return_output[window_valid]  = window_valid;
  assign \return_output[ready_for_data_in]  = o_ready_for_data_in_mux_solution_c_l149_c3_b279_return_output;
endmodule

module sliding_window_process_0clk_81b7b836(clk, clock_enable, \global_to_module[input] , \module_to_global[input_ready] , \module_to_global[center_bunker_vulnerable_pipeline_in] , \module_to_global[center_bunker_vulnerable_pipeline_in_valid] , \module_to_global[sliding_window_solution_c_l352_c25_cd81] );
  wire _0_;
  wire [8:0] _1_;
  wire [8:0] _2_;
  wire [8:0] _3_;
  wire _4_;
  wire _5_;
  wire _6_;
  wire [8:0] _7_;
  wire _8_;
  input clk;
  wire clk;
  wire clk_en_internal;
  input clock_enable;
  wire clock_enable;
  input [3:0] \global_to_module[input] ;
  wire [3:0] \global_to_module[input] ;
  output [8:0] \module_to_global[center_bunker_vulnerable_pipeline_in] ;
  wire [8:0] \module_to_global[center_bunker_vulnerable_pipeline_in] ;
  output \module_to_global[center_bunker_vulnerable_pipeline_in_valid] ;
  wire \module_to_global[center_bunker_vulnerable_pipeline_in_valid] ;
  output \module_to_global[input_ready] ;
  wire \module_to_global[input_ready] ;
  output \module_to_global[sliding_window_solution_c_l352_c25_cd81] ;
  wire \module_to_global[sliding_window_solution_c_l352_c25_cd81] ;
  wire sliding_window_solution_c_l352_c25_cd81_clock_enable;
  wire sliding_window_solution_c_l352_c25_cd81_data;
  wire sliding_window_solution_c_l352_c25_cd81_data_valid;
  wire sliding_window_solution_c_l352_c25_cd81_grid_fragment_last;
  wire sliding_window_solution_c_l352_c25_cd81_grid_last;
  wire [28:0] sliding_window_solution_c_l352_c25_cd81_return_output;
  assign _6_ = clk_en_internal ? sliding_window_solution_c_l352_c25_cd81_return_output[28] : 1'h0;
  assign _7_ = clk_en_internal ? sliding_window_solution_c_l352_c25_cd81_return_output[8:0] : 9'h000;
  assign _8_ = clk_en_internal ? sliding_window_solution_c_l352_c25_cd81_return_output[27] : 1'h0;
  sliding_window_0clk_f144350a sliding_window_solution_c_l352_c25_cd81 (
    .clk(clk),
    .clock_enable(sliding_window_solution_c_l352_c25_cd81_clock_enable),
    .data(sliding_window_solution_c_l352_c25_cd81_data),
    .data_valid(sliding_window_solution_c_l352_c25_cd81_data_valid),
    .grid_fragment_last(sliding_window_solution_c_l352_c25_cd81_grid_fragment_last),
    .grid_last(sliding_window_solution_c_l352_c25_cd81_grid_last),
    .\module_to_global[done_frame_pulse] (_0_),
    .\return_output[ready_for_data_in] (_5_),
    .\return_output[window] (_1_),
    .\return_output[window_valid] (_4_),
    .\return_output[window_x_pos] (_2_),
    .\return_output[window_y_pos] (_3_)
  );
  assign clk_en_internal = clock_enable;
  assign sliding_window_solution_c_l352_c25_cd81_clock_enable = clk_en_internal;
  assign sliding_window_solution_c_l352_c25_cd81_data = \global_to_module[input] [0];
  assign sliding_window_solution_c_l352_c25_cd81_grid_fragment_last = \global_to_module[input] [1];
  assign sliding_window_solution_c_l352_c25_cd81_grid_last = \global_to_module[input] [2];
  assign sliding_window_solution_c_l352_c25_cd81_data_valid = \global_to_module[input] [3];
  assign sliding_window_solution_c_l352_c25_cd81_return_output = { _5_, _4_, _3_, _2_, _1_ };
  assign \module_to_global[input_ready]  = _6_;
  assign \module_to_global[center_bunker_vulnerable_pipeline_in]  = _7_;
  assign \module_to_global[center_bunker_vulnerable_pipeline_in_valid]  = _8_;
  assign \module_to_global[sliding_window_solution_c_l352_c25_cd81]  = _0_;
endmodule

module solution(\input[data] , \input[valid] , clk, input_ready, \output[data] , \output[valid] );
  wire _0_;
  wire _1_;
  wire _2_;
  wire [8:0] _3_;
  wire _4_;
  wire _5_;
  wire [16:0] _6_;
  input clk;
  wire clk;
  (* dont_touch = "true" *)
  (* keep = "true" *)
  (* syn_keep = 1'h1 *)
  wire clk_1p0khz;
  wire [16:0] global_to_module;
  input [2:0] \input[data] ;
  wire [2:0] \input[data] ;
  input \input[valid] ;
  wire \input[valid] ;
  output input_ready;
  wire input_ready;
  wire [30:0] module_to_global;
  output [15:0] \output[data] ;
  wire [15:0] \output[data] ;
  output \output[valid] ;
  wire \output[valid] ;
  accum_pipeline_output_0clk_d58ec462 accum_pipeline_output_0clk_d58ec462 (
    .clk(clk_1p0khz),
    .clock_enable(1'h1),
    .\global_to_module[center_bunker_vulnerable_pipeline_out] (global_to_module[15]),
    .\global_to_module[center_bunker_vulnerable_pipeline_out_valid] (global_to_module[14]),
    .\global_to_module[done_frame_pulse] (global_to_module[16]),
    .\module_to_global[output] (_6_)
  );
  center_bunker_vulnerable_pipeline_0clk_16f17d08 center_bunker_vulnerable_pipeline_0clk_16f17d08 (
    .clk(clk_1p0khz),
    .clock_enable(1'h1),
    .\global_to_module[center_bunker_vulnerable_pipeline_in] (global_to_module[8:0]),
    .\global_to_module[center_bunker_vulnerable_pipeline_in_valid] (global_to_module[9]),
    .\module_to_global[center_bunker_vulnerable_pipeline_out] (_0_),
    .\module_to_global[center_bunker_vulnerable_pipeline_out_valid] (_1_)
  );
  sliding_window_process_0clk_81b7b836 sliding_window_process_0clk_81b7b836 (
    .clk(clk_1p0khz),
    .clock_enable(1'h1),
    .\global_to_module[input] (global_to_module[13:10]),
    .\module_to_global[center_bunker_vulnerable_pipeline_in] (_3_),
    .\module_to_global[center_bunker_vulnerable_pipeline_in_valid] (_4_),
    .\module_to_global[input_ready] (_2_),
    .\module_to_global[sliding_window_solution_c_l352_c25_cd81] (_5_)
  );
  assign clk_1p0khz = clk;
  assign module_to_global = { _6_, _5_, _4_, _3_, _2_, _1_, _0_ };
  assign global_to_module = { module_to_global[13], module_to_global[0], module_to_global[1], \input[valid] , \input[data] , module_to_global[12:3] };
  assign input_ready = module_to_global[2];
  assign \output[data]  = module_to_global[29:14];
  assign \output[valid]  = module_to_global[30];
endmodule

module uint1_array_and4_0clk_e595f783(x, return_output);
  wire _0_;
  wire _1_;
  wire _2_;
  wire bin_op_and_bit_math_h_l37_c24_15e8_left;
  wire bin_op_and_bit_math_h_l37_c24_15e8_return_output;
  wire bin_op_and_bit_math_h_l37_c24_15e8_right;
  wire bin_op_and_bit_math_h_l39_c24_faa9_left;
  wire bin_op_and_bit_math_h_l39_c24_faa9_return_output;
  wire bin_op_and_bit_math_h_l39_c24_faa9_right;
  wire bin_op_and_bit_math_h_l43_c24_e8be_left;
  wire bin_op_and_bit_math_h_l43_c24_e8be_return_output;
  wire bin_op_and_bit_math_h_l43_c24_e8be_right;
  output return_output;
  wire return_output;
  input [3:0] x;
  wire [3:0] x;
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 bin_op_and_bit_math_h_l37_c24_15e8 (
    .left(bin_op_and_bit_math_h_l37_c24_15e8_left),
    .return_output(_0_),
    .right(bin_op_and_bit_math_h_l37_c24_15e8_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 bin_op_and_bit_math_h_l39_c24_faa9 (
    .left(bin_op_and_bit_math_h_l39_c24_faa9_left),
    .return_output(_1_),
    .right(bin_op_and_bit_math_h_l39_c24_faa9_right)
  );
  bin_op_and_uint1_t_uint1_t_0clk_de264c78 bin_op_and_bit_math_h_l43_c24_e8be (
    .left(bin_op_and_bit_math_h_l43_c24_e8be_left),
    .return_output(_2_),
    .right(bin_op_and_bit_math_h_l43_c24_e8be_right)
  );
  assign bin_op_and_bit_math_h_l37_c24_15e8_left = x[3];
  assign bin_op_and_bit_math_h_l37_c24_15e8_right = x[2];
  assign bin_op_and_bit_math_h_l37_c24_15e8_return_output = _0_;
  assign bin_op_and_bit_math_h_l39_c24_faa9_left = x[1];
  assign bin_op_and_bit_math_h_l39_c24_faa9_right = x[0];
  assign bin_op_and_bit_math_h_l39_c24_faa9_return_output = _1_;
  assign bin_op_and_bit_math_h_l43_c24_e8be_left = bin_op_and_bit_math_h_l37_c24_15e8_return_output;
  assign bin_op_and_bit_math_h_l43_c24_e8be_right = bin_op_and_bit_math_h_l39_c24_faa9_return_output;
  assign bin_op_and_bit_math_h_l43_c24_e8be_return_output = _2_;
  assign return_output = bin_op_and_bit_math_h_l43_c24_e8be_return_output;
endmodule

module unary_op_not_uint1_t_0clk_de264c78(expr, return_output);
  wire _0_;
  wire [2:0] \:1609.read_pipe ;
  input expr;
  wire expr;
  output return_output;
  wire return_output;
  assign _0_ = ~ expr;
  assign \:1609.read_pipe  = { expr, 2'hx };
  assign return_output = _0_;
endmodule

Timing Analysis

Path 1-8.760 ns

From: inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/_119_[0]$_DFFE_PP_/Q

To: inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/_125_$_DFFE_PP_/D

Data Arrival: 8.571 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/_119_[0]$_DFFE_PP_/CLK`
2.257	sky130_fd_sc_hvl__dfxtp_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/_119_[0]$_DFFE_PP_/Q`
2.257	sky130_fd_sc_hvl__nand2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_plus_solution_c_l291_c9_bc84/$abc$6179$auto$blifparse.cc:396:parse_blif$6180/A`
2.714	sky130_fd_sc_hvl__nand2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_plus_solution_c_l291_c9_bc84/$abc$6179$auto$blifparse.cc:396:parse_blif$6180/Y`
2.714	sky130_fd_sc_hvl__o21ai_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_plus_solution_c_l291_c9_bc84/$abc$6179$auto$blifparse.cc:396:parse_blif$6185/A1`
3.080	sky130_fd_sc_hvl__o21ai_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_plus_solution_c_l291_c9_bc84/$abc$6179$auto$blifparse.cc:396:parse_blif$6185/Y`
3.080	sky130_fd_sc_hvl__a21oi_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_plus_solution_c_l291_c9_bc84/$abc$6179$auto$blifparse.cc:396:parse_blif$6190/A1`
3.367	sky130_fd_sc_hvl__a21oi_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_plus_solution_c_l291_c9_bc84/$abc$6179$auto$blifparse.cc:396:parse_blif$6190/Y`
3.367	sky130_fd_sc_hvl__xnor2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_plus_solution_c_l291_c9_bc84/$abc$6179$auto$blifparse.cc:396:parse_blif$6192/A`
3.635	sky130_fd_sc_hvl__xnor2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_plus_solution_c_l291_c9_bc84/$abc$6179$auto$blifparse.cc:396:parse_blif$6192/Y`
3.635	sky130_fd_sc_hvl__inv_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_lt_solution_c_l293_c30_911c/bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42/$abc$6126$auto$blifparse.cc:396:parse_blif$6130/A`
3.769	sky130_fd_sc_hvl__inv_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_lt_solution_c_l293_c30_911c/bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42/$abc$6126$auto$blifparse.cc:396:parse_blif$6130/Y`
3.769	sky130_fd_sc_hvl__or2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_lt_solution_c_l293_c30_911c/bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42/$abc$6126$auto$blifparse.cc:396:parse_blif$6149/A`
4.269	sky130_fd_sc_hvl__or2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_lt_solution_c_l293_c30_911c/bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42/$abc$6126$auto$blifparse.cc:396:parse_blif$6149/X`
4.269	sky130_fd_sc_hvl__nand3_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_lt_solution_c_l293_c30_911c/bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42/$abc$6126$auto$blifparse.cc:396:parse_blif$6154/C`
4.431	sky130_fd_sc_hvl__nand3_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_lt_solution_c_l293_c30_911c/bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42/$abc$6126$auto$blifparse.cc:396:parse_blif$6154/Y`
4.431	sky130_fd_sc_hvl__and3_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_lt_solution_c_l293_c30_911c/bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42/$abc$6126$auto$blifparse.cc:396:parse_blif$6156/C`
4.791	sky130_fd_sc_hvl__and3_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_lt_solution_c_l293_c30_911c/bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42/$abc$6126$auto$blifparse.cc:396:parse_blif$6156/X`
4.791	sky130_fd_sc_hvl__o21a_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_lt_solution_c_l293_c30_911c/bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42/$abc$6126$auto$blifparse.cc:396:parse_blif$6160/A2`
5.101	sky130_fd_sc_hvl__o21a_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_lt_solution_c_l293_c30_911c/bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42/$abc$6126$auto$blifparse.cc:396:parse_blif$6160/X`
5.101	sky130_fd_sc_hvl__o21a_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_lt_solution_c_l293_c30_911c/bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42/$abc$6126$auto$blifparse.cc:396:parse_blif$6164/A2`
5.375	sky130_fd_sc_hvl__o21a_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_lt_solution_c_l293_c30_911c/bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42/$abc$6126$auto$blifparse.cc:396:parse_blif$6164/X`
5.375	sky130_fd_sc_hvl__a21oi_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_lt_solution_c_l293_c30_911c/bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42/$abc$6126$auto$blifparse.cc:396:parse_blif$6167/B1`
5.540	sky130_fd_sc_hvl__a21oi_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_lt_solution_c_l293_c30_911c/bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42/$abc$6126$auto$blifparse.cc:396:parse_blif$6167/Y`
5.540	sky130_fd_sc_hvl__a21oi_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_lt_solution_c_l293_c30_911c/bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42/$abc$6126$auto$blifparse.cc:396:parse_blif$6174/A1`
5.878	sky130_fd_sc_hvl__a21oi_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_lt_solution_c_l293_c30_911c/bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42/$abc$6126$auto$blifparse.cc:396:parse_blif$6174/Y`
5.878	sky130_fd_sc_hvl__xnor2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_lt_solution_c_l293_c30_911c/bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42/$abc$6126$auto$blifparse.cc:396:parse_blif$6175/B`
6.015	sky130_fd_sc_hvl__xnor2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_lt_solution_c_l293_c30_911c/bin_op_lt_bin_op_lt_int9_t_int9_t_c_l22_c14_8e03/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_0c42/$abc$6126$auto$blifparse.cc:396:parse_blif$6175/Y`
6.015	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_lt_solution_c_l293_c30_911c/rv_mux_bin_op_lt_int9_t_int9_t_c_l20_c5_10d2/$abc$6342$auto$blifparse.cc:396:parse_blif$6343/A1`
6.522	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_lt_solution_c_l293_c30_911c/rv_mux_bin_op_lt_int9_t_int9_t_c_l20_c5_10d2/$abc$6342$auto$blifparse.cc:396:parse_blif$6343/X`
6.522	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/win_y_lt_num_lines_mux_solution_c_l272_c7_a3df/$abc$6342$auto$blifparse.cc:396:parse_blif$6343/A1`
7.028	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/win_y_lt_num_lines_mux_solution_c_l272_c7_a3df/$abc$6342$auto$blifparse.cc:396:parse_blif$6343/X`
7.028	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/win_y_lt_num_lines_mux_solution_c_l251_c5_4213/$abc$6342$auto$blifparse.cc:396:parse_blif$6343/A0`
7.538	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/win_y_lt_num_lines_mux_solution_c_l251_c5_4213/$abc$6342$auto$blifparse.cc:396:parse_blif$6343/X`
7.538	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/win_y_lt_num_lines_mux_solution_c_l247_c3_5f6b/$abc$6342$auto$blifparse.cc:396:parse_blif$6343/A1`
8.057	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/win_y_lt_num_lines_mux_solution_c_l247_c3_5f6b/$abc$6342$auto$blifparse.cc:396:parse_blif$6343/X`
8.057	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/$abc$6903$auto$blifparse.cc:396:parse_blif$6908/A1`
8.571	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/$abc$6903$auto$blifparse.cc:396:parse_blif$6908/X`
8.571	sky130_fd_sc_hvl__dfxtp_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/_125_$_DFFE_PP_/D`

Path 2-8.726 ns

From:

inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/_29_[0]$_SDFFE_PP0P_/Q

To: inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/_111_[7]$_DFFE_PP_/D

Data Arrival: 8.538 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/_29_[0]$_SDFFE_PP0P_/CLK`
1.871	sky130_fd_sc_hvl__dfxtp_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/_29_[0]$_SDFFE_PP0P_/Q`
1.871	sky130_fd_sc_hvl__inv_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/$abc$6358$auto$blifparse.cc:396:parse_blif$6372/A`
2.358	sky130_fd_sc_hvl__inv_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/$abc$6358$auto$blifparse.cc:396:parse_blif$6372/Y`
2.358	sky130_fd_sc_hvl__a22oi_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/$abc$6358$auto$blifparse.cc:396:parse_blif$6383/B1`
2.648	sky130_fd_sc_hvl__a22oi_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/$abc$6358$auto$blifparse.cc:396:parse_blif$6383/Y`
2.648	sky130_fd_sc_hvl__nand3_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/$abc$6358$auto$blifparse.cc:396:parse_blif$6385/B`
2.908	sky130_fd_sc_hvl__nand3_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/$abc$6358$auto$blifparse.cc:396:parse_blif$6385/Y`
2.908	sky130_fd_sc_hvl__nor3_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/$abc$6358$auto$blifparse.cc:396:parse_blif$6394/A`
3.273	sky130_fd_sc_hvl__nor3_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/$abc$6358$auto$blifparse.cc:396:parse_blif$6394/Y`
3.273	sky130_fd_sc_hvl__nor2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/$abc$6358$auto$blifparse.cc:396:parse_blif$6395/B`
3.360	sky130_fd_sc_hvl__nor2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/$abc$6358$auto$blifparse.cc:396:parse_blif$6395/Y`
3.360	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/o_ready_for_data_in_mux_solution_c_l149_c3_b279/$abc$6342$auto$blifparse.cc:396:parse_blif$6343/A0`
3.865	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/o_ready_for_data_in_mux_solution_c_l149_c3_b279/$abc$6342$auto$blifparse.cc:396:parse_blif$6343/X`
3.865	sky130_fd_sc_hvl__and2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_and_solution_c_l153_c6_6e62/$abc$5951$auto$blifparse.cc:396:parse_blif$5952/A`
5.475	sky130_fd_sc_hvl__and2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_and_solution_c_l153_c6_6e62/$abc$5951$auto$blifparse.cc:396:parse_blif$5952/X`
5.475	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/current_line_width_mux_solution_c_l153_c3_2e68/$abc$6311$auto$blifparse.cc:396:parse_blif$6319/S`
6.474	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/current_line_width_mux_solution_c_l153_c3_2e68/$abc$6311$auto$blifparse.cc:396:parse_blif$6319/X`
6.474	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/current_line_width_mux_solution_c_l272_c7_a3df/$abc$6311$auto$blifparse.cc:396:parse_blif$6319/A1`
6.997	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/current_line_width_mux_solution_c_l272_c7_a3df/$abc$6311$auto$blifparse.cc:396:parse_blif$6319/X`
6.997	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/current_line_width_mux_solution_c_l251_c5_4213/$abc$6311$auto$blifparse.cc:396:parse_blif$6319/A0`
7.507	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/current_line_width_mux_solution_c_l251_c5_4213/$abc$6311$auto$blifparse.cc:396:parse_blif$6319/X`
7.507	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/current_line_width_mux_solution_c_l247_c3_5f6b/$abc$6311$auto$blifparse.cc:396:parse_blif$6319/A1`
8.025	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/current_line_width_mux_solution_c_l247_c3_5f6b/$abc$6311$auto$blifparse.cc:396:parse_blif$6319/X`
8.025	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/$abc$6903$auto$blifparse.cc:396:parse_blif$6948/A1`
8.538	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/$abc$6903$auto$blifparse.cc:396:parse_blif$6948/X`
8.538	sky130_fd_sc_hvl__dfxtp_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/_111_[7]$_DFFE_PP_/D`

Path 3-8.726 ns

From:

inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/_29_[0]$_SDFFE_PP0P_/Q

To: inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/_113_[7]$_DFFE_PP_/D

Data Arrival: 8.538 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/_29_[0]$_SDFFE_PP0P_/CLK`
1.871	sky130_fd_sc_hvl__dfxtp_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/_29_[0]$_SDFFE_PP0P_/Q`
1.871	sky130_fd_sc_hvl__inv_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/$abc$6358$auto$blifparse.cc:396:parse_blif$6372/A`
2.358	sky130_fd_sc_hvl__inv_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/$abc$6358$auto$blifparse.cc:396:parse_blif$6372/Y`
2.358	sky130_fd_sc_hvl__a22oi_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/$abc$6358$auto$blifparse.cc:396:parse_blif$6383/B1`
2.648	sky130_fd_sc_hvl__a22oi_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/$abc$6358$auto$blifparse.cc:396:parse_blif$6383/Y`
2.648	sky130_fd_sc_hvl__nand3_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/$abc$6358$auto$blifparse.cc:396:parse_blif$6385/B`
2.908	sky130_fd_sc_hvl__nand3_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/$abc$6358$auto$blifparse.cc:396:parse_blif$6385/Y`
2.908	sky130_fd_sc_hvl__nor3_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/$abc$6358$auto$blifparse.cc:396:parse_blif$6394/A`
3.273	sky130_fd_sc_hvl__nor3_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/$abc$6358$auto$blifparse.cc:396:parse_blif$6394/Y`
3.273	sky130_fd_sc_hvl__nor2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/$abc$6358$auto$blifparse.cc:396:parse_blif$6395/B`
3.360	sky130_fd_sc_hvl__nor2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/for_solution_c_l168_c3_5d74_iter_0_line_fifo_solution_c_l183_c28_1788/pipelinec_fifo_fwft_inst/$abc$6358$auto$blifparse.cc:396:parse_blif$6395/Y`
3.360	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/o_ready_for_data_in_mux_solution_c_l149_c3_b279/$abc$6342$auto$blifparse.cc:396:parse_blif$6343/A0`
3.865	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/o_ready_for_data_in_mux_solution_c_l149_c3_b279/$abc$6342$auto$blifparse.cc:396:parse_blif$6343/X`
3.865	sky130_fd_sc_hvl__and2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_and_solution_c_l153_c6_6e62/$abc$5951$auto$blifparse.cc:396:parse_blif$5952/A`
5.475	sky130_fd_sc_hvl__and2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/bin_op_and_solution_c_l153_c6_6e62/$abc$5951$auto$blifparse.cc:396:parse_blif$5952/X`
5.475	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/current_num_lines_mux_solution_c_l153_c3_2e68/$abc$6311$auto$blifparse.cc:396:parse_blif$6319/S`
6.474	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/current_num_lines_mux_solution_c_l153_c3_2e68/$abc$6311$auto$blifparse.cc:396:parse_blif$6319/X`
6.474	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/current_num_lines_mux_solution_c_l272_c7_a3df/$abc$6311$auto$blifparse.cc:396:parse_blif$6319/A1`
6.997	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/current_num_lines_mux_solution_c_l272_c7_a3df/$abc$6311$auto$blifparse.cc:396:parse_blif$6319/X`
6.997	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/current_num_lines_mux_solution_c_l251_c5_4213/$abc$6311$auto$blifparse.cc:396:parse_blif$6319/A0`
7.507	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/current_num_lines_mux_solution_c_l251_c5_4213/$abc$6311$auto$blifparse.cc:396:parse_blif$6319/X`
7.507	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/current_num_lines_mux_solution_c_l247_c3_5f6b/$abc$6311$auto$blifparse.cc:396:parse_blif$6319/A1`
8.025	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/current_num_lines_mux_solution_c_l247_c3_5f6b/$abc$6311$auto$blifparse.cc:396:parse_blif$6319/X`
8.025	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/$abc$6903$auto$blifparse.cc:396:parse_blif$6939/A1`
8.538	sky130_fd_sc_hvl__mux2_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/$abc$6903$auto$blifparse.cc:396:parse_blif$6939/X`
8.538	sky130_fd_sc_hvl__dfxtp_1	`inner/sliding_window_process_0clk_81b7b836/sliding_window_solution_c_l352_c25_cd81/_113_[7]$_DFFE_PP_/D`

Post-Synthesis Verilog

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