Bunker Network - Latchup

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Submission #2

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Submitted Solution

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready, // sic
  input wire i_valid,
  input wire i_payload_grid_fragment_fragment,
  input wire i_payload_grid_fragment_last,
  input wire i_payload_grid_last,
  output wire [16-1:0] o_payload,
  output wire o_valid
);

reg [0:127] b [0:2];
reg [0:128] a [0:2];

reg [1:0] abc;
reg [1:0] df;
reg [2:0] abcdf;
reg [1:0] gi;
reg [1:0] ghi;
reg [3:0] abcdfghi;
reg [2:0] defgi;

reg sub_middle;
reg add_middle;
reg add_bottom;

reg [1:0] add;
reg [15:0] acc;
reg ready;
reg last;  
reg valid;

reg [7:0] a_cnt;
reg [7:0] b_cnt;

always@(*) begin
    // a b c | a b c | a b c | 
    // d e f | d X f | d X f | d e f
    // g h i |       | g h i | g X i
    abc = a[2][0] + a[2][1] + a[2][2];
    df = a[1][0] + a[1][2];
    abcdf = abc + df;
    gi = a[0][0] + a[0][2];
    ghi = a[0][1] + gi;
    abcdfghi = abcdf + ghi;
    defgi = df + gi + a[1][1];

    add_bottom = (a[0][1] && defgi < 4); // assume undefended unless proven otherwise
    sub_middle = (a[1][1] && abcdfghi >= 4); // this was shown to be defended
    add_middle = (a[1][1] && abcdf >= 4); // already known.

    add = add_middle + add_bottom - sub_middle;
end

wire [0:127] next_shift = {i_payload_grid_fragment_fragment, b[0][0:126]};

always@(posedge clk) begin
    // buffer.
    if (i_valid && i_payload_grid_last) begin
        // final last
        b[2] <= b[1];
        b[1] <= next_shift;
        b[0] <= 128'b0;
        b_cnt <= 0;
    end else if (i_valid && i_payload_grid_fragment_last) begin
        // line last
        b[2] <= b[1];
        b[1] <= next_shift;
        b[0] <= 128'b0;
        b_cnt <= 0;
    end else if (i_valid) begin
        // line shift
        b[0] <= next_shift;
        b_cnt <= b_cnt + 1;
    end

    // analysis
  if (i_valid && (i_payload_grid_last || i_payload_grid_fragment_last)) begin
        // final last
        a[2] <= {1'b0, b[2]};
        a[1] <= {1'b0, b[1]};
        a[0] <= {1'b0, next_shift};
        a_cnt <= b_cnt;
    end else begin
        a[2] <= {a[2][1:128], 1'b0};
        a[1] <= {a[1][1:128], 1'b0};
        a[0] <= {a[0][1:128], 1'b0};
        if (a_cnt != 8'b0) begin
            a_cnt <= a_cnt - 1;
        end
    end

    // state
    if (i_valid && i_payload_grid_last) begin
        ready <= 0;
        last <= 1;
    end else if (a_cnt == 0) begin
        ready <= 1;
      	last <= 0;
    end
    if (o_valid) begin
        acc <= 0;
    end else begin
      acc <= acc + {{14{add[1]}}, add};
    end
  
    valid <= last && (a_cnt == 0);

    // resets
    if (reset) begin
        ready <= 0;
        valid <= 0;
        acc <= 0;
        b_cnt <= 0;
        a_cnt <= 0;
        b[0] <= 128'b0;
        b[1] <= 128'b0;
        b[2] <= 128'b0;
        a[0] <= 129'b0;
        a[1] <= 129'b0;
        a[2] <= 129'b0;
        last <= 0;
    end

end

assign i_ready = ready;
assign o_payload = acc;
assign o_valid = valid;

// Define your design here

endmodule

Generated Verilog

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready, // sic
  input wire i_valid,
  input wire i_payload_grid_fragment_fragment,
  input wire i_payload_grid_fragment_last,
  input wire i_payload_grid_last,
  output wire [16-1:0] o_payload,
  output wire o_valid
);

reg [0:127] b [0:2];
reg [0:128] a [0:2];

reg [1:0] abc;
reg [1:0] df;
reg [2:0] abcdf;
reg [1:0] gi;
reg [1:0] ghi;
reg [3:0] abcdfghi;
reg [2:0] defgi;

reg sub_middle;
reg add_middle;
reg add_bottom;

reg [1:0] add;
reg [15:0] acc;
reg ready;
reg last;  
reg valid;

reg [7:0] a_cnt;
reg [7:0] b_cnt;

always@(*) begin
    // a b c | a b c | a b c | 
    // d e f | d X f | d X f | d e f
    // g h i |       | g h i | g X i
    abc = a[2][0] + a[2][1] + a[2][2];
    df = a[1][0] + a[1][2];
    abcdf = abc + df;
    gi = a[0][0] + a[0][2];
    ghi = a[0][1] + gi;
    abcdfghi = abcdf + ghi;
    defgi = df + gi + a[1][1];

    add_bottom = (a[0][1] && defgi < 4); // assume undefended unless proven otherwise
    sub_middle = (a[1][1] && abcdfghi >= 4); // this was shown to be defended
    add_middle = (a[1][1] && abcdf >= 4); // already known.

    add = add_middle + add_bottom - sub_middle;
end

wire [0:127] next_shift = {i_payload_grid_fragment_fragment, b[0][0:126]};

always@(posedge clk) begin
    // buffer.
    if (i_valid && i_payload_grid_last) begin
        // final last
        b[2] <= b[1];
        b[1] <= next_shift;
        b[0] <= 128'b0;
        b_cnt <= 0;
    end else if (i_valid && i_payload_grid_fragment_last) begin
        // line last
        b[2] <= b[1];
        b[1] <= next_shift;
        b[0] <= 128'b0;
        b_cnt <= 0;
    end else if (i_valid) begin
        // line shift
        b[0] <= next_shift;
        b_cnt <= b_cnt + 1;
    end

    // analysis
  if (i_valid && (i_payload_grid_last || i_payload_grid_fragment_last)) begin
        // final last
        a[2] <= {1'b0, b[2]};
        a[1] <= {1'b0, b[1]};
        a[0] <= {1'b0, next_shift};
        a_cnt <= b_cnt;
    end else begin
        a[2] <= {a[2][1:128], 1'b0};
        a[1] <= {a[1][1:128], 1'b0};
        a[0] <= {a[0][1:128], 1'b0};
        if (a_cnt != 8'b0) begin
            a_cnt <= a_cnt - 1;
        end
    end

    // state
    if (i_valid && i_payload_grid_last) begin
        ready <= 0;
        last <= 1;
    end else if (a_cnt == 0) begin
        ready <= 1;
      	last <= 0;
    end
    if (o_valid) begin
        acc <= 0;
    end else begin
      acc <= acc + {{14{add[1]}}, add};
    end
  
    valid <= last && (a_cnt == 0);

    // resets
    if (reset) begin
        ready <= 0;
        valid <= 0;
        acc <= 0;
        b_cnt <= 0;
        a_cnt <= 0;
        b[0] <= 128'b0;
        b[1] <= 128'b0;
        b[2] <= 128'b0;
        a[0] <= 129'b0;
        a[1] <= 129'b0;
        a[2] <= 129'b0;
        last <= 0;
    end

end

assign i_ready = ready;
assign o_payload = acc;
assign o_valid = valid;

// Define your design here

endmodule

Timing Analysis

Path 1-50.240 ns

From: i_payload_grid_last

To: b_cnt[6]$_SDFFE_PP0P_/D

Data Arrival: 50.020 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`i_payload_grid_last`
0.000	sky130_fd_sc_hvl__o21a_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5447/A1`
0.688	sky130_fd_sc_hvl__o21a_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5447/X`
0.688	sky130_fd_sc_hvl__nor2_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5487/B`
45.220	sky130_fd_sc_hvl__nor2_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5487/Y`
45.220	sky130_fd_sc_hvl__o21ai_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5507/B1`
48.800	sky130_fd_sc_hvl__o21ai_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5507/Y`
48.800	sky130_fd_sc_hvl__a21oi_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5508/B1`
50.020	sky130_fd_sc_hvl__a21oi_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5508/Y`
50.020	sky130_fd_sc_hvl__dfxtp_1	`b_cnt[6]$_SDFFE_PP0P_/D`

Path 2-50.000 ns

From: i_payload_grid_last

To: b_cnt[3]$_SDFFE_PP0P_/D

Data Arrival: 49.770 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`i_payload_grid_last`
0.000	sky130_fd_sc_hvl__o21a_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5447/A1`
0.688	sky130_fd_sc_hvl__o21a_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5447/X`
0.688	sky130_fd_sc_hvl__nor2_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5487/B`
45.220	sky130_fd_sc_hvl__nor2_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5487/Y`
45.220	sky130_fd_sc_hvl__o21ai_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5498/B1`
48.780	sky130_fd_sc_hvl__o21ai_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5498/Y`
48.780	sky130_fd_sc_hvl__nor2_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5499/B`
49.770	sky130_fd_sc_hvl__nor2_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5499/Y`
49.770	sky130_fd_sc_hvl__dfxtp_1	`b_cnt[3]$_SDFFE_PP0P_/D`

Path 3-50.000 ns

From: i_payload_grid_last

To: b_cnt[4]$_SDFFE_PP0P_/D

Data Arrival: 49.770 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`i_payload_grid_last`
0.000	sky130_fd_sc_hvl__o21a_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5447/A1`
0.688	sky130_fd_sc_hvl__o21a_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5447/X`
0.688	sky130_fd_sc_hvl__nor2_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5487/B`
45.220	sky130_fd_sc_hvl__nor2_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5487/Y`
45.220	sky130_fd_sc_hvl__o21ai_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5501/B1`
48.780	sky130_fd_sc_hvl__o21ai_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5501/Y`
48.780	sky130_fd_sc_hvl__nor2_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5502/B`
49.770	sky130_fd_sc_hvl__nor2_1	`$abc$5339$auto$blifparse.cc:396:parse_blif$5502/Y`
49.770	sky130_fd_sc_hvl__dfxtp_1	`b_cnt[4]$_SDFFE_PP0P_/D`

Post-Synthesis Verilog

Download synth.v