Drone Says It's Fine

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Submission #1

PASSED

RankingPercentile

Latency

30.80 (18 cycles)ns

1st

top 1%

Throughput (ranked)

584.45 (100.0%)MHz

1st

top 1%

Throughput (visible)

584.45 (100.0%)MHz

—

top —%

Fmax

584.45MHz

—

top —%

Area

229μm²

1st

top 1%

Score

100.00

1st

top 1%

Throughput is Fmax × the measured percentage. Rankings use hidden tests; visible tests are unranked feedback.

Submitted Solution

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready,
  input wire i_valid,
  input wire [1-1:0] i_payload_heartbeat_fragment,
  input wire i_payload_heartbeat_last,
  output wire [1-1:0] o_payload_fragment,
  output wire o_payload_last,
  output wire o_valid
);

  // just curious how fast this is compared to the other high-clock-rate solutions.
  // k-map friendly version, since I think this is intended to be done as a
  // schematic
  //
  // s[1] s[0]    i | n[1] n[0]    o
  //    0    0    0 |    0    1    0
  //    0    0    1 |    0    0    0
  //    0    1    0 |    1    0    0
  //    0    1    1 |    0    0    0
  //    1    0    0 |    1    1    1
  //    1    0    1 |    0    0    0
  //    1    1    0 |    1    1    1
  //    1    1    1 |    1    1    1
  //
  //
  // n[0] (s horizontal, i vertical)
  //   00 01 11 10
  // 0  1     1  1
  // 1        1
  //
  // n[1] (s horizontal, i vertical)
  //   00 01 11 10
  // 0     1  1  1
  // 1        1
  //
  // o (s horizontal, i vertiacal)
  //   00 01 11 10
  // 0        1  1
  // 1        1
  //
  logic [1:0] s = 2'b00;
  wire i = i_payload_heartbeat_fragment;
  wire c = (!i && s[1]) || (s[1] && s[0]); // common to all three
  wire [1:0] n = {(c || (s[0] && !i)),
                   (c || (!s[0] && !i))};
                  
  always_ff@(posedge clk) begin
    if (i_valid) begin
      s <= n;
    end

    if (reset || (i_valid && i_payload_heartbeat_last)) begin
      s <= 2'b00;
    end
  end
                   
  assign i_ready = 1'b1;
  assign o_payload_fragment = c;
  assign o_payload_last = i_payload_heartbeat_last;
  assign o_valid = i_valid;

endmodule

Generated Verilog

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready,
  input wire i_valid,
  input wire [1-1:0] i_payload_heartbeat_fragment,
  input wire i_payload_heartbeat_last,
  output wire [1-1:0] o_payload_fragment,
  output wire o_payload_last,
  output wire o_valid
);

  // just curious how fast this is compared to the other high-clock-rate solutions.
  // k-map friendly version, since I think this is intended to be done as a
  // schematic
  //
  // s[1] s[0]    i | n[1] n[0]    o
  //    0    0    0 |    0    1    0
  //    0    0    1 |    0    0    0
  //    0    1    0 |    1    0    0
  //    0    1    1 |    0    0    0
  //    1    0    0 |    1    1    1
  //    1    0    1 |    0    0    0
  //    1    1    0 |    1    1    1
  //    1    1    1 |    1    1    1
  //
  //
  // n[0] (s horizontal, i vertical)
  //   00 01 11 10
  // 0  1     1  1
  // 1        1
  //
  // n[1] (s horizontal, i vertical)
  //   00 01 11 10
  // 0     1  1  1
  // 1        1
  //
  // o (s horizontal, i vertiacal)
  //   00 01 11 10
  // 0        1  1
  // 1        1
  //
  logic [1:0] s = 2'b00;
  wire i = i_payload_heartbeat_fragment;
  wire c = (!i && s[1]) || (s[1] && s[0]); // common to all three
  wire [1:0] n = {(c || (s[0] && !i)),
                   (c || (!s[0] && !i))};
                  
  always_ff@(posedge clk) begin
    if (i_valid) begin
      s <= n;
    end

    if (reset || (i_valid && i_payload_heartbeat_last)) begin
      s <= 2'b00;
    end
  end
                   
  assign i_ready = 1'b1;
  assign o_payload_fragment = c;
  assign o_payload_last = i_payload_heartbeat_last;
  assign o_valid = i_valid;

endmodule

Timing Analysis

Path 1-1.707 ns

From: s[0]$_SDFFE_PP0P_/Q

To: s[0]$_SDFFE_PP0P_/D

Data Arrival: 1.563 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`s[0]$_SDFFE_PP0P_/CLK`
0.706	sky130_fd_sc_hvl__dfxtp_1	`s[0]$_SDFFE_PP0P_/Q`
0.706	sky130_fd_sc_hvl__or3_1	`$abc$130$auto$blifparse.cc:396:parse_blif$135/B`
1.384	sky130_fd_sc_hvl__or3_1	`$abc$130$auto$blifparse.cc:396:parse_blif$135/X`
1.384	sky130_fd_sc_hvl__a21oi_1	`$abc$130$auto$blifparse.cc:396:parse_blif$136/A2`
1.563	sky130_fd_sc_hvl__a21oi_1	`$abc$130$auto$blifparse.cc:396:parse_blif$136/Y`
1.563	sky130_fd_sc_hvl__dfxtp_1	`s[0]$_SDFFE_PP0P_/D`

Path 2-1.508 ns

From: s[0]$_SDFFE_PP0P_/Q

To: s[1]$_SDFFE_PP0P_/D

Data Arrival: 1.320 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`s[0]$_SDFFE_PP0P_/CLK`
0.706	sky130_fd_sc_hvl__dfxtp_1	`s[0]$_SDFFE_PP0P_/Q`
0.706	sky130_fd_sc_hvl__o21a_1	`$abc$130$auto$blifparse.cc:396:parse_blif$137/A1`
1.016	sky130_fd_sc_hvl__o21a_1	`$abc$130$auto$blifparse.cc:396:parse_blif$137/X`
1.016	sky130_fd_sc_hvl__a21oi_1	`$abc$130$auto$blifparse.cc:396:parse_blif$139/B1`
1.176	sky130_fd_sc_hvl__a21oi_1	`$abc$130$auto$blifparse.cc:396:parse_blif$139/Y`
1.176	sky130_fd_sc_hvl__a21oi_1	`$abc$130$auto$blifparse.cc:396:parse_blif$140/A2`
1.320	sky130_fd_sc_hvl__a21oi_1	`$abc$130$auto$blifparse.cc:396:parse_blif$140/Y`
1.320	sky130_fd_sc_hvl__dfxtp_1	`s[1]$_SDFFE_PP0P_/D`

Path 3-1.015 ns

From: s[0]$_SDFFE_PP0P_/Q

To: o_payload_fragment[0]

Data Arrival: 1.016 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`s[0]$_SDFFE_PP0P_/CLK`
0.706	sky130_fd_sc_hvl__dfxtp_1	`s[0]$_SDFFE_PP0P_/Q`
0.706	sky130_fd_sc_hvl__o21a_1	`$abc$130$auto$blifparse.cc:396:parse_blif$137/A1`
1.016	sky130_fd_sc_hvl__o21a_1	`$abc$130$auto$blifparse.cc:396:parse_blif$137/X`
1.016	Solution	`o_payload_fragment[0]`

Post-Synthesis Verilog

Download synth.v