The Reactor Is Not Our Product

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Submission #1

PASSED

RankingPercentile

Latency

72.64 (44 cycles)ns

2nd

top 100%

Throughput (ranked)

605.69 (100.0%)MHz

2nd

top 100%

Throughput (visible)

605.69 (100.0%)MHz

—

top —%

Fmax

605.69MHz

—

top —%

Area

225μm²

2nd

top 100%

Score

97.80

2nd

top 100%

Throughput is Fmax × the measured percentage. Rankings use hidden tests; visible tests are unranked feedback.

Submitted Solution

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready,
  input wire i_valid,
  input wire [2-1:0] i_payload_temperature_fragment,
  input wire i_payload_temperature_last,
  output wire [1-1:0] o_payload_fragment_1,
  output wire [1-1:0] o_payload_fragment_2,
  output wire o_payload_last,
  output wire o_valid
);

// this looks like a k-map homework problem.  the thing
// to notice is that it's effective two independent FSMs.
// from there, each FSM has two states.  so just a register per
// FSM.  I call these "non-FSM FSMs" since I'm not going to use
// a switch-case.
// 
// fsm 1:
// let t = i_payload_temperature_fragment
// let s = "state" (0 = cooler off, 1 = cooler on)
// let o = next(s), eg, output 0 when moving/staying in cooler off.
//
//        | 00(cold) | 01(normal) | 11(critical) | 10(warm)
// -------+----------+------------+--------------+----------
// 0(off) |   0      |   0        |   1   A      |  1   A
// -------+----------+------------+--------------+----------
// 1(on)  |   0      |   1  B     |   1   A B    |  1   A
// -------+----------+------------+--------------+----------
//
//                A          B
// o = next(s) = t[1] || (s && t[0])
//
// fsm 2:
// let t = i_payload_temperature_fragment
// let s = "state" (0 = alarm off, 1 = alarm on)
// let o = next(s), eg, output 0 when moving/staying in alarm off.
//
//        | 00(cold) | 01(normal) | 11(critical) | 10(warm)
// -------+----------+------------+--------------+----------
// 0(off) |   0      |   0        |   1   B      |  0    
// -------+----------+------------+--------------+----------
// 1(on)  |   1 A    |   1 A      |   1 A B      |  1 A  
// -------+----------+------------+--------------+----------
//
// o = next(s) = s || (t[0] && t[1])
//
// note that normally you wouldn't write code like this or
// manually do k-maps.  this just really seemed like a k-map
// homework problem.

// (input name is very long...)
logic cooler;
logic alarm;
  
wire [1:0] temperature = i_payload_temperature_fragment;
wire next_cooler = temperature[1] || (cooler && temperature[0]);
wire next_alarm = alarm || &temperature;
  
always@(posedge clk) begin
  if (i_valid) begin
    if (i_payload_temperature_last) begin
      cooler <= 1'b0;
      alarm <= 1'b0;
    end else begin
      cooler <= next_cooler;
      alarm <= next_alarm;
    end
  end

  if (reset) begin
    cooler <= 1'b0;
    alarm <= 1'b0;
  end 
end

assign i_ready = 1'b1;
assign o_payload_fragment_1 = next_cooler;
assign o_payload_fragment_2 = next_alarm;
assign o_payload_last = i_payload_temperature_last;
assign o_valid = i_valid;
  
endmodule

Generated Verilog

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready,
  input wire i_valid,
  input wire [2-1:0] i_payload_temperature_fragment,
  input wire i_payload_temperature_last,
  output wire [1-1:0] o_payload_fragment_1,
  output wire [1-1:0] o_payload_fragment_2,
  output wire o_payload_last,
  output wire o_valid
);

// this looks like a k-map homework problem.  the thing
// to notice is that it's effective two independent FSMs.
// from there, each FSM has two states.  so just a register per
// FSM.  I call these "non-FSM FSMs" since I'm not going to use
// a switch-case.
// 
// fsm 1:
// let t = i_payload_temperature_fragment
// let s = "state" (0 = cooler off, 1 = cooler on)
// let o = next(s), eg, output 0 when moving/staying in cooler off.
//
//        | 00(cold) | 01(normal) | 11(critical) | 10(warm)
// -------+----------+------------+--------------+----------
// 0(off) |   0      |   0        |   1   A      |  1   A
// -------+----------+------------+--------------+----------
// 1(on)  |   0      |   1  B     |   1   A B    |  1   A
// -------+----------+------------+--------------+----------
//
//                A          B
// o = next(s) = t[1] || (s && t[0])
//
// fsm 2:
// let t = i_payload_temperature_fragment
// let s = "state" (0 = alarm off, 1 = alarm on)
// let o = next(s), eg, output 0 when moving/staying in alarm off.
//
//        | 00(cold) | 01(normal) | 11(critical) | 10(warm)
// -------+----------+------------+--------------+----------
// 0(off) |   0      |   0        |   1   B      |  0    
// -------+----------+------------+--------------+----------
// 1(on)  |   1 A    |   1 A      |   1 A B      |  1 A  
// -------+----------+------------+--------------+----------
//
// o = next(s) = s || (t[0] && t[1])
//
// note that normally you wouldn't write code like this or
// manually do k-maps.  this just really seemed like a k-map
// homework problem.

// (input name is very long...)
logic cooler;
logic alarm;
  
wire [1:0] temperature = i_payload_temperature_fragment;
wire next_cooler = temperature[1] || (cooler && temperature[0]);
wire next_alarm = alarm || &temperature;
  
always@(posedge clk) begin
  if (i_valid) begin
    if (i_payload_temperature_last) begin
      cooler <= 1'b0;
      alarm <= 1'b0;
    end else begin
      cooler <= next_cooler;
      alarm <= next_alarm;
    end
  end

  if (reset) begin
    cooler <= 1'b0;
    alarm <= 1'b0;
  end 
end

assign i_ready = 1'b1;
assign o_payload_fragment_1 = next_cooler;
assign o_payload_fragment_2 = next_alarm;
assign o_payload_last = i_payload_temperature_last;
assign o_valid = i_valid;
  
endmodule

Timing Analysis

Path 1-1.647 ns

From: alarm$_SDFFE_PP0P_/Q

To: alarm$_SDFFE_PP0P_/D

Data Arrival: 1.473 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`alarm$_SDFFE_PP0P_/CLK`
0.634	sky130_fd_sc_hvl__dfxtp_1	`alarm$_SDFFE_PP0P_/Q`
0.634	sky130_fd_sc_hvl__mux2_1	`$abc$128$auto$blifparse.cc:396:parse_blif$137/A0`
1.138	sky130_fd_sc_hvl__mux2_1	`$abc$128$auto$blifparse.cc:396:parse_blif$137/X`
1.138	sky130_fd_sc_hvl__and3_1	`$abc$128$auto$blifparse.cc:396:parse_blif$138/C`
1.473	sky130_fd_sc_hvl__and3_1	`$abc$128$auto$blifparse.cc:396:parse_blif$138/X`
1.473	sky130_fd_sc_hvl__dfxtp_1	`alarm$_SDFFE_PP0P_/D`

Path 2-1.343 ns

From: cooler$_SDFFE_PP0P_/Q

To: cooler$_SDFFE_PP0P_/D

Data Arrival: 1.157 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`cooler$_SDFFE_PP0P_/CLK`
0.648	sky130_fd_sc_hvl__dfxtp_1	`cooler$_SDFFE_PP0P_/Q`
0.648	sky130_fd_sc_hvl__a21o_1	`$abc$128$auto$blifparse.cc:396:parse_blif$133/A1`
0.912	sky130_fd_sc_hvl__a21o_1	`$abc$128$auto$blifparse.cc:396:parse_blif$133/X`
0.912	sky130_fd_sc_hvl__nand3_1	`$abc$128$auto$blifparse.cc:396:parse_blif$134/C`
1.023	sky130_fd_sc_hvl__nand3_1	`$abc$128$auto$blifparse.cc:396:parse_blif$134/Y`
1.023	sky130_fd_sc_hvl__a21oi_1	`$abc$128$auto$blifparse.cc:396:parse_blif$135/A2`
1.157	sky130_fd_sc_hvl__a21oi_1	`$abc$128$auto$blifparse.cc:396:parse_blif$135/Y`
1.157	sky130_fd_sc_hvl__dfxtp_1	`cooler$_SDFFE_PP0P_/D`

Path 3-0.911 ns

From: cooler$_SDFFE_PP0P_/Q

To: o_payload_fragment_1[0]

Data Arrival: 0.912 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`cooler$_SDFFE_PP0P_/CLK`
0.648	sky130_fd_sc_hvl__dfxtp_1	`cooler$_SDFFE_PP0P_/Q`
0.648	sky130_fd_sc_hvl__a21o_1	`$abc$128$auto$blifparse.cc:396:parse_blif$133/A1`
0.912	sky130_fd_sc_hvl__a21o_1	`$abc$128$auto$blifparse.cc:396:parse_blif$133/X`
0.912	Solution	`o_payload_fragment_1[0]`

Post-Synthesis Verilog

Download synth.v