Latchup
Problems
Community
SpinalHDL Docs
VHDL Tutorial
Verilog Tutorial
Login
SpinalHDL
VHDL
Verilog
Reset from template
//class Io extends Bundle { // val i = slave Stream(new Bundle { // val r = UInt(32 bits) // val c = UInt(32 bits) // val h = Fragment(UInt(32 bits)) // }) // val o = master Flow(UInt(32 bits)) //} import spinal.core._ import spinal.lib._ case class Solution() extends Component { val io = new Io() // Your code here }
View past submissions
Leaderboard
Submit
Back to problem
Submissions