SpinalHDL
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Leaderboard
| # | User | Language | Latency▼ ns | Throughput MHz | Area μm² | Score | |
|---|---|---|---|---|---|---|---|
| 1 | agus-fshr | Amaranth | 7.51 (1 cycles) | 133.14 (100.0%) | 34051 | 89.93 | |
| 2 | d4pr0 | Verilog | 7.51 (1 cycles) | 133.14 (100.0%) | 34051 | 89.93 | |
| 3 | keshav verma | Verilog | 7.51 (1 cycles) | 133.14 (100.0%) | 34051 | 89.93 | |
| 4 | santhosh k | Verilog | 7.51 (1 cycles) | 133.14 (100.0%) | 34051 | 89.93 | |
| 5 | swasthikm | Verilog | 7.51 (1 cycles) | 133.14 (100.0%) | 34051 | 89.93 | |
| 6 | Jones Mao | Verilog | 7.51 (1 cycles) | 133.14 (100.0%) | 34051 | 89.93 | |
| 7 | nuttapat tamprasert | Chisel | 7.51 (1 cycles) | 133.14 (100.0%) | 34051 | 89.93 | |
| 8 | guilhermegog | Verilog | 7.51 (1 cycles) | 133.14 (100.0%) | 34051 | 89.93 | |
| 9 | iN1PE | Verilog | 7.51 (1 cycles) | 133.14 (100.0%) | 34051 | 89.93 | |
| 10 | aej | VHDL | 7.51 (1 cycles) | 133.14 (100.0%) | 34051 | 89.93 |
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