Multiplier - Latchup

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Leaderboard

#	User	Language	Latency▼ ns	Throughput MHz	Area μm²	Score
1	Justin Eng	Verilog	10.02 (1 cycles)	—	39955	56.67
2	widlarizer	Verilog	10.53 (1 cycles)	—	21423	59.43
3	Allen Appukuttan	Verilog	10.97 (1 cycles)	—	20333	59.48
4	Eric Santigosa Lepe	Verilog	11.14 (1 cycles)	—	20315	59.41
5	O	VHDL	11.27 (1 cycles)	—	22021	58.97
6	axytho	Verilog	11.37 (1 cycles)	—	21822	58.97
7	utkudotdev	Spade	11.44 (1 cycles)	87.40 (100.0%)	20241	90.44
8	mcstonedzor stoned	Verilog	11.44 (1 cycles)	87.40 (100.0%)	20241	90.44
9	TuxCoder	Spade	11.44 (1 cycles)	87.40 (100.0%)	20241	90.44
10	jmi2k	Spade	11.44 (1 cycles)	—	20241	59.30

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