Division - Latchup

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Leaderboard

#	User	Language	Latency▼ ns	Throughput MHz	Area μm²	Score
1	LVK-96	Verilog	69.68 (18 cycles)	14.35 (5.6%)	1100	99.03
2	j-nac	Verilog	88.81 (8 cycles)	12.87 (14.3%)	21050	83.14
3	iracigt	HardCaml	95.42 (7 cycles)	14.67 (20.0%)	13386	85.60
4	nbstrong	VHDL	114.73 (8 cycles)	—	12464	52.59
5	vishu	Verilog	150.16 (1 cycles)	6.66 (100.0%)	372305	63.63
6	L-Sherry	Amaranth	167.05 (9 cycles)	—	17493	49.16
7	Bhavin Bhavani	Verilog	213.36 (1 cycles)	4.69 (100.0%)	49834	69.92
8	shantanu-spec	Verilog	213.36 (1 cycles)	—	49834	42.95
9	Eric Santigosa Lepe	Verilog	213.36 (1 cycles)	—	49834	42.95
10	O	VHDL	213.36 (1 cycles)	—	49834	42.95

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