SpinalHDL
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Leaderboard
| # | User | Language | Latency▼ ns | Throughput MHz | Area μm² | Score | |
|---|---|---|---|---|---|---|---|
| 1 | LVK-96 | Verilog | 69.68 (18 cycles) | 14.35 (5.6%) | 1100 | 88.37 | |
| 2 | j-nac | Verilog | 88.81 (8 cycles) | 12.01 (13.3%) | 21050 | 72.16 | |
| 3 | iracigt | HardCaml | 95.42 (7 cycles) | 13.34 (18.2%) | 13386 | 74.49 | |
| 4 | nbstrong | VHDL | 114.73 (8 cycles) | 10.73 (15.4%) | 12464 | 72.90 | |
| 5 | JLNuijens | SpinalHDL | 138.33 (1 cycles) | 7.23 (100.0%) | 65963 | 62.09 | |
| 6 | Julian Kemmerer | Pypeline | 149.08 (1 cycles) | 6.71 (100.0%) | 228005 | 55.41 | |
| 7 | vishu | Verilog | 150.16 (1 cycles) | 6.66 (100.0%) | 372305 | 52.98 | |
| 8 | L-Sherry | Amaranth | 167.05 (9 cycles) | — | 17493 | 49.16 | |
| 9 | Eric Santigosa Lepe | Verilog | 213.36 (1 cycles) | 4.69 (100.0%) | 49834 | 59.27 | |
| 10 | Bhavin Bhavani | Verilog | 213.36 (1 cycles) | 4.69 (100.0%) | 49834 | 59.27 |
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