SpinalHDL
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Leaderboard
| # | User | Language | Latency▼ ns | Throughput MHz | Area μm² | Score | |
|---|---|---|---|---|---|---|---|
| 1 | SolowYolow | VHDL | 62.05 (1 cycles) | 16.12 (100.0%) | 11495 | 88.81 | |
| 2 | Vegard Eriksen | Amaranth | 89.54 (1 cycles) | — | 22138 | 58.65 | |
| 3 | JoGei | Verilog | 123.94 (1 cycles) | 8.07 (100.0%) | 26893 | 78.07 | |
| 4 | nbstrong | VHDL | 141.14 (18 cycles) | — | 7301 | 61.80 | |
| 5 | Ivan Buda Mandura | Verilog | 178.94 (18 cycles) | — | 10528 | 58.90 | |
| 6 | Steve Hoover | TL-Verilog | 183.11 (17 cycles) | — | 8494 | 59.82 | |
| 7 | Julian Kemmerer | PipelineC | 187.50 (1 cycles) | 5.33 (100.0%) | 190275 | 64.68 | |
| 8 | TheZoq2 | Spade | 202.83 (17 cycles) | 83.82 (100.0%) | 113121 | 80.05 | |
| 9 | psmears | Amaranth | 255.87 (17 cycles) | 66.44 (100.0%) | 128938 | 77.18 | |
| 10 | iracigt | HardCaml | 312.14 (18 cycles) | 3.39 (5.9%) | 22273 | 70.36 |
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