SpinalHDL
1 / 1
View past submissionsLeaderboard
Back to problem

Leaderboard

#UserLanguage
Latency
ns
Throughput
MHz
Area
μm²
Score
1Julian KemmererPypeline32.86 (2 cycles)60.86 (100.0%)257957163.85
2SolowYolowVHDL62.05 (1 cycles)16.12 (100.0%)1149580.44
3vishuVerilog69.04 (17 cycles)246.24 (100.0%)8055183.68
4Vegard EriksenAmaranth89.54 (1 cycles)2213855.60
5N1PEVerilog89.78 (17 cycles)189.36 (100.0%)6164082.44
6ciccio-87Verilog89.78 (17 cycles)189.36 (100.0%)6216982.39
7aejVHDL113.91 (1 cycles)8.78 (100.0%)10047064.17
8JoGeiVerilog123.94 (1 cycles)8.07 (100.0%)2689369.70
9nbstrongVHDL141.14 (18 cycles)730158.74
10Ivan Buda ManduraVerilog178.94 (18 cycles)1052855.84
Page 1