Square Root - Latchup

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Submission #13

PASSED

RankingPercentile

Latency

89.78 (17 cycles)ns

5th

top 17%

Throughput

189.36 (100.0%)MHz

3rd

top 9%

Area

61640μm²

19th

top 78%

Score

82.44

3rd

top 9%

Submitted Solution

// AUTO-GENERATED USING Seal-Lang 2026.7a ON 2026/08/01 - DO NOT EDIT FILE

`timescale 1ns/1ps
`default_nettype none

module Solution (
    input wire clk,
    input wire reset,
    output wire i_ready,
    input wire i_valid,
    input wire [31:0] i_payload_x,
    output reg o_valid,
    output reg [15:0] o_payload
);

reg [31:0] i_payload_x_d [1:15];
reg i_valid_d [1:15];
reg [17:0] remainder_pl [1:15];
reg [16:0] root_pl [1:15];

wire [31:0] w122;
wire [17:0] w124;
wire [16:0] w126;
wire w127;
wire [31:0] w363;
wire [16:0] w370;
wire [31:0] ur_w6 [0:13];
integer rst_i0;
integer ur_i1;
integer ur_i2;


assign w122 = ((i_payload_x >> (32'd30 - (32'd2 * 32'd0))) & 32'd3);
assign w124 = ((18'd0 << 18'd2) | w122[1:0]);
assign w126 = ((17'd0 << 17'd2) | 17'd1);
assign w127 = (w124 >= w126);
assign w363 = ((i_payload_x_d[32'd15] >> (32'd30 - (32'd2 * 32'd15))) & 32'd3);
assign w370 = ((root_pl[32'd15] << 17'd1) | ((((remainder_pl[32'd15] << 18'd2) | w363[1:0]) >= ((root_pl[32'd15] << 17'd2) | 17'd1)) ? 17'd1 : 17'd0));
assign i_ready = 32'd1;
assign ur_w6[0] = ((i_payload_x_d[32'd1] >> (32'd30 - (32'd2 * 32'd1))) & 32'd3);
assign ur_w6[1] = ((i_payload_x_d[32'd2] >> (32'd30 - (32'd2 * 32'd2))) & 32'd3);
assign ur_w6[2] = ((i_payload_x_d[32'd3] >> (32'd30 - (32'd2 * 32'd3))) & 32'd3);
assign ur_w6[3] = ((i_payload_x_d[32'd4] >> (32'd30 - (32'd2 * 32'd4))) & 32'd3);
assign ur_w6[4] = ((i_payload_x_d[32'd5] >> (32'd30 - (32'd2 * 32'd5))) & 32'd3);
assign ur_w6[5] = ((i_payload_x_d[32'd6] >> (32'd30 - (32'd2 * 32'd6))) & 32'd3);
assign ur_w6[6] = ((i_payload_x_d[32'd7] >> (32'd30 - (32'd2 * 32'd7))) & 32'd3);
assign ur_w6[7] = ((i_payload_x_d[32'd8] >> (32'd30 - (32'd2 * 32'd8))) & 32'd3);
assign ur_w6[8] = ((i_payload_x_d[32'd9] >> (32'd30 - (32'd2 * 32'd9))) & 32'd3);
assign ur_w6[9] = ((i_payload_x_d[32'd10] >> (32'd30 - (32'd2 * 32'd10))) & 32'd3);
assign ur_w6[10] = ((i_payload_x_d[32'd11] >> (32'd30 - (32'd2 * 32'd11))) & 32'd3);
assign ur_w6[11] = ((i_payload_x_d[32'd12] >> (32'd30 - (32'd2 * 32'd12))) & 32'd3);
assign ur_w6[12] = ((i_payload_x_d[32'd13] >> (32'd30 - (32'd2 * 32'd13))) & 32'd3);
assign ur_w6[13] = ((i_payload_x_d[32'd14] >> (32'd30 - (32'd2 * 32'd14))) & 32'd3);

always @(posedge clk) begin
    if (reset) begin
        o_valid <= 1'd0;
        o_payload <= 16'd0;
        for (rst_i0 = 1; rst_i0 <= 15; rst_i0 = rst_i0 + 1) begin
            i_payload_x_d[rst_i0] <= 32'd0;
            i_valid_d[rst_i0] <= 1'd0;
            remainder_pl[rst_i0] <= 18'd0;
            root_pl[rst_i0] <= 17'd0;
        end
    end else begin
        // main.seal:28  remainder = take_bit ? candidate - trial : candidate;
        remainder_pl[32'd1] <= (w127 ? (w124 - w126) : w124);
        // main.seal:29  root      = (root << 1) | (take_bit ? 1 : 0);
        root_pl[32'd1] <= ((17'd0 << 17'd1) | (w127 ? 17'd1 : 17'd0));
        for (ur_i1 = 0; ur_i1 <= 13; ur_i1 = ur_i1 + 1) begin
            remainder_pl[(2 + ur_i1)] <= ((((remainder_pl[(1 + ur_i1)] << 18'd2) | ur_w6[ur_i1][1:0]) >= ((root_pl[(1 + ur_i1)] << 17'd2) | 17'd1)) ? (((remainder_pl[(1 + ur_i1)] << 18'd2) | ur_w6[ur_i1][1:0]) - ((root_pl[(1 + ur_i1)] << 17'd2) | 17'd1)) : ((remainder_pl[(1 + ur_i1)] << 18'd2) | ur_w6[ur_i1][1:0]));
            root_pl[(2 + ur_i1)] <= ((root_pl[(1 + ur_i1)] << 17'd1) | ((((remainder_pl[(1 + ur_i1)] << 18'd2) | ur_w6[ur_i1][1:0]) >= ((root_pl[(1 + ur_i1)] << 17'd2) | 17'd1)) ? 17'd1 : 17'd0));
        end
        // main.seal:32  o_payload = (uint16_t) root;
        o_payload <= w370[15:0];
        // main.seal:33  o_valid   = i_valid;
        o_valid <= i_valid_d[32'd15];
        i_payload_x_d[32'd1] <= i_payload_x;
        i_valid_d[32'd1] <= i_valid;
        for (ur_i2 = 0; ur_i2 <= 13; ur_i2 = ur_i2 + 1) begin
            i_payload_x_d[(2 + ur_i2)] <= i_payload_x_d[(1 + ur_i2)];
            i_valid_d[(2 + ur_i2)] <= i_valid_d[(1 + ur_i2)];
        end
    end
end

endmodule

Generated Verilog

// AUTO-GENERATED USING Seal-Lang 2026.7a ON 2026/08/01 - DO NOT EDIT FILE

`timescale 1ns/1ps
`default_nettype none

module Solution (
    input wire clk,
    input wire reset,
    output wire i_ready,
    input wire i_valid,
    input wire [31:0] i_payload_x,
    output reg o_valid,
    output reg [15:0] o_payload
);

reg [31:0] i_payload_x_d [1:15];
reg i_valid_d [1:15];
reg [17:0] remainder_pl [1:15];
reg [16:0] root_pl [1:15];

wire [31:0] w122;
wire [17:0] w124;
wire [16:0] w126;
wire w127;
wire [31:0] w363;
wire [16:0] w370;
wire [31:0] ur_w6 [0:13];
integer rst_i0;
integer ur_i1;
integer ur_i2;


assign w122 = ((i_payload_x >> (32'd30 - (32'd2 * 32'd0))) & 32'd3);
assign w124 = ((18'd0 << 18'd2) | w122[1:0]);
assign w126 = ((17'd0 << 17'd2) | 17'd1);
assign w127 = (w124 >= w126);
assign w363 = ((i_payload_x_d[32'd15] >> (32'd30 - (32'd2 * 32'd15))) & 32'd3);
assign w370 = ((root_pl[32'd15] << 17'd1) | ((((remainder_pl[32'd15] << 18'd2) | w363[1:0]) >= ((root_pl[32'd15] << 17'd2) | 17'd1)) ? 17'd1 : 17'd0));
assign i_ready = 32'd1;
assign ur_w6[0] = ((i_payload_x_d[32'd1] >> (32'd30 - (32'd2 * 32'd1))) & 32'd3);
assign ur_w6[1] = ((i_payload_x_d[32'd2] >> (32'd30 - (32'd2 * 32'd2))) & 32'd3);
assign ur_w6[2] = ((i_payload_x_d[32'd3] >> (32'd30 - (32'd2 * 32'd3))) & 32'd3);
assign ur_w6[3] = ((i_payload_x_d[32'd4] >> (32'd30 - (32'd2 * 32'd4))) & 32'd3);
assign ur_w6[4] = ((i_payload_x_d[32'd5] >> (32'd30 - (32'd2 * 32'd5))) & 32'd3);
assign ur_w6[5] = ((i_payload_x_d[32'd6] >> (32'd30 - (32'd2 * 32'd6))) & 32'd3);
assign ur_w6[6] = ((i_payload_x_d[32'd7] >> (32'd30 - (32'd2 * 32'd7))) & 32'd3);
assign ur_w6[7] = ((i_payload_x_d[32'd8] >> (32'd30 - (32'd2 * 32'd8))) & 32'd3);
assign ur_w6[8] = ((i_payload_x_d[32'd9] >> (32'd30 - (32'd2 * 32'd9))) & 32'd3);
assign ur_w6[9] = ((i_payload_x_d[32'd10] >> (32'd30 - (32'd2 * 32'd10))) & 32'd3);
assign ur_w6[10] = ((i_payload_x_d[32'd11] >> (32'd30 - (32'd2 * 32'd11))) & 32'd3);
assign ur_w6[11] = ((i_payload_x_d[32'd12] >> (32'd30 - (32'd2 * 32'd12))) & 32'd3);
assign ur_w6[12] = ((i_payload_x_d[32'd13] >> (32'd30 - (32'd2 * 32'd13))) & 32'd3);
assign ur_w6[13] = ((i_payload_x_d[32'd14] >> (32'd30 - (32'd2 * 32'd14))) & 32'd3);

always @(posedge clk) begin
    if (reset) begin
        o_valid <= 1'd0;
        o_payload <= 16'd0;
        for (rst_i0 = 1; rst_i0 <= 15; rst_i0 = rst_i0 + 1) begin
            i_payload_x_d[rst_i0] <= 32'd0;
            i_valid_d[rst_i0] <= 1'd0;
            remainder_pl[rst_i0] <= 18'd0;
            root_pl[rst_i0] <= 17'd0;
        end
    end else begin
        // main.seal:28  remainder = take_bit ? candidate - trial : candidate;
        remainder_pl[32'd1] <= (w127 ? (w124 - w126) : w124);
        // main.seal:29  root      = (root << 1) | (take_bit ? 1 : 0);
        root_pl[32'd1] <= ((17'd0 << 17'd1) | (w127 ? 17'd1 : 17'd0));
        for (ur_i1 = 0; ur_i1 <= 13; ur_i1 = ur_i1 + 1) begin
            remainder_pl[(2 + ur_i1)] <= ((((remainder_pl[(1 + ur_i1)] << 18'd2) | ur_w6[ur_i1][1:0]) >= ((root_pl[(1 + ur_i1)] << 17'd2) | 17'd1)) ? (((remainder_pl[(1 + ur_i1)] << 18'd2) | ur_w6[ur_i1][1:0]) - ((root_pl[(1 + ur_i1)] << 17'd2) | 17'd1)) : ((remainder_pl[(1 + ur_i1)] << 18'd2) | ur_w6[ur_i1][1:0]));
            root_pl[(2 + ur_i1)] <= ((root_pl[(1 + ur_i1)] << 17'd1) | ((((remainder_pl[(1 + ur_i1)] << 18'd2) | ur_w6[ur_i1][1:0]) >= ((root_pl[(1 + ur_i1)] << 17'd2) | 17'd1)) ? 17'd1 : 17'd0));
        end
        // main.seal:32  o_payload = (uint16_t) root;
        o_payload <= w370[15:0];
        // main.seal:33  o_valid   = i_valid;
        o_valid <= i_valid_d[32'd15];
        i_payload_x_d[32'd1] <= i_payload_x;
        i_valid_d[32'd1] <= i_valid;
        for (ur_i2 = 0; ur_i2 <= 13; ur_i2 = ur_i2 + 1) begin
            i_payload_x_d[(2 + ur_i2)] <= i_payload_x_d[(1 + ur_i2)];
            i_valid_d[(2 + ur_i2)] <= i_valid_d[(1 + ur_i2)];
        end
    end
end

endmodule

Timing Analysis

Path 1-5.278 ns

From: remainder_pl[13][3]$_SDFF_PP0_/Q

To: remainder_pl[14][0]$_SDFF_PP0_/D

Data Arrival: 5.087 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`remainder_pl[13][3]$_SDFF_PP0_/CLK`
0.717	sky130_fd_sc_hvl__dfxtp_1	`remainder_pl[13][3]$_SDFF_PP0_/Q`
0.717	sky130_fd_sc_hvl__nand2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11458/B`
0.915	sky130_fd_sc_hvl__nand2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11458/Y`
0.915	sky130_fd_sc_hvl__inv_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11459/A`
1.057	sky130_fd_sc_hvl__inv_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11459/Y`
1.057	sky130_fd_sc_hvl__nor2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11510/B`
1.315	sky130_fd_sc_hvl__nor2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11510/Y`
1.315	sky130_fd_sc_hvl__o21ai_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11516/A2`
1.530	sky130_fd_sc_hvl__o21ai_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11516/Y`
1.530	sky130_fd_sc_hvl__a21oi_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11517/A1`
1.797	sky130_fd_sc_hvl__a21oi_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11517/Y`
1.797	sky130_fd_sc_hvl__nand2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11526/A`
2.138	sky130_fd_sc_hvl__nand2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11526/Y`
2.138	sky130_fd_sc_hvl__a21oi_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11527/A2`
2.373	sky130_fd_sc_hvl__a21oi_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11527/Y`
2.373	sky130_fd_sc_hvl__nand3_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11528/A`
2.631	sky130_fd_sc_hvl__nand3_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11528/Y`
2.631	sky130_fd_sc_hvl__nor2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11529/B`
3.799	sky130_fd_sc_hvl__nor2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11529/Y`
3.799	sky130_fd_sc_hvl__inv_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11531/A`
4.713	sky130_fd_sc_hvl__inv_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11531/Y`
4.713	sky130_fd_sc_hvl__nand2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11532/B`
4.933	sky130_fd_sc_hvl__nand2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11532/Y`
4.933	sky130_fd_sc_hvl__a21oi_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11533/A1`
5.087	sky130_fd_sc_hvl__a21oi_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11533/Y`
5.087	sky130_fd_sc_hvl__dfxtp_1	`remainder_pl[14][0]$_SDFF_PP0_/D`

Path 2-5.278 ns

From: remainder_pl[13][3]$_SDFF_PP0_/Q

To: remainder_pl[14][10]$_SDFF_PP0_/D

Data Arrival: 5.087 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`remainder_pl[13][3]$_SDFF_PP0_/CLK`
0.717	sky130_fd_sc_hvl__dfxtp_1	`remainder_pl[13][3]$_SDFF_PP0_/Q`
0.717	sky130_fd_sc_hvl__nand2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11458/B`
0.915	sky130_fd_sc_hvl__nand2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11458/Y`
0.915	sky130_fd_sc_hvl__inv_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11459/A`
1.057	sky130_fd_sc_hvl__inv_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11459/Y`
1.057	sky130_fd_sc_hvl__nor2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11510/B`
1.315	sky130_fd_sc_hvl__nor2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11510/Y`
1.315	sky130_fd_sc_hvl__o21ai_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11516/A2`
1.530	sky130_fd_sc_hvl__o21ai_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11516/Y`
1.530	sky130_fd_sc_hvl__a21oi_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11517/A1`
1.797	sky130_fd_sc_hvl__a21oi_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11517/Y`
1.797	sky130_fd_sc_hvl__nand2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11526/A`
2.138	sky130_fd_sc_hvl__nand2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11526/Y`
2.138	sky130_fd_sc_hvl__a21oi_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11527/A2`
2.373	sky130_fd_sc_hvl__a21oi_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11527/Y`
2.373	sky130_fd_sc_hvl__nand3_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11528/A`
2.631	sky130_fd_sc_hvl__nand3_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11528/Y`
2.631	sky130_fd_sc_hvl__nor2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11529/B`
3.799	sky130_fd_sc_hvl__nor2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11529/Y`
3.799	sky130_fd_sc_hvl__inv_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11531/A`
4.713	sky130_fd_sc_hvl__inv_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11531/Y`
4.713	sky130_fd_sc_hvl__nand2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11594/B`
4.933	sky130_fd_sc_hvl__nand2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11594/Y`
4.933	sky130_fd_sc_hvl__a21oi_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11595/A1`
5.087	sky130_fd_sc_hvl__a21oi_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11595/Y`
5.087	sky130_fd_sc_hvl__dfxtp_1	`remainder_pl[14][10]$_SDFF_PP0_/D`

Path 3-5.278 ns

From: remainder_pl[13][3]$_SDFF_PP0_/Q

To: remainder_pl[14][12]$_SDFF_PP0_/D

Data Arrival: 5.087 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`remainder_pl[13][3]$_SDFF_PP0_/CLK`
0.717	sky130_fd_sc_hvl__dfxtp_1	`remainder_pl[13][3]$_SDFF_PP0_/Q`
0.717	sky130_fd_sc_hvl__nand2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11458/B`
0.915	sky130_fd_sc_hvl__nand2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11458/Y`
0.915	sky130_fd_sc_hvl__inv_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11459/A`
1.057	sky130_fd_sc_hvl__inv_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11459/Y`
1.057	sky130_fd_sc_hvl__nor2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11510/B`
1.315	sky130_fd_sc_hvl__nor2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11510/Y`
1.315	sky130_fd_sc_hvl__o21ai_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11516/A2`
1.530	sky130_fd_sc_hvl__o21ai_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11516/Y`
1.530	sky130_fd_sc_hvl__a21oi_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11517/A1`
1.797	sky130_fd_sc_hvl__a21oi_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11517/Y`
1.797	sky130_fd_sc_hvl__nand2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11526/A`
2.138	sky130_fd_sc_hvl__nand2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11526/Y`
2.138	sky130_fd_sc_hvl__a21oi_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11527/A2`
2.373	sky130_fd_sc_hvl__a21oi_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11527/Y`
2.373	sky130_fd_sc_hvl__nand3_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11528/A`
2.631	sky130_fd_sc_hvl__nand3_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11528/Y`
2.631	sky130_fd_sc_hvl__nor2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11529/B`
3.799	sky130_fd_sc_hvl__nor2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11529/Y`
3.799	sky130_fd_sc_hvl__inv_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11531/A`
4.713	sky130_fd_sc_hvl__inv_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11531/Y`
4.713	sky130_fd_sc_hvl__nand2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11608/B`
4.933	sky130_fd_sc_hvl__nand2_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11608/Y`
4.933	sky130_fd_sc_hvl__a21oi_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11609/A1`
5.087	sky130_fd_sc_hvl__a21oi_1	`$abc$9045$auto$blifparse.cc:396:parse_blif$11609/Y`
5.087	sky130_fd_sc_hvl__dfxtp_1	`remainder_pl[14][12]$_SDFF_PP0_/D`

Post-Synthesis Verilog

Download synth.v