Median Filter - Latchup

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Submitted Solution

// PipelineC solution template.
#include "uintN_t.h"
#include "intN_t.h"
#include "stream/stream.h"

// Input stream interface:
//   input.valid (input): Asserted when input data is valid
//   input.data.* (input): Input payload fields
//   input_ready (output): Assert when ready to accept input
//
// Output flow interface (no backpressure):
//   output.valid (output): Assert when output data is valid
//   output.data.* (output): Output payload fields

typedef struct input_payload_t {
  uint8_t stream_fragment;
  uint1_t stream_last;
} input_payload_t;
DECL_STREAM_TYPE(input_payload_t)

typedef struct output_payload_t {
  uint8_t fragment;
  uint1_t last;
} output_payload_t;
DECL_STREAM_TYPE(output_payload_t)

DECL_INPUT(stream(input_payload_t), input)
DECL_OUTPUT(uint1_t, input_ready)

DECL_OUTPUT(stream(output_payload_t), output)
  
// See https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Latchup-Solutions

#define CLK_RATE_MHZ 335 // ~ 9 stage median pipeline given current timing models
DECL_INPUT(uint1_t, clk)
CLK_MHZ(clk, CLK_RATE_MHZ)
MAIN_MHZ(solution, CLK_RATE_MHZ)

typedef struct cas_t{
    uint8_t l;
    uint8_t r;
} cas_t;

cas_t cas(uint8_t a, uint8_t b)
{
    uint8_t lo = (a < b) ? a : b;
    uint8_t hi = (a < b) ? b : a;
    cas_t result = { lo, hi };
    return result;
}

uint8_t claude_median(uint8_t window[5])
{
    /* ── Load inputs into named locals ─────────────────────────── */
    uint8_t a0 = window[0];
    uint8_t a1 = window[1];
    uint8_t a2 = window[2];
    uint8_t a3 = window[3];
    uint8_t a4 = window[4];

    /* ── 9-comparator sorting network for N = 5 ────────────────── */
    cas_t p;

    p = cas(a0, a1); a0 = p.l; a1 = p.r;   /* step 1 – sort bottom pair         */
    p = cas(a2, a3); a2 = p.l; a3 = p.r;   /* step 1 – sort top pair (parallel) */

    p = cas(a0, a2); a0 = p.l; a2 = p.r;   /* step 2 – cross-compare lo         */
    p = cas(a1, a3); a1 = p.l; a3 = p.r;   /* step 2 – cross-compare hi         */

    p = cas(a1, a2); a1 = p.l; a2 = p.r;   /* step 3 – sort inner pair          */

    /* Steps 4–7: merge the fifth element (a4) into sorted a0..a3  */
    p = cas(a0, a4); a0 = p.l; a4 = p.r;
    p = cas(a1, a4); a1 = p.l; a4 = p.r;
    p = cas(a2, a4); a2 = p.l; a4 = p.r;
    p = cas(a3, a4); a3 = p.l; a4 = p.r;

    /* ── a0 ≤ a1 ≤ a2 ≤ a3 ≤ a4  →  median is the middle element ─ */
    return a2;
}

#include "arrays.h"
typedef struct window_t{
  uint8_t data[5];
  uint1_t valid;
  uint1_t last;
}window_t;
window_t sliding_window(uint8_t data_in, uint1_t valid, uint1_t last){
  static uint8_t data[5];
  static uint5_t saw_five_elements_one_hot_counter = 1;
  uint1_t saw_five_elements = saw_five_elements_one_hot_counter(4);
  window_t rv;
  rv.data = data;
  rv.last = last;
  if(valid){
    ARRAY_1SHIFT_INTO_TOP(data, 5, data_in)
    rv.data = data; // TODO dont want muxing on rv.data
    if(~saw_five_elements) saw_five_elements_one_hot_counter <<= 1;
    rv.valid = saw_five_elements;
    if(last) saw_five_elements_one_hot_counter = 1;
  }
  return rv;
}

void solution()
{
  window_t w = sliding_window(input.data.stream_fragment, input.valid, input.data.stream_last);
  output.data.fragment = claude_median(w.data);
  output.data.last = w.last;
  output.valid = w.valid;
  input_ready = 1;
}

Compile Log

/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:7114: SyntaxWarning: invalid escape sequence '\/'
  
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:7485: SyntaxWarning: invalid escape sequence '\d'
  )
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10680: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + "_WRITE" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10680: SyntaxWarning: invalid escape sequence '\s'
  r = f"\w+" + "_WRITE" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10682: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + "_WRITE_[0-9]+" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10682: SyntaxWarning: invalid escape sequence '\s'
  r = f"\w+" + "_WRITE_[0-9]+" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10688: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + "_READ" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10688: SyntaxWarning: invalid escape sequence '\s'
  r = f"\w+" + "_READ" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10690: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + "_READ_[0-9]+" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10690: SyntaxWarning: invalid escape sequence '\s'
  r = f"\w+" + "_READ_[0-9]+" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:272: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_SINGLE_INST.h"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:348: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_array(_[0-9]+)+_t"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:374: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_array_N_t.h"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:404: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_bytes_t.h"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:434: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + C_TO_FSM.FSM_EXT + ".h"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:526: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + C_TO_FSM.FSM_EXT
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:598: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_bytes_t"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:652: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_bytes_t"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:1469: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_array_[0-9]+_t"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:1902: SyntaxWarning: invalid escape sequence '\s'
  for type_regex in [f"uint[0-9]+_negate\s?\("]:  # DO int,float negate?
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:1963: SyntaxWarning: invalid escape sequence '\s'
  for type_regex in [f"int[0-9]+_abs\s?\("]:  # Float abs is bit manip func
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2049: SyntaxWarning: invalid escape sequence '\w'
  for type_regex in [f"\w+_mux[0-9]+\s?\("]:
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2245: SyntaxWarning: invalid escape sequence '\s'
  for type_regex in [f"count0s_uint[0-9]+\s?\("]:
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2474: SyntaxWarning: invalid escape sequence '\s'
  regex = type_regex + "_" + op_regex + f"[0-9]+\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2841: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_[0-9]+_[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2877: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"u?int[0-9]+_u?int[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2915: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"[^_][u?]int[0-9]+_[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2955: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"[^_]rotl[0-9]+_[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2988: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"[^_]rotr[0-9]+_[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:3023: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"u?int[0-9]+_uint[0-9]+_[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:3064: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_uint[0-9]+_uint[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:3110: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_uint[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:3147: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_abs\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:3183: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_sign\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:3215: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"bswap_[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:3249: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"uint[0-9]+_array[0-9]+_(?:be|le)\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SYN.py:1183: SyntaxWarning: invalid escape sequence '\/'
  

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Output directory: /submission/user/pipelinec_output
================== Parsing C Code to Logical Hierarchy ================================
Parsing: /submission/user/Solution.c
Preprocessing file...
Parsing C syntax...
Parsing non-function definitions...
Parsing derived fsm logic functions...
Doing old-style code generation based on PipelineC supported text patterns...
Elaborating function dataflow...
Defaulting to pyrtl based timing estimates...
Using PYRTL synthesizing for part: None
Elaborating dataflow of function: cas
Elaborating dataflow of function: claude_median
Elaborating dataflow of function: sliding_window
Elaborating dataflow of function: solution
Elaborating user function hierarchies down to raw HDL logic...
... found: BIN_OP_LT_uint8_t_uint8_t
Doing obvious logic trimming/collapsing...
Writing generated PipelineC code from elaboration to output directories...
Writing cache of parsed information to file...
================== Writing Resulting Logic to File ================================
Writing output files before adding pipelining...
Writing log of integer module instances: /submission/user/pipelinec_output/integer_module_instances.log
Writing VHDL files for all functions (before any added pipelining)...
Writing multi main top level files...
Writing the constant struct+enum definitions as defined from C code...
Writing global wire definitions as parsed from C code...
================== Adding Timing Information from Synthesis Tool ================================
Synthesizing before pipelining to get path delays...

Synthesizing function: sliding_window
Synthesizing function: MUX_uint1_t_uint8_t_uint8_t
Synthesizing function: BIN_OP_MINUS_int9_t_int9_t
Synthesizing function: BIN_OP_LT_uint8_t_uint8_t
Synthesizing function: cas
Synthesizing function: claude_median
Synthesizing function: solution
Function 18/24, elapsed time 0:00:04.262664...
...Waiting on synthesis for: sliding_window
Running: /submission/user/pipelinec_output/sliding_window/pyrtl_0CLK_295015b8.log
Running: /submission/user/pipelinec_output/built_in/BIN_OP_LT_uint8_t_uint8_t/pyrtl_0CLK_380ecc95.log
Running: /submission/user/pipelinec_output/built_in/BIN_OP_MINUS_int9_t_int9_t/pyrtl_0CLK_de264c78.log
Running: /submission/user/pipelinec_output/built_in/MUX_uint1_t_uint8_t_uint8_t/pyrtl_0CLK_de264c78.log
Running: /submission/user/pipelinec_output/cas/pyrtl_0CLK_a72cdf86.log
Running: /submission/user/pipelinec_output/claude_median/pyrtl_0CLK_f776743d.log
Running: /submission/user/pipelinec_output/solution/pyrtl_0CLK_c86015b8.log
sliding_window FMAX: 625.000 MHz (1.600 ns path delay)
Function 19/24, elapsed time 0:00:05.816353...
...Waiting on synthesis for: MUX_uint1_t_uint8_t_uint8_t
MUX_uint1_t_uint8_t_uint8_t Path delay (maybe to be pipelined): 0.505 ns
Function 20/24, elapsed time 0:00:05.816625...
...Waiting on synthesis for: BIN_OP_MINUS_int9_t_int9_t
BIN_OP_MINUS_int9_t_int9_t Path delay (maybe to be pipelined): 3.030 ns
Function 21/24, elapsed time 0:00:05.816816...
...Waiting on synthesis for: BIN_OP_LT_uint8_t_uint8_t
BIN_OP_LT_uint8_t_uint8_t Path delay (maybe to be pipelined): 2.442 ns
Function 22/24, elapsed time 0:00:05.816978...
...Waiting on synthesis for: cas
cas Path delay (maybe to be pipelined): 2.586 ns
Function 23/24, elapsed time 0:00:06.192755...
...Waiting on synthesis for: claude_median
claude_median Path delay (maybe to be pipelined): 12.928 ns
Function 24/24, elapsed time 0:00:07.122501...
...Waiting on synthesis for: solution
solution Path delay (maybe to be pipelined): 13.629 ns
================== Beginning Throughput Sweep ================================
Function: solution Target MHz: 335.0
Starting with no added pipelining...
Starting with blank sweep state...
Starting middle out sweep...
Starting from timing params without added pipelining...
Collecting modules to pipeline...
Pipelining modules...
Best guess slicing: solution 13.6 (ns) in to target 2.985074626865672 (ns) , mult = 1.0 ~= 4 clks
Updating output files...
Estimated register usage: /submission/user/pipelinec_output/solution/solution_f84f_registers.log
Running syn w timing params...
Elapsed time: 0:00:08.342796...
solution : 4 clocks latency total...
Running: /submission/user/pipelinec_output/solution/pyrtl_f84f.log
solution Clock Goal: 335.00 (MHz) Current: 194.87 (MHz)(5.13 ns) 4 clks
Best guess sweep multiplier: 1.7190659000000004
Starting from timing params without added pipelining...
Collecting modules to pipeline...
Pipelining modules...
Best guess slicing: solution 13.6 (ns) in to target 2.985074626865672 (ns) , mult = 1.7190659000000004 ~= 7 clks
Updating output files...
Estimated register usage: /submission/user/pipelinec_output/solution/solution_d6fa_registers.log
Running syn w timing params...
Elapsed time: 0:00:13.218347...
solution : 7 clocks latency total...
Running: /submission/user/pipelinec_output/solution/pyrtl_d6fa.log
solution Clock Goal: 335.00 (MHz) Current: 266.19 (MHz)(3.76 ns) 7 clks
Best guess sweep multiplier: 2.1634695335121403
Starting from timing params without added pipelining...
Collecting modules to pipeline...
Pipelining modules...
Best guess slicing: solution 13.6 (ns) in to target 2.985074626865672 (ns) , mult = 2.1634695335121403 ~= 9 clks
Updating output files...
Estimated register usage: /submission/user/pipelinec_output/solution/solution_8d48_registers.log
Running syn w timing params...
Elapsed time: 0:00:18.871803...
solution : 9 clocks latency total...
Running: /submission/user/pipelinec_output/solution/pyrtl_8d48.log
solution Clock Goal: 335.00 (MHz) Current: 331.18 (MHz)(3.02 ns) 9 clks
Best guess sweep multiplier: 2.1884052506614946
Starting from timing params without added pipelining...
Collecting modules to pipeline...
Pipelining modules...
Best guess slicing: solution 13.6 (ns) in to target 2.985074626865672 (ns) , mult = 2.1884052506614946 ~= 9 clks
Updating output files...
Estimated register usage: /submission/user/pipelinec_output/solution/solution_8d48_registers.log
Running syn w timing params...
Elapsed time: 0:00:24.900968...
solution : 9 clocks latency total...
Reading log /submission/user/pipelinec_output/solution/pyrtl_8d48.log
solution Clock Goal: 335.00 (MHz) Current: 331.18 (MHz)(3.02 ns) 9 clks
Best guess sweep multiplier: 2.213628371899569
Starting from timing params without added pipelining...
Collecting modules to pipeline...
Pipelining modules...
Best guess slicing: solution 13.6 (ns) in to target 2.985074626865672 (ns) , mult = 2.213628371899569 ~= 10 clks
Updating output files...
Estimated register usage: /submission/user/pipelinec_output/solution/solution_e5a6_registers.log
Running syn w timing params...
Elapsed time: 0:00:24.966161...
solution : 10 clocks latency total...
Running: /submission/user/pipelinec_output/solution/pyrtl_e5a6.log
solution Clock Goal: 335.00 (MHz) Current: 356.94 (MHz)(2.80 ns) 10 clks
Met timing...
================== Writing Results of Throughput Sweep ================================
Output VHDL files: /submission/user/pipelinec_output/vhdl_files.txt
Done.

Generated Verilog

module Solution(
    input clk,
    input reset,
    input i_valid,
    output i_ready,
    input [7:0] i_payload_stream_fragment,
    input i_payload_stream_last,
    output o_valid,
    output [7:0] o_payload_fragment,
    output o_payload_last
);

    wire [8:0] input_data;
    assign input_data = { i_payload_stream_last, i_payload_stream_fragment };

    wire [8:0] output_data;
    wire output_valid;
    wire output_input_ready;

    solution inner(
        .clk(clk),
        .\input[data] (input_data),
        .\input[valid] (i_valid),
        .\output[data] (output_data),
        .\output[valid] (output_valid),
        .input_ready(output_input_ready)
    );

    assign i_ready = output_input_ready;
    assign o_valid = output_valid;
    assign o_payload_fragment = output_data[7:0];
    assign o_payload_last = output_data[8:8];

endmodule


/* Generated by Yosys 0.55 (git sha1 60f126cd00c94892782470192d6c9f7abebe7c05, g++ 14.3.0 -fPIC -O3) */

module bin_op_lt_uint8_t_uint8_t_1clk_046a4912(clk, left, right, return_output);
  wire [9:0] _0_;
  wire [8:0] bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_left;
  wire [9:0] bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_return_output;
  wire [8:0] bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_right;
  input clk;
  wire clk;
  input [7:0] left;
  wire [7:0] left;
  output return_output;
  wire return_output;
  input [7:0] right;
  wire [7:0] right;
  bin_op_minus_int9_t_int9_t_1clk_01ccb89b bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9 (
    .clk(clk),
    .left(bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_left),
    .return_output(_0_),
    .right(bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_right)
  );
  assign bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_left = { 1'h0, left };
  assign bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_right = { 1'h0, right };
  assign bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_return_output = _0_;
  assign return_output = bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_return_output[8];
endmodule

module bin_op_lt_uint8_t_uint8_t_1clk_313573eb(clk, left, right, return_output);
  wire [9:0] _0_;
  wire [8:0] bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_left;
  wire [9:0] bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_return_output;
  wire [8:0] bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_right;
  input clk;
  wire clk;
  input [7:0] left;
  wire [7:0] left;
  output return_output;
  wire return_output;
  input [7:0] right;
  wire [7:0] right;
  bin_op_minus_int9_t_int9_t_1clk_7e88f82f bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9 (
    .clk(clk),
    .left(bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_left),
    .return_output(_0_),
    .right(bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_right)
  );
  assign bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_left = { 1'h0, left };
  assign bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_right = { 1'h0, right };
  assign bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_return_output = _0_;
  assign return_output = bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_return_output[8];
endmodule

module bin_op_lt_uint8_t_uint8_t_1clk_6615fba5(clk, left, right, return_output);
  wire [9:0] _0_;
  wire [8:0] bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_left;
  wire [9:0] bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_return_output;
  wire [8:0] bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_right;
  input clk;
  wire clk;
  input [7:0] left;
  wire [7:0] left;
  output return_output;
  wire return_output;
  input [7:0] right;
  wire [7:0] right;
  bin_op_minus_int9_t_int9_t_1clk_a4e459e8 bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9 (
    .clk(clk),
    .left(bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_left),
    .return_output(_0_),
    .right(bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_right)
  );
  assign bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_left = { 1'h0, left };
  assign bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_right = { 1'h0, right };
  assign bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_return_output = _0_;
  assign return_output = bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_return_output[8];
endmodule

module bin_op_lt_uint8_t_uint8_t_1clk_dd4c22f5(clk, left, right, return_output);
  wire [9:0] _0_;
  wire [8:0] bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_left;
  wire [9:0] bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_return_output;
  wire [8:0] bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_right;
  input clk;
  wire clk;
  input [7:0] left;
  wire [7:0] left;
  output return_output;
  wire return_output;
  input [7:0] right;
  wire [7:0] right;
  bin_op_minus_int9_t_int9_t_1clk_538a228b bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9 (
    .clk(clk),
    .left(bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_left),
    .return_output(_0_),
    .right(bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_right)
  );
  assign bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_left = { 1'h0, left };
  assign bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_right = { 1'h0, right };
  assign bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_return_output = _0_;
  assign return_output = bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_return_output[8];
endmodule

module bin_op_lt_uint8_t_uint8_t_1clk_f256b9d9(clk, left, right, return_output);
  wire [9:0] _0_;
  wire [8:0] bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_left;
  wire [9:0] bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_return_output;
  wire [8:0] bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_right;
  input clk;
  wire clk;
  input [7:0] left;
  wire [7:0] left;
  output return_output;
  wire return_output;
  input [7:0] right;
  wire [7:0] right;
  bin_op_minus_int9_t_int9_t_1clk_19818444 bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9 (
    .clk(clk),
    .left(bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_left),
    .return_output(_0_),
    .right(bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_right)
  );
  assign bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_left = { 1'h0, left };
  assign bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_right = { 1'h0, right };
  assign bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_return_output = _0_;
  assign return_output = bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9_return_output[8];
endmodule

module bin_op_minus_int9_t_int9_t_1clk_01ccb89b(clk, left, right, return_output);
  wire [5:0] _0_;
  wire [5:0] _1_;
  wire [4:0] _2_;
  wire [4:0] _3_;
  reg [169:0] _4_;
  wire [84:0] \:1429.read_pipe ;
  input clk;
  wire clk;
  input [8:0] left;
  wire [8:0] left;
  wire [169:0] manual_registers;
  wire [169:0] manual_registers_r;
  output [9:0] return_output;
  wire [9:0] return_output;
  input [8:0] right;
  wire [8:0] right;
  assign _0_ = { 1'h0, left[4:0] } - { 1'h0, right[4:0] };
  assign _1_ = _0_ - 6'h00;
  assign _2_ = { manual_registers_r[104], manual_registers_r[104:101] } - { manual_registers_r[113], manual_registers_r[113:110] };
  assign _3_ = _2_ - { 4'h0, manual_registers_r[85] };
  always @(posedge clk)
    _4_ <= manual_registers;
  assign manual_registers = { left, right, 15'h0000, _1_[4:0], 4'h0, right[4:0], 4'h0, left[4:0], right, left, 4'h0, _1_, _1_[5], manual_registers_r[169:152], _3_, manual_registers_r[136:132], _3_, manual_registers_r[136:132], 5'h00, manual_registers_r[113:110], 5'h00, manual_registers_r[104:101], manual_registers_r[113:96], 5'h00, _3_, _3_[4] };
  assign manual_registers_r = _4_;
  assign \:1429.read_pipe  = manual_registers_r[169:85];
  assign return_output = { _3_, manual_registers_r[136:132] };
endmodule

module bin_op_minus_int9_t_int9_t_1clk_19818444(clk, left, right, return_output);
  wire [5:0] _0_;
  wire [5:0] _1_;
  wire [4:0] _2_;
  wire [4:0] _3_;
  reg [169:0] _4_;
  wire [84:0] \:1316.read_pipe ;
  input clk;
  wire clk;
  input [8:0] left;
  wire [8:0] left;
  wire [169:0] manual_registers;
  wire [169:0] manual_registers_r;
  output [9:0] return_output;
  wire [9:0] return_output;
  input [8:0] right;
  wire [8:0] right;
  assign _0_ = { 1'h0, left[4:0] } - { 1'h0, right[4:0] };
  assign _1_ = _0_ - 6'h00;
  assign _2_ = { manual_registers_r[104], manual_registers_r[104:101] } - { manual_registers_r[113], manual_registers_r[113:110] };
  assign _3_ = _2_ - { 4'h0, manual_registers_r[85] };
  always @(posedge clk)
    _4_ <= manual_registers;
  assign manual_registers = { left, right, 15'h0000, _1_[4:0], 4'h0, right[4:0], 4'h0, left[4:0], right, left, 4'h0, _1_, _1_[5], manual_registers_r[169:152], _3_, manual_registers_r[136:132], _3_, manual_registers_r[136:132], 5'h00, manual_registers_r[113:110], 5'h00, manual_registers_r[104:101], manual_registers_r[113:96], 5'h00, _3_, _3_[4] };
  assign manual_registers_r = _4_;
  assign \:1316.read_pipe  = manual_registers_r[169:85];
  assign return_output = { _3_, manual_registers_r[136:132] };
endmodule

module bin_op_minus_int9_t_int9_t_1clk_538a228b(clk, left, right, return_output);
  wire [4:0] _0_;
  wire [4:0] _1_;
  wire [5:0] _2_;
  wire [5:0] _3_;
  reg [169:0] _4_;
  wire [84:0] \:1090.read_pipe ;
  input clk;
  wire clk;
  input [8:0] left;
  wire [8:0] left;
  wire [169:0] manual_registers;
  wire [169:0] manual_registers_r;
  output [9:0] return_output;
  wire [9:0] return_output;
  input [8:0] right;
  wire [8:0] right;
  assign _0_ = { 1'h0, left[3:0] } - { 1'h0, right[3:0] };
  assign _1_ = _0_ - 5'h00;
  assign _2_ = { manual_registers_r[104], manual_registers_r[104:100] } - { manual_registers_r[113], manual_registers_r[113:109] };
  assign _3_ = _2_ - { 5'h00, manual_registers_r[85] };
  always @(posedge clk)
    _4_ <= manual_registers;
  assign manual_registers = { left, right, 16'h0000, _1_[3:0], 5'h00, right[3:0], 5'h00, left[3:0], right, left, 5'h00, _1_, _1_[4], manual_registers_r[169:152], _3_, manual_registers_r[135:132], _3_, manual_registers_r[135:132], 4'h0, manual_registers_r[113:109], 4'h0, manual_registers_r[104:100], manual_registers_r[113:96], 4'h0, _3_, _3_[5] };
  assign manual_registers_r = _4_;
  assign \:1090.read_pipe  = manual_registers_r[169:85];
  assign return_output = { _3_, manual_registers_r[135:132] };
endmodule

module bin_op_minus_int9_t_int9_t_1clk_7e88f82f(clk, left, right, return_output);
  wire [5:0] _0_;
  wire [5:0] _1_;
  wire [4:0] _2_;
  wire [4:0] _3_;
  reg [169:0] _4_;
  wire [84:0] \:1203.read_pipe ;
  input clk;
  wire clk;
  input [8:0] left;
  wire [8:0] left;
  wire [169:0] manual_registers;
  wire [169:0] manual_registers_r;
  output [9:0] return_output;
  wire [9:0] return_output;
  input [8:0] right;
  wire [8:0] right;
  assign _0_ = { 1'h0, left[4:0] } - { 1'h0, right[4:0] };
  assign _1_ = _0_ - 6'h00;
  assign _2_ = { manual_registers_r[104], manual_registers_r[104:101] } - { manual_registers_r[113], manual_registers_r[113:110] };
  assign _3_ = _2_ - { 4'h0, manual_registers_r[85] };
  always @(posedge clk)
    _4_ <= manual_registers;
  assign manual_registers = { left, right, 15'h0000, _1_[4:0], 4'h0, right[4:0], 4'h0, left[4:0], right, left, 4'h0, _1_, _1_[5], manual_registers_r[169:152], _3_, manual_registers_r[136:132], _3_, manual_registers_r[136:132], 5'h00, manual_registers_r[113:110], 5'h00, manual_registers_r[104:101], manual_registers_r[113:96], 5'h00, _3_, _3_[4] };
  assign manual_registers_r = _4_;
  assign \:1203.read_pipe  = manual_registers_r[169:85];
  assign return_output = { _3_, manual_registers_r[136:132] };
endmodule

module bin_op_minus_int9_t_int9_t_1clk_a4e459e8(clk, left, right, return_output);
  wire [5:0] _0_;
  wire [5:0] _1_;
  wire [4:0] _2_;
  wire [4:0] _3_;
  reg [169:0] _4_;
  wire [84:0] \:1542.read_pipe ;
  input clk;
  wire clk;
  input [8:0] left;
  wire [8:0] left;
  wire [169:0] manual_registers;
  wire [169:0] manual_registers_r;
  output [9:0] return_output;
  wire [9:0] return_output;
  input [8:0] right;
  wire [8:0] right;
  assign _0_ = { 1'h0, left[4:0] } - { 1'h0, right[4:0] };
  assign _1_ = _0_ - 6'h00;
  assign _2_ = { manual_registers_r[104], manual_registers_r[104:101] } - { manual_registers_r[113], manual_registers_r[113:110] };
  assign _3_ = _2_ - { 4'h0, manual_registers_r[85] };
  always @(posedge clk)
    _4_ <= manual_registers;
  assign manual_registers = { left, right, 15'h0000, _1_[4:0], 4'h0, right[4:0], 4'h0, left[4:0], right, left, 4'h0, _1_, _1_[5], manual_registers_r[169:152], _3_, manual_registers_r[136:132], _3_, manual_registers_r[136:132], 5'h00, manual_registers_r[113:110], 5'h00, manual_registers_r[104:101], manual_registers_r[113:96], 5'h00, _3_, _3_[4] };
  assign manual_registers_r = _4_;
  assign \:1542.read_pipe  = manual_registers_r[169:85];
  assign return_output = { _3_, manual_registers_r[136:132] };
endmodule

module cas_1clk_ae17090d(clk, a, b, \return_output[l] , \return_output[r] );
  wire [7:0] _0_;
  wire [7:0] _1_;
  wire _2_;
  reg [7:0] _3_;
  reg [7:0] _4_;
  reg [7:0] _5_;
  reg [7:0] _6_;
  input [7:0] a;
  wire [7:0] a;
  input [7:0] b;
  wire [7:0] b;
  wire [7:0] bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_left;
  wire bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_return_output;
  wire [7:0] bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_right;
  input clk;
  wire clk;
  wire [7:0] comb_stage0_mux_solution_c_l46_c19_f623_iffalse;
  wire [7:0] comb_stage0_mux_solution_c_l46_c19_f623_iftrue;
  wire [7:0] comb_stage0_mux_solution_c_l47_c19_e080_iffalse;
  wire [7:0] comb_stage0_mux_solution_c_l47_c19_e080_iftrue;
  wire mux_solution_c_l46_c19_f623_cond;
  wire [7:0] mux_solution_c_l46_c19_f623_iffalse;
  wire [7:0] mux_solution_c_l46_c19_f623_iftrue;
  wire [7:0] mux_solution_c_l46_c19_f623_return_output;
  wire mux_solution_c_l47_c19_e080_cond;
  wire [7:0] mux_solution_c_l47_c19_e080_iffalse;
  wire [7:0] mux_solution_c_l47_c19_e080_iftrue;
  wire [7:0] mux_solution_c_l47_c19_e080_return_output;
  wire [7:0] reg_stage0_mux_solution_c_l46_c19_f623_iffalse;
  wire [7:0] reg_stage0_mux_solution_c_l46_c19_f623_iftrue;
  wire [7:0] reg_stage0_mux_solution_c_l47_c19_e080_iffalse;
  wire [7:0] reg_stage0_mux_solution_c_l47_c19_e080_iftrue;
  output [7:0] \return_output[l] ;
  wire [7:0] \return_output[l] ;
  output [7:0] \return_output[r] ;
  wire [7:0] \return_output[r] ;
  always @(posedge clk)
    _3_ <= comb_stage0_mux_solution_c_l46_c19_f623_iftrue;
  always @(posedge clk)
    _4_ <= comb_stage0_mux_solution_c_l46_c19_f623_iffalse;
  always @(posedge clk)
    _5_ <= comb_stage0_mux_solution_c_l47_c19_e080_iftrue;
  always @(posedge clk)
    _6_ <= comb_stage0_mux_solution_c_l47_c19_e080_iffalse;
  bin_op_lt_uint8_t_uint8_t_1clk_6615fba5 bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3 (
    .clk(clk),
    .left(bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_left),
    .return_output(_2_),
    .right(bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_right)
  );
  mux_uint1_t_uint8_t_uint8_t_0clk_de264c78 mux_solution_c_l46_c19_f623 (
    .cond(mux_solution_c_l46_c19_f623_cond),
    .iffalse(mux_solution_c_l46_c19_f623_iffalse),
    .iftrue(mux_solution_c_l46_c19_f623_iftrue),
    .return_output(_0_)
  );
  mux_uint1_t_uint8_t_uint8_t_0clk_de264c78 mux_solution_c_l47_c19_e080 (
    .cond(mux_solution_c_l47_c19_e080_cond),
    .iffalse(mux_solution_c_l47_c19_e080_iffalse),
    .iftrue(mux_solution_c_l47_c19_e080_iftrue),
    .return_output(_1_)
  );
  assign reg_stage0_mux_solution_c_l46_c19_f623_iftrue = _3_;
  assign reg_stage0_mux_solution_c_l46_c19_f623_iffalse = _4_;
  assign reg_stage0_mux_solution_c_l47_c19_e080_iftrue = _5_;
  assign reg_stage0_mux_solution_c_l47_c19_e080_iffalse = _6_;
  assign comb_stage0_mux_solution_c_l46_c19_f623_iftrue = a;
  assign comb_stage0_mux_solution_c_l46_c19_f623_iffalse = b;
  assign comb_stage0_mux_solution_c_l47_c19_e080_iftrue = b;
  assign comb_stage0_mux_solution_c_l47_c19_e080_iffalse = a;
  assign mux_solution_c_l46_c19_f623_cond = bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_return_output;
  assign mux_solution_c_l46_c19_f623_iftrue = reg_stage0_mux_solution_c_l46_c19_f623_iftrue;
  assign mux_solution_c_l46_c19_f623_iffalse = reg_stage0_mux_solution_c_l46_c19_f623_iffalse;
  assign mux_solution_c_l46_c19_f623_return_output = _0_;
  assign mux_solution_c_l47_c19_e080_cond = bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_return_output;
  assign mux_solution_c_l47_c19_e080_iftrue = reg_stage0_mux_solution_c_l47_c19_e080_iftrue;
  assign mux_solution_c_l47_c19_e080_iffalse = reg_stage0_mux_solution_c_l47_c19_e080_iffalse;
  assign mux_solution_c_l47_c19_e080_return_output = _1_;
  assign bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_left = a;
  assign bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_right = b;
  assign bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_return_output = _2_;
  assign \return_output[l]  = mux_solution_c_l46_c19_f623_return_output;
  assign \return_output[r]  = mux_solution_c_l47_c19_e080_return_output;
endmodule

module cas_2clk_247944ad(clk, a, b, \return_output[l] , \return_output[r] );
  wire [7:0] _0_;
  wire [7:0] _1_;
  wire _2_;
  reg [7:0] _3_;
  reg [7:0] _4_;
  reg [7:0] _5_;
  reg [7:0] _6_;
  input [7:0] a;
  wire [7:0] a;
  input [7:0] b;
  wire [7:0] b;
  wire [7:0] bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_left;
  wire bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_return_output;
  wire [7:0] bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_right;
  input clk;
  wire clk;
  wire [7:0] comb_stage0_mux_solution_c_l46_c19_f623_iffalse;
  wire [7:0] comb_stage0_mux_solution_c_l46_c19_f623_iftrue;
  wire [7:0] comb_stage0_mux_solution_c_l47_c19_e080_iffalse;
  wire [7:0] comb_stage0_mux_solution_c_l47_c19_e080_iftrue;
  wire mux_solution_c_l46_c19_f623_cond;
  wire [7:0] mux_solution_c_l46_c19_f623_iffalse;
  wire [7:0] mux_solution_c_l46_c19_f623_iftrue;
  wire [7:0] mux_solution_c_l46_c19_f623_return_output;
  wire mux_solution_c_l47_c19_e080_cond;
  wire [7:0] mux_solution_c_l47_c19_e080_iffalse;
  wire [7:0] mux_solution_c_l47_c19_e080_iftrue;
  wire [7:0] mux_solution_c_l47_c19_e080_return_output;
  wire [7:0] reg_stage0_mux_solution_c_l46_c19_f623_iffalse;
  wire [7:0] reg_stage0_mux_solution_c_l46_c19_f623_iftrue;
  wire [7:0] reg_stage0_mux_solution_c_l47_c19_e080_iffalse;
  wire [7:0] reg_stage0_mux_solution_c_l47_c19_e080_iftrue;
  output [7:0] \return_output[l] ;
  wire [7:0] \return_output[l] ;
  output [7:0] \return_output[r] ;
  wire [7:0] \return_output[r] ;
  always @(posedge clk)
    _3_ <= comb_stage0_mux_solution_c_l46_c19_f623_iftrue;
  always @(posedge clk)
    _4_ <= comb_stage0_mux_solution_c_l46_c19_f623_iffalse;
  always @(posedge clk)
    _5_ <= comb_stage0_mux_solution_c_l47_c19_e080_iftrue;
  always @(posedge clk)
    _6_ <= comb_stage0_mux_solution_c_l47_c19_e080_iffalse;
  bin_op_lt_uint8_t_uint8_t_1clk_046a4912 bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3 (
    .clk(clk),
    .left(bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_left),
    .return_output(_2_),
    .right(bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_right)
  );
  mux_uint1_t_uint8_t_uint8_t_1clk_46dc7b5a mux_solution_c_l46_c19_f623 (
    .clk(clk),
    .cond(mux_solution_c_l46_c19_f623_cond),
    .iffalse(mux_solution_c_l46_c19_f623_iffalse),
    .iftrue(mux_solution_c_l46_c19_f623_iftrue),
    .return_output(_0_)
  );
  mux_uint1_t_uint8_t_uint8_t_1clk_46dc7b5a mux_solution_c_l47_c19_e080 (
    .clk(clk),
    .cond(mux_solution_c_l47_c19_e080_cond),
    .iffalse(mux_solution_c_l47_c19_e080_iffalse),
    .iftrue(mux_solution_c_l47_c19_e080_iftrue),
    .return_output(_1_)
  );
  assign reg_stage0_mux_solution_c_l46_c19_f623_iftrue = _3_;
  assign reg_stage0_mux_solution_c_l46_c19_f623_iffalse = _4_;
  assign reg_stage0_mux_solution_c_l47_c19_e080_iftrue = _5_;
  assign reg_stage0_mux_solution_c_l47_c19_e080_iffalse = _6_;
  assign comb_stage0_mux_solution_c_l46_c19_f623_iftrue = a;
  assign comb_stage0_mux_solution_c_l46_c19_f623_iffalse = b;
  assign comb_stage0_mux_solution_c_l47_c19_e080_iftrue = b;
  assign comb_stage0_mux_solution_c_l47_c19_e080_iffalse = a;
  assign mux_solution_c_l46_c19_f623_cond = bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_return_output;
  assign mux_solution_c_l46_c19_f623_iftrue = reg_stage0_mux_solution_c_l46_c19_f623_iftrue;
  assign mux_solution_c_l46_c19_f623_iffalse = reg_stage0_mux_solution_c_l46_c19_f623_iffalse;
  assign mux_solution_c_l46_c19_f623_return_output = _0_;
  assign mux_solution_c_l47_c19_e080_cond = bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_return_output;
  assign mux_solution_c_l47_c19_e080_iftrue = reg_stage0_mux_solution_c_l47_c19_e080_iftrue;
  assign mux_solution_c_l47_c19_e080_iffalse = reg_stage0_mux_solution_c_l47_c19_e080_iffalse;
  assign mux_solution_c_l47_c19_e080_return_output = _1_;
  assign bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_left = a;
  assign bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_right = b;
  assign bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_return_output = _2_;
  assign \return_output[l]  = mux_solution_c_l46_c19_f623_return_output;
  assign \return_output[r]  = mux_solution_c_l47_c19_e080_return_output;
endmodule

module cas_2clk_4973135e(clk, a, b, \return_output[l] , \return_output[r] );
  wire [7:0] _0_;
  wire [7:0] _1_;
  wire _2_;
  reg [7:0] _3_;
  reg [7:0] _4_;
  reg [7:0] _5_;
  reg [7:0] _6_;
  input [7:0] a;
  wire [7:0] a;
  input [7:0] b;
  wire [7:0] b;
  wire [7:0] bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_left;
  wire bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_return_output;
  wire [7:0] bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_right;
  input clk;
  wire clk;
  wire [7:0] comb_stage0_mux_solution_c_l46_c19_f623_iffalse;
  wire [7:0] comb_stage0_mux_solution_c_l46_c19_f623_iftrue;
  wire [7:0] comb_stage0_mux_solution_c_l47_c19_e080_iffalse;
  wire [7:0] comb_stage0_mux_solution_c_l47_c19_e080_iftrue;
  wire mux_solution_c_l46_c19_f623_cond;
  wire [7:0] mux_solution_c_l46_c19_f623_iffalse;
  wire [7:0] mux_solution_c_l46_c19_f623_iftrue;
  wire [7:0] mux_solution_c_l46_c19_f623_return_output;
  wire mux_solution_c_l47_c19_e080_cond;
  wire [7:0] mux_solution_c_l47_c19_e080_iffalse;
  wire [7:0] mux_solution_c_l47_c19_e080_iftrue;
  wire [7:0] mux_solution_c_l47_c19_e080_return_output;
  wire [7:0] reg_stage0_mux_solution_c_l46_c19_f623_iffalse;
  wire [7:0] reg_stage0_mux_solution_c_l46_c19_f623_iftrue;
  wire [7:0] reg_stage0_mux_solution_c_l47_c19_e080_iffalse;
  wire [7:0] reg_stage0_mux_solution_c_l47_c19_e080_iftrue;
  output [7:0] \return_output[l] ;
  wire [7:0] \return_output[l] ;
  output [7:0] \return_output[r] ;
  wire [7:0] \return_output[r] ;
  always @(posedge clk)
    _3_ <= comb_stage0_mux_solution_c_l46_c19_f623_iftrue;
  always @(posedge clk)
    _4_ <= comb_stage0_mux_solution_c_l46_c19_f623_iffalse;
  always @(posedge clk)
    _5_ <= comb_stage0_mux_solution_c_l47_c19_e080_iftrue;
  always @(posedge clk)
    _6_ <= comb_stage0_mux_solution_c_l47_c19_e080_iffalse;
  bin_op_lt_uint8_t_uint8_t_1clk_f256b9d9 bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3 (
    .clk(clk),
    .left(bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_left),
    .return_output(_2_),
    .right(bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_right)
  );
  mux_uint1_t_uint8_t_uint8_t_1clk_76079683 mux_solution_c_l46_c19_f623 (
    .clk(clk),
    .cond(mux_solution_c_l46_c19_f623_cond),
    .iffalse(mux_solution_c_l46_c19_f623_iffalse),
    .iftrue(mux_solution_c_l46_c19_f623_iftrue),
    .return_output(_0_)
  );
  mux_uint1_t_uint8_t_uint8_t_1clk_76079683 mux_solution_c_l47_c19_e080 (
    .clk(clk),
    .cond(mux_solution_c_l47_c19_e080_cond),
    .iffalse(mux_solution_c_l47_c19_e080_iffalse),
    .iftrue(mux_solution_c_l47_c19_e080_iftrue),
    .return_output(_1_)
  );
  assign reg_stage0_mux_solution_c_l46_c19_f623_iftrue = _3_;
  assign reg_stage0_mux_solution_c_l46_c19_f623_iffalse = _4_;
  assign reg_stage0_mux_solution_c_l47_c19_e080_iftrue = _5_;
  assign reg_stage0_mux_solution_c_l47_c19_e080_iffalse = _6_;
  assign comb_stage0_mux_solution_c_l46_c19_f623_iftrue = a;
  assign comb_stage0_mux_solution_c_l46_c19_f623_iffalse = b;
  assign comb_stage0_mux_solution_c_l47_c19_e080_iftrue = b;
  assign comb_stage0_mux_solution_c_l47_c19_e080_iffalse = a;
  assign mux_solution_c_l46_c19_f623_cond = bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_return_output;
  assign mux_solution_c_l46_c19_f623_iftrue = reg_stage0_mux_solution_c_l46_c19_f623_iftrue;
  assign mux_solution_c_l46_c19_f623_iffalse = reg_stage0_mux_solution_c_l46_c19_f623_iffalse;
  assign mux_solution_c_l46_c19_f623_return_output = _0_;
  assign mux_solution_c_l47_c19_e080_cond = bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_return_output;
  assign mux_solution_c_l47_c19_e080_iftrue = reg_stage0_mux_solution_c_l47_c19_e080_iftrue;
  assign mux_solution_c_l47_c19_e080_iffalse = reg_stage0_mux_solution_c_l47_c19_e080_iffalse;
  assign mux_solution_c_l47_c19_e080_return_output = _1_;
  assign bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_left = a;
  assign bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_right = b;
  assign bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_return_output = _2_;
  assign \return_output[l]  = mux_solution_c_l46_c19_f623_return_output;
  assign \return_output[r]  = mux_solution_c_l47_c19_e080_return_output;
endmodule

module cas_2clk_50f68833(clk, a, b, \return_output[l] , \return_output[r] );
  wire [7:0] _0_;
  wire [7:0] _1_;
  wire _2_;
  reg [7:0] _3_;
  reg [7:0] _4_;
  reg [7:0] _5_;
  reg [7:0] _6_;
  input [7:0] a;
  wire [7:0] a;
  input [7:0] b;
  wire [7:0] b;
  wire [7:0] bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_left;
  wire bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_return_output;
  wire [7:0] bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_right;
  input clk;
  wire clk;
  wire [7:0] comb_stage0_mux_solution_c_l46_c19_f623_iffalse;
  wire [7:0] comb_stage0_mux_solution_c_l46_c19_f623_iftrue;
  wire [7:0] comb_stage0_mux_solution_c_l47_c19_e080_iffalse;
  wire [7:0] comb_stage0_mux_solution_c_l47_c19_e080_iftrue;
  wire mux_solution_c_l46_c19_f623_cond;
  wire [7:0] mux_solution_c_l46_c19_f623_iffalse;
  wire [7:0] mux_solution_c_l46_c19_f623_iftrue;
  wire [7:0] mux_solution_c_l46_c19_f623_return_output;
  wire mux_solution_c_l47_c19_e080_cond;
  wire [7:0] mux_solution_c_l47_c19_e080_iffalse;
  wire [7:0] mux_solution_c_l47_c19_e080_iftrue;
  wire [7:0] mux_solution_c_l47_c19_e080_return_output;
  wire [7:0] reg_stage0_mux_solution_c_l46_c19_f623_iffalse;
  wire [7:0] reg_stage0_mux_solution_c_l46_c19_f623_iftrue;
  wire [7:0] reg_stage0_mux_solution_c_l47_c19_e080_iffalse;
  wire [7:0] reg_stage0_mux_solution_c_l47_c19_e080_iftrue;
  output [7:0] \return_output[l] ;
  wire [7:0] \return_output[l] ;
  output [7:0] \return_output[r] ;
  wire [7:0] \return_output[r] ;
  always @(posedge clk)
    _3_ <= comb_stage0_mux_solution_c_l46_c19_f623_iftrue;
  always @(posedge clk)
    _4_ <= comb_stage0_mux_solution_c_l46_c19_f623_iffalse;
  always @(posedge clk)
    _5_ <= comb_stage0_mux_solution_c_l47_c19_e080_iftrue;
  always @(posedge clk)
    _6_ <= comb_stage0_mux_solution_c_l47_c19_e080_iffalse;
  bin_op_lt_uint8_t_uint8_t_1clk_dd4c22f5 bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3 (
    .clk(clk),
    .left(bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_left),
    .return_output(_2_),
    .right(bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_right)
  );
  mux_uint1_t_uint8_t_uint8_t_1clk_93a40912 mux_solution_c_l46_c19_f623 (
    .clk(clk),
    .cond(mux_solution_c_l46_c19_f623_cond),
    .iffalse(mux_solution_c_l46_c19_f623_iffalse),
    .iftrue(mux_solution_c_l46_c19_f623_iftrue),
    .return_output(_0_)
  );
  mux_uint1_t_uint8_t_uint8_t_1clk_93a40912 mux_solution_c_l47_c19_e080 (
    .clk(clk),
    .cond(mux_solution_c_l47_c19_e080_cond),
    .iffalse(mux_solution_c_l47_c19_e080_iffalse),
    .iftrue(mux_solution_c_l47_c19_e080_iftrue),
    .return_output(_1_)
  );
  assign reg_stage0_mux_solution_c_l46_c19_f623_iftrue = _3_;
  assign reg_stage0_mux_solution_c_l46_c19_f623_iffalse = _4_;
  assign reg_stage0_mux_solution_c_l47_c19_e080_iftrue = _5_;
  assign reg_stage0_mux_solution_c_l47_c19_e080_iffalse = _6_;
  assign comb_stage0_mux_solution_c_l46_c19_f623_iftrue = a;
  assign comb_stage0_mux_solution_c_l46_c19_f623_iffalse = b;
  assign comb_stage0_mux_solution_c_l47_c19_e080_iftrue = b;
  assign comb_stage0_mux_solution_c_l47_c19_e080_iffalse = a;
  assign mux_solution_c_l46_c19_f623_cond = bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_return_output;
  assign mux_solution_c_l46_c19_f623_iftrue = reg_stage0_mux_solution_c_l46_c19_f623_iftrue;
  assign mux_solution_c_l46_c19_f623_iffalse = reg_stage0_mux_solution_c_l46_c19_f623_iffalse;
  assign mux_solution_c_l46_c19_f623_return_output = _0_;
  assign mux_solution_c_l47_c19_e080_cond = bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_return_output;
  assign mux_solution_c_l47_c19_e080_iftrue = reg_stage0_mux_solution_c_l47_c19_e080_iftrue;
  assign mux_solution_c_l47_c19_e080_iffalse = reg_stage0_mux_solution_c_l47_c19_e080_iffalse;
  assign mux_solution_c_l47_c19_e080_return_output = _1_;
  assign bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_left = a;
  assign bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_right = b;
  assign bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_return_output = _2_;
  assign \return_output[l]  = mux_solution_c_l46_c19_f623_return_output;
  assign \return_output[r]  = mux_solution_c_l47_c19_e080_return_output;
endmodule

module cas_2clk_70ef9970(clk, a, b, \return_output[l] , \return_output[r] );
  reg [7:0] _0_;
  wire [7:0] _1_;
  wire [7:0] _2_;
  wire _3_;
  reg [7:0] _4_;
  reg [7:0] _5_;
  reg [7:0] _6_;
  input [7:0] a;
  wire [7:0] a;
  input [7:0] b;
  wire [7:0] b;
  wire [7:0] bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_left;
  wire bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_return_output;
  wire [7:0] bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_right;
  input clk;
  wire clk;
  wire [7:0] comb_stage0_mux_solution_c_l46_c19_f623_iffalse;
  wire [7:0] comb_stage0_mux_solution_c_l46_c19_f623_iftrue;
  wire [7:0] comb_stage0_mux_solution_c_l47_c19_e080_iffalse;
  wire [7:0] comb_stage0_mux_solution_c_l47_c19_e080_iftrue;
  wire mux_solution_c_l46_c19_f623_cond;
  wire [7:0] mux_solution_c_l46_c19_f623_iffalse;
  wire [7:0] mux_solution_c_l46_c19_f623_iftrue;
  wire [7:0] mux_solution_c_l46_c19_f623_return_output;
  wire mux_solution_c_l47_c19_e080_cond;
  wire [7:0] mux_solution_c_l47_c19_e080_iffalse;
  wire [7:0] mux_solution_c_l47_c19_e080_iftrue;
  wire [7:0] mux_solution_c_l47_c19_e080_return_output;
  wire [7:0] reg_stage0_mux_solution_c_l46_c19_f623_iffalse;
  wire [7:0] reg_stage0_mux_solution_c_l46_c19_f623_iftrue;
  wire [7:0] reg_stage0_mux_solution_c_l47_c19_e080_iffalse;
  wire [7:0] reg_stage0_mux_solution_c_l47_c19_e080_iftrue;
  output [7:0] \return_output[l] ;
  wire [7:0] \return_output[l] ;
  output [7:0] \return_output[r] ;
  wire [7:0] \return_output[r] ;
  always @(posedge clk)
    _4_ <= comb_stage0_mux_solution_c_l46_c19_f623_iftrue;
  always @(posedge clk)
    _5_ <= comb_stage0_mux_solution_c_l46_c19_f623_iffalse;
  always @(posedge clk)
    _6_ <= comb_stage0_mux_solution_c_l47_c19_e080_iftrue;
  always @(posedge clk)
    _0_ <= comb_stage0_mux_solution_c_l47_c19_e080_iffalse;
  bin_op_lt_uint8_t_uint8_t_1clk_313573eb bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3 (
    .clk(clk),
    .left(bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_left),
    .return_output(_3_),
    .right(bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_right)
  );
  mux_uint1_t_uint8_t_uint8_t_1clk_56fb9438 mux_solution_c_l46_c19_f623 (
    .clk(clk),
    .cond(mux_solution_c_l46_c19_f623_cond),
    .iffalse(mux_solution_c_l46_c19_f623_iffalse),
    .iftrue(mux_solution_c_l46_c19_f623_iftrue),
    .return_output(_1_)
  );
  mux_uint1_t_uint8_t_uint8_t_1clk_56fb9438 mux_solution_c_l47_c19_e080 (
    .clk(clk),
    .cond(mux_solution_c_l47_c19_e080_cond),
    .iffalse(mux_solution_c_l47_c19_e080_iffalse),
    .iftrue(mux_solution_c_l47_c19_e080_iftrue),
    .return_output(_2_)
  );
  assign reg_stage0_mux_solution_c_l46_c19_f623_iftrue = _4_;
  assign reg_stage0_mux_solution_c_l46_c19_f623_iffalse = _5_;
  assign reg_stage0_mux_solution_c_l47_c19_e080_iftrue = _6_;
  assign reg_stage0_mux_solution_c_l47_c19_e080_iffalse = _0_;
  assign comb_stage0_mux_solution_c_l46_c19_f623_iftrue = a;
  assign comb_stage0_mux_solution_c_l46_c19_f623_iffalse = b;
  assign comb_stage0_mux_solution_c_l47_c19_e080_iftrue = b;
  assign comb_stage0_mux_solution_c_l47_c19_e080_iffalse = a;
  assign mux_solution_c_l46_c19_f623_cond = bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_return_output;
  assign mux_solution_c_l46_c19_f623_iftrue = reg_stage0_mux_solution_c_l46_c19_f623_iftrue;
  assign mux_solution_c_l46_c19_f623_iffalse = reg_stage0_mux_solution_c_l46_c19_f623_iffalse;
  assign mux_solution_c_l46_c19_f623_return_output = _1_;
  assign mux_solution_c_l47_c19_e080_cond = bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_return_output;
  assign mux_solution_c_l47_c19_e080_iftrue = reg_stage0_mux_solution_c_l47_c19_e080_iftrue;
  assign mux_solution_c_l47_c19_e080_iffalse = reg_stage0_mux_solution_c_l47_c19_e080_iffalse;
  assign mux_solution_c_l47_c19_e080_return_output = _2_;
  assign bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_left = a;
  assign bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_right = b;
  assign bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3_return_output = _3_;
  assign \return_output[l]  = mux_solution_c_l46_c19_f623_return_output;
  assign \return_output[r]  = mux_solution_c_l47_c19_e080_return_output;
endmodule

module claude_median_9clk_c433c9d8(clk, window, return_output);
  wire [7:0] _00_;
  wire [7:0] _01_;
  wire [7:0] _02_;
  wire [7:0] _03_;
  wire [7:0] _04_;
  wire [7:0] _05_;
  wire [7:0] _06_;
  wire [7:0] _07_;
  wire [7:0] _08_;
  wire [7:0] _09_;
  wire [7:0] _10_;
  wire [7:0] _11_;
  wire [7:0] _12_;
  wire [7:0] _13_;
  wire [7:0] _14_;
  wire [7:0] _15_;
  reg [7:0] _16_;
  reg [7:0] _17_;
  reg [7:0] _18_;
  reg [7:0] _19_;
  reg [7:0] _20_;
  reg [7:0] _21_;
  wire [7:0] cas_solution_c_l64_c9_d58e_a;
  wire [7:0] cas_solution_c_l64_c9_d58e_b;
  wire [15:0] cas_solution_c_l64_c9_d58e_return_output;
  wire [7:0] cas_solution_c_l65_c9_6264_a;
  wire [7:0] cas_solution_c_l65_c9_6264_b;
  wire [15:0] cas_solution_c_l65_c9_6264_return_output;
  wire [7:0] cas_solution_c_l67_c9_abd1_a;
  wire [7:0] cas_solution_c_l67_c9_abd1_b;
  wire [15:0] cas_solution_c_l67_c9_abd1_return_output;
  wire [7:0] cas_solution_c_l68_c9_6d9c_a;
  wire [7:0] cas_solution_c_l68_c9_6d9c_b;
  wire [15:0] cas_solution_c_l68_c9_6d9c_return_output;
  wire [7:0] cas_solution_c_l70_c9_9b28_a;
  wire [7:0] cas_solution_c_l70_c9_9b28_b;
  wire [15:0] cas_solution_c_l70_c9_9b28_return_output;
  wire [7:0] cas_solution_c_l73_c9_dbdc_a;
  wire [7:0] cas_solution_c_l73_c9_dbdc_b;
  wire [15:0] cas_solution_c_l73_c9_dbdc_return_output;
  wire [7:0] cas_solution_c_l74_c9_d2b4_a;
  wire [7:0] cas_solution_c_l74_c9_d2b4_b;
  wire [15:0] cas_solution_c_l74_c9_d2b4_return_output;
  wire [7:0] cas_solution_c_l75_c9_1b24_a;
  wire [7:0] cas_solution_c_l75_c9_1b24_b;
  wire [15:0] cas_solution_c_l75_c9_1b24_return_output;
  input clk;
  wire clk;
  wire [7:0] comb_stage0_cas_solution_c_l73_c9_dbdc_b;
  wire [7:0] comb_stage1_cas_solution_c_l73_c9_dbdc_b;
  wire [7:0] comb_stage2_cas_solution_c_l73_c9_dbdc_b;
  wire [7:0] comb_stage3_cas_solution_c_l73_c9_dbdc_b;
  wire [7:0] comb_stage6_cas_solution_c_l75_c9_1b24_a;
  wire [7:0] comb_stage7_cas_solution_c_l75_c9_1b24_a;
  wire [7:0] reg_stage0_cas_solution_c_l73_c9_dbdc_b;
  wire [7:0] reg_stage1_cas_solution_c_l73_c9_dbdc_b;
  wire [7:0] reg_stage2_cas_solution_c_l73_c9_dbdc_b;
  wire [7:0] reg_stage3_cas_solution_c_l73_c9_dbdc_b;
  wire [7:0] reg_stage6_cas_solution_c_l75_c9_1b24_a;
  wire [7:0] reg_stage7_cas_solution_c_l75_c9_1b24_a;
  output [7:0] return_output;
  wire [7:0] return_output;
  input [39:0] window;
  wire [39:0] window;
  always @(posedge clk)
    _16_ <= comb_stage0_cas_solution_c_l73_c9_dbdc_b;
  always @(posedge clk)
    _17_ <= comb_stage1_cas_solution_c_l73_c9_dbdc_b;
  always @(posedge clk)
    _18_ <= comb_stage2_cas_solution_c_l73_c9_dbdc_b;
  always @(posedge clk)
    _19_ <= comb_stage3_cas_solution_c_l73_c9_dbdc_b;
  always @(posedge clk)
    _20_ <= comb_stage6_cas_solution_c_l75_c9_1b24_a;
  always @(posedge clk)
    _21_ <= comb_stage7_cas_solution_c_l75_c9_1b24_a;
  cas_2clk_50f68833 cas_solution_c_l64_c9_d58e (
    .a(cas_solution_c_l64_c9_d58e_a),
    .b(cas_solution_c_l64_c9_d58e_b),
    .clk(clk),
    .\return_output[l] (_00_),
    .\return_output[r] (_01_)
  );
  cas_2clk_50f68833 cas_solution_c_l65_c9_6264 (
    .a(cas_solution_c_l65_c9_6264_a),
    .b(cas_solution_c_l65_c9_6264_b),
    .clk(clk),
    .\return_output[l] (_02_),
    .\return_output[r] (_03_)
  );
  cas_2clk_70ef9970 cas_solution_c_l67_c9_abd1 (
    .a(cas_solution_c_l67_c9_abd1_a),
    .b(cas_solution_c_l67_c9_abd1_b),
    .clk(clk),
    .\return_output[l] (_04_),
    .\return_output[r] (_05_)
  );
  cas_2clk_70ef9970 cas_solution_c_l68_c9_6d9c (
    .a(cas_solution_c_l68_c9_6d9c_a),
    .b(cas_solution_c_l68_c9_6d9c_b),
    .clk(clk),
    .\return_output[l] (_06_),
    .\return_output[r] (_07_)
  );
  cas_2clk_4973135e cas_solution_c_l70_c9_9b28 (
    .a(cas_solution_c_l70_c9_9b28_a),
    .b(cas_solution_c_l70_c9_9b28_b),
    .clk(clk),
    .\return_output[l] (_08_),
    .\return_output[r] (_09_)
  );
  cas_2clk_4973135e cas_solution_c_l73_c9_dbdc (
    .a(cas_solution_c_l73_c9_dbdc_a),
    .b(cas_solution_c_l73_c9_dbdc_b),
    .clk(clk),
    .\return_output[l] (_10_),
    .\return_output[r] (_11_)
  );
  cas_2clk_247944ad cas_solution_c_l74_c9_d2b4 (
    .a(cas_solution_c_l74_c9_d2b4_a),
    .b(cas_solution_c_l74_c9_d2b4_b),
    .clk(clk),
    .\return_output[l] (_12_),
    .\return_output[r] (_13_)
  );
  cas_1clk_ae17090d cas_solution_c_l75_c9_1b24 (
    .a(cas_solution_c_l75_c9_1b24_a),
    .b(cas_solution_c_l75_c9_1b24_b),
    .clk(clk),
    .\return_output[l] (_14_),
    .\return_output[r] (_15_)
  );
  assign reg_stage0_cas_solution_c_l73_c9_dbdc_b = _16_;
  assign comb_stage0_cas_solution_c_l73_c9_dbdc_b = window[7:0];
  assign reg_stage1_cas_solution_c_l73_c9_dbdc_b = _17_;
  assign comb_stage1_cas_solution_c_l73_c9_dbdc_b = reg_stage0_cas_solution_c_l73_c9_dbdc_b;
  assign reg_stage2_cas_solution_c_l73_c9_dbdc_b = _18_;
  assign comb_stage2_cas_solution_c_l73_c9_dbdc_b = reg_stage1_cas_solution_c_l73_c9_dbdc_b;
  assign reg_stage3_cas_solution_c_l73_c9_dbdc_b = _19_;
  assign comb_stage3_cas_solution_c_l73_c9_dbdc_b = reg_stage2_cas_solution_c_l73_c9_dbdc_b;
  assign reg_stage6_cas_solution_c_l75_c9_1b24_a = _20_;
  assign comb_stage6_cas_solution_c_l75_c9_1b24_a = cas_solution_c_l70_c9_9b28_return_output[15:8];
  assign reg_stage7_cas_solution_c_l75_c9_1b24_a = _21_;
  assign comb_stage7_cas_solution_c_l75_c9_1b24_a = reg_stage6_cas_solution_c_l75_c9_1b24_a;
  assign cas_solution_c_l64_c9_d58e_a = window[39:32];
  assign cas_solution_c_l64_c9_d58e_b = window[31:24];
  assign cas_solution_c_l64_c9_d58e_return_output = { _01_, _00_ };
  assign cas_solution_c_l65_c9_6264_a = window[23:16];
  assign cas_solution_c_l65_c9_6264_b = window[15:8];
  assign cas_solution_c_l65_c9_6264_return_output = { _03_, _02_ };
  assign cas_solution_c_l67_c9_abd1_a = cas_solution_c_l64_c9_d58e_return_output[7:0];
  assign cas_solution_c_l67_c9_abd1_b = cas_solution_c_l65_c9_6264_return_output[7:0];
  assign cas_solution_c_l67_c9_abd1_return_output = { _05_, _04_ };
  assign cas_solution_c_l68_c9_6d9c_a = cas_solution_c_l64_c9_d58e_return_output[15:8];
  assign cas_solution_c_l68_c9_6d9c_b = cas_solution_c_l65_c9_6264_return_output[15:8];
  assign cas_solution_c_l68_c9_6d9c_return_output = { _07_, _06_ };
  assign cas_solution_c_l70_c9_9b28_a = cas_solution_c_l68_c9_6d9c_return_output[7:0];
  assign cas_solution_c_l70_c9_9b28_b = cas_solution_c_l67_c9_abd1_return_output[15:8];
  assign cas_solution_c_l70_c9_9b28_return_output = { _09_, _08_ };
  assign cas_solution_c_l73_c9_dbdc_a = cas_solution_c_l67_c9_abd1_return_output[7:0];
  assign cas_solution_c_l73_c9_dbdc_b = reg_stage3_cas_solution_c_l73_c9_dbdc_b;
  assign cas_solution_c_l73_c9_dbdc_return_output = { _11_, _10_ };
  assign cas_solution_c_l74_c9_d2b4_a = cas_solution_c_l70_c9_9b28_return_output[7:0];
  assign cas_solution_c_l74_c9_d2b4_b = cas_solution_c_l73_c9_dbdc_return_output[15:8];
  assign cas_solution_c_l74_c9_d2b4_return_output = { _13_, _12_ };
  assign cas_solution_c_l75_c9_1b24_a = reg_stage7_cas_solution_c_l75_c9_1b24_a;
  assign cas_solution_c_l75_c9_1b24_b = cas_solution_c_l74_c9_d2b4_return_output[15:8];
  assign cas_solution_c_l75_c9_1b24_return_output = { _15_, _14_ };
  assign return_output = cas_solution_c_l75_c9_1b24_return_output[7:0];
endmodule

module const_sl_1_uint5_t_0clk_de264c78(x, return_output);
  wire [4:0] _0_;
  wire [9:0] \:427.read_pipe ;
  output [4:0] return_output;
  wire [4:0] return_output;
  input [4:0] x;
  wire [4:0] x;
  assign _0_ = x << 31'h00000001;
  assign \:427.read_pipe  = { 5'hxx, x };
  assign return_output = _0_;
endmodule

module mux_uint1_t_uint1_t_uint1_t_0clk_de264c78(cond, iftrue, iffalse, return_output);
  wire _0_;
  wire _1_;
  wire [3:0] \:384.read_pipe ;
  input cond;
  wire cond;
  input iffalse;
  wire iffalse;
  input iftrue;
  wire iftrue;
  output return_output;
  wire return_output;
  assign _0_ = cond == 1'h1;
  assign _1_ = _0_ ? iftrue : iffalse;
  assign \:384.read_pipe  = { iffalse, iftrue, cond, 1'hx };
  assign return_output = _1_;
endmodule

module mux_uint1_t_uint5_t_uint5_t_0clk_de264c78(cond, iftrue, iffalse, return_output);
  wire _0_;
  wire [4:0] _1_;
  wire [15:0] \:362.read_pipe ;
  input cond;
  wire cond;
  input [4:0] iffalse;
  wire [4:0] iffalse;
  input [4:0] iftrue;
  wire [4:0] iftrue;
  output [4:0] return_output;
  wire [4:0] return_output;
  assign _0_ = cond == 1'h1;
  assign _1_ = _0_ ? iftrue : iffalse;
  assign \:362.read_pipe  = { iffalse, iftrue, cond, 5'hxx };
  assign return_output = _1_;
endmodule

module mux_uint1_t_uint8_t_5_uint8_t_5_0clk_de264c78(cond, iftrue, iffalse, return_output);
  wire _0_;
  wire [39:0] _1_;
  wire [120:0] \:446.read_pipe ;
  input cond;
  wire cond;
  input [39:0] iffalse;
  wire [39:0] iffalse;
  input [39:0] iftrue;
  wire [39:0] iftrue;
  output [39:0] return_output;
  wire [39:0] return_output;
  assign _0_ = cond == 1'h1;
  assign _1_ = _0_ ? iftrue : iffalse;
  assign \:446.read_pipe  = { iffalse, iftrue, cond, 40'hxxxxxxxxxx };
  assign return_output = _1_;
endmodule

module mux_uint1_t_uint8_t_uint8_t_0clk_de264c78(cond, iftrue, iffalse, return_output);
  wire _0_;
  wire [7:0] _1_;
  wire [24:0] \:1024.read_pipe ;
  input cond;
  wire cond;
  input [7:0] iffalse;
  wire [7:0] iffalse;
  input [7:0] iftrue;
  wire [7:0] iftrue;
  output [7:0] return_output;
  wire [7:0] return_output;
  assign _0_ = cond == 1'h1;
  assign _1_ = _0_ ? iftrue : iffalse;
  assign \:1024.read_pipe  = { iffalse, iftrue, cond, 8'hxx };
  assign return_output = _1_;
endmodule

module mux_uint1_t_uint8_t_uint8_t_1clk_46dc7b5a(clk, cond, iftrue, iffalse, return_output);
  wire _0_;
  wire [7:0] _1_;
  reg [49:0] _2_;
  wire [24:0] \:950.read_pipe ;
  input clk;
  wire clk;
  input cond;
  wire cond;
  input [7:0] iffalse;
  wire [7:0] iffalse;
  input [7:0] iftrue;
  wire [7:0] iftrue;
  wire [49:0] manual_registers;
  wire [49:0] manual_registers_r;
  output [7:0] return_output;
  wire [7:0] return_output;
  assign _0_ = cond == 1'h1;
  assign _1_ = _0_ ? iftrue : iffalse;
  always @(posedge clk)
    _2_ <= manual_registers;
  assign manual_registers = { iffalse, iftrue, cond, _1_, manual_registers_r[49:25] };
  assign manual_registers_r = _2_;
  assign \:950.read_pipe  = manual_registers_r[49:25];
  assign return_output = manual_registers_r[32:25];
endmodule

module mux_uint1_t_uint8_t_uint8_t_1clk_56fb9438(clk, cond, iftrue, iffalse, return_output);
  wire _0_;
  wire [7:0] _1_;
  reg [49:0] _2_;
  wire [24:0] \:800.read_pipe ;
  input clk;
  wire clk;
  input cond;
  wire cond;
  input [7:0] iffalse;
  wire [7:0] iffalse;
  input [7:0] iftrue;
  wire [7:0] iftrue;
  wire [49:0] manual_registers;
  wire [49:0] manual_registers_r;
  output [7:0] return_output;
  wire [7:0] return_output;
  assign _0_ = cond == 1'h1;
  assign _1_ = _0_ ? iftrue : iffalse;
  always @(posedge clk)
    _2_ <= manual_registers;
  assign manual_registers = { iffalse, iftrue, cond, _1_, manual_registers_r[49:25] };
  assign manual_registers_r = _2_;
  assign \:800.read_pipe  = manual_registers_r[49:25];
  assign return_output = manual_registers_r[32:25];
endmodule

module mux_uint1_t_uint8_t_uint8_t_1clk_76079683(clk, cond, iftrue, iffalse, return_output);
  wire _0_;
  wire [7:0] _1_;
  reg [49:0] _2_;
  wire [24:0] \:875.read_pipe ;
  input clk;
  wire clk;
  input cond;
  wire cond;
  input [7:0] iffalse;
  wire [7:0] iffalse;
  input [7:0] iftrue;
  wire [7:0] iftrue;
  wire [49:0] manual_registers;
  wire [49:0] manual_registers_r;
  output [7:0] return_output;
  wire [7:0] return_output;
  assign _0_ = cond == 1'h1;
  assign _1_ = _0_ ? iftrue : iffalse;
  always @(posedge clk)
    _2_ <= manual_registers;
  assign manual_registers = { iffalse, iftrue, cond, _1_, manual_registers_r[49:25] };
  assign manual_registers_r = _2_;
  assign \:875.read_pipe  = manual_registers_r[49:25];
  assign return_output = manual_registers_r[32:25];
endmodule

module mux_uint1_t_uint8_t_uint8_t_1clk_93a40912(clk, cond, iftrue, iffalse, return_output);
  wire _0_;
  wire [7:0] _1_;
  reg [49:0] _2_;
  wire [24:0] \:724.read_pipe ;
  input clk;
  wire clk;
  input cond;
  wire cond;
  input [7:0] iffalse;
  wire [7:0] iffalse;
  input [7:0] iftrue;
  wire [7:0] iftrue;
  wire [49:0] manual_registers;
  wire [49:0] manual_registers_r;
  output [7:0] return_output;
  wire [7:0] return_output;
  assign _0_ = manual_registers_r[33] == 1'h1;
  assign _1_ = _0_ ? manual_registers_r[41:34] : manual_registers_r[49:42];
  always @(posedge clk)
    _2_ <= manual_registers;
  assign manual_registers = { iffalse, iftrue, cond, \:724.read_pipe [7:0], manual_registers_r[49:33], _1_ };
  assign manual_registers_r = _2_;
  assign \:724.read_pipe  = manual_registers_r[49:25];
  assign return_output = _1_;
endmodule

module sliding_window_1clk_f72c93dd(clk, clock_enable, data_in, valid, last, \return_output[data] , \return_output[valid] , \return_output[last] );
  wire [4:0] _00_;
  wire _01_;
  wire _02_;
  wire [4:0] _03_;
  wire [4:0] _04_;
  wire [4:0] _05_;
  wire [39:0] _06_;
  wire [39:0] _07_;
  reg [39:0] _08_ = 40'h0000000000;
  wire [4:0] _09_;
  reg [4:0] _10_ = 5'h01;
  reg [41:0] _11_ = 42'h00000000000;
  input clk;
  wire clk;
  wire clk_en_internal;
  input clock_enable;
  wire clock_enable;
  wire [4:0] const_sl_1_solution_c_l98_c28_f70b_return_output;
  wire [4:0] const_sl_1_solution_c_l98_c28_f70b_x;
  wire [39:0] data;
  input [7:0] data_in;
  wire [7:0] data_in;
  wire [41:0] io_registers;
  wire [41:0] io_registers_r;
  input last;
  wire last;
  wire mux_uint1_t_uint8_t_5_uint8_t_5_solution_c_l95_c3_f8af_duplicate_2611_cond;
  wire [39:0] mux_uint1_t_uint8_t_5_uint8_t_5_solution_c_l95_c3_f8af_duplicate_2611_iffalse;
  wire [39:0] mux_uint1_t_uint8_t_5_uint8_t_5_solution_c_l95_c3_f8af_duplicate_2611_iftrue;
  wire [39:0] mux_uint1_t_uint8_t_5_uint8_t_5_solution_c_l95_c3_f8af_duplicate_2611_return_output;
  wire [39:0] reg_comb_data;
  wire [4:0] reg_comb_saw_five_elements_one_hot_counter;
  output [39:0] \return_output[data] ;
  wire [39:0] \return_output[data] ;
  output \return_output[last] ;
  wire \return_output[last] ;
  output \return_output[valid] ;
  wire \return_output[valid] ;
  wire rv_valid_mux_solution_c_l95_c3_f8af_cond;
  wire rv_valid_mux_solution_c_l95_c3_f8af_iffalse;
  wire rv_valid_mux_solution_c_l95_c3_f8af_iftrue;
  wire rv_valid_mux_solution_c_l95_c3_f8af_return_output;
  wire [4:0] saw_five_elements_one_hot_counter;
  wire saw_five_elements_one_hot_counter_mux_solution_c_l100_c5_4ba7_cond;
  wire [4:0] saw_five_elements_one_hot_counter_mux_solution_c_l100_c5_4ba7_iffalse;
  wire [4:0] saw_five_elements_one_hot_counter_mux_solution_c_l100_c5_4ba7_iftrue;
  wire [4:0] saw_five_elements_one_hot_counter_mux_solution_c_l100_c5_4ba7_return_output;
  wire saw_five_elements_one_hot_counter_mux_solution_c_l95_c3_f8af_cond;
  wire [4:0] saw_five_elements_one_hot_counter_mux_solution_c_l95_c3_f8af_iffalse;
  wire [4:0] saw_five_elements_one_hot_counter_mux_solution_c_l95_c3_f8af_iftrue;
  wire [4:0] saw_five_elements_one_hot_counter_mux_solution_c_l95_c3_f8af_return_output;
  wire saw_five_elements_one_hot_counter_mux_solution_c_l98_c5_7ee2_cond;
  wire [4:0] saw_five_elements_one_hot_counter_mux_solution_c_l98_c5_7ee2_iffalse;
  wire [4:0] saw_five_elements_one_hot_counter_mux_solution_c_l98_c5_7ee2_iftrue;
  wire [4:0] saw_five_elements_one_hot_counter_mux_solution_c_l98_c5_7ee2_return_output;
  wire unary_op_not_solution_c_l98_c9_8daf_expr;
  wire unary_op_not_solution_c_l98_c9_8daf_return_output;
  input valid;
  wire valid;
  assign _07_ = clk_en_internal ? reg_comb_data : data;
  always @(posedge clk)
    _08_ <= _07_;
  assign _09_ = clk_en_internal ? reg_comb_saw_five_elements_one_hot_counter : saw_five_elements_one_hot_counter;
  always @(posedge clk)
    _10_ <= _09_;
  always @(posedge clk)
    _11_ <= io_registers;
  const_sl_1_uint5_t_0clk_de264c78 const_sl_1_solution_c_l98_c28_f70b (
    .return_output(_04_),
    .x(const_sl_1_solution_c_l98_c28_f70b_x)
  );
  mux_uint1_t_uint8_t_5_uint8_t_5_0clk_de264c78 mux_uint1_t_uint8_t_5_uint8_t_5_solution_c_l95_c3_f8af_duplicate_2611 (
    .cond(mux_uint1_t_uint8_t_5_uint8_t_5_solution_c_l95_c3_f8af_duplicate_2611_cond),
    .iffalse(mux_uint1_t_uint8_t_5_uint8_t_5_solution_c_l95_c3_f8af_duplicate_2611_iffalse),
    .iftrue(mux_uint1_t_uint8_t_5_uint8_t_5_solution_c_l95_c3_f8af_duplicate_2611_iftrue),
    .return_output(_06_)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 rv_valid_mux_solution_c_l95_c3_f8af (
    .cond(rv_valid_mux_solution_c_l95_c3_f8af_cond),
    .iffalse(rv_valid_mux_solution_c_l95_c3_f8af_iffalse),
    .iftrue(rv_valid_mux_solution_c_l95_c3_f8af_iftrue),
    .return_output(_01_)
  );
  mux_uint1_t_uint5_t_uint5_t_0clk_de264c78 saw_five_elements_one_hot_counter_mux_solution_c_l100_c5_4ba7 (
    .cond(saw_five_elements_one_hot_counter_mux_solution_c_l100_c5_4ba7_cond),
    .iffalse(saw_five_elements_one_hot_counter_mux_solution_c_l100_c5_4ba7_iffalse),
    .iftrue(saw_five_elements_one_hot_counter_mux_solution_c_l100_c5_4ba7_iftrue),
    .return_output(_05_)
  );
  mux_uint1_t_uint5_t_uint5_t_0clk_de264c78 saw_five_elements_one_hot_counter_mux_solution_c_l95_c3_f8af (
    .cond(saw_five_elements_one_hot_counter_mux_solution_c_l95_c3_f8af_cond),
    .iffalse(saw_five_elements_one_hot_counter_mux_solution_c_l95_c3_f8af_iffalse),
    .iftrue(saw_five_elements_one_hot_counter_mux_solution_c_l95_c3_f8af_iftrue),
    .return_output(_00_)
  );
  mux_uint1_t_uint5_t_uint5_t_0clk_de264c78 saw_five_elements_one_hot_counter_mux_solution_c_l98_c5_7ee2 (
    .cond(saw_five_elements_one_hot_counter_mux_solution_c_l98_c5_7ee2_cond),
    .iffalse(saw_five_elements_one_hot_counter_mux_solution_c_l98_c5_7ee2_iffalse),
    .iftrue(saw_five_elements_one_hot_counter_mux_solution_c_l98_c5_7ee2_iftrue),
    .return_output(_03_)
  );
  unary_op_not_uint1_t_0clk_de264c78 unary_op_not_solution_c_l98_c9_8daf (
    .expr(unary_op_not_solution_c_l98_c9_8daf_expr),
    .return_output(_02_)
  );
  assign data = _08_;
  assign saw_five_elements_one_hot_counter = _10_;
  assign reg_comb_data = mux_uint1_t_uint8_t_5_uint8_t_5_solution_c_l95_c3_f8af_duplicate_2611_return_output;
  assign reg_comb_saw_five_elements_one_hot_counter = saw_five_elements_one_hot_counter_mux_solution_c_l95_c3_f8af_return_output;
  assign clk_en_internal = clock_enable;
  assign io_registers = { last, rv_valid_mux_solution_c_l95_c3_f8af_return_output, mux_uint1_t_uint8_t_5_uint8_t_5_solution_c_l95_c3_f8af_duplicate_2611_return_output };
  assign io_registers_r = _11_;
  assign saw_five_elements_one_hot_counter_mux_solution_c_l95_c3_f8af_cond = valid;
  assign saw_five_elements_one_hot_counter_mux_solution_c_l95_c3_f8af_iftrue = saw_five_elements_one_hot_counter_mux_solution_c_l100_c5_4ba7_return_output;
  assign saw_five_elements_one_hot_counter_mux_solution_c_l95_c3_f8af_iffalse = saw_five_elements_one_hot_counter;
  assign saw_five_elements_one_hot_counter_mux_solution_c_l95_c3_f8af_return_output = _00_;
  assign rv_valid_mux_solution_c_l95_c3_f8af_cond = valid;
  assign rv_valid_mux_solution_c_l95_c3_f8af_iftrue = saw_five_elements_one_hot_counter[4];
  assign rv_valid_mux_solution_c_l95_c3_f8af_iffalse = 1'h0;
  assign rv_valid_mux_solution_c_l95_c3_f8af_return_output = _01_;
  assign unary_op_not_solution_c_l98_c9_8daf_expr = saw_five_elements_one_hot_counter[4];
  assign unary_op_not_solution_c_l98_c9_8daf_return_output = _02_;
  assign saw_five_elements_one_hot_counter_mux_solution_c_l98_c5_7ee2_cond = unary_op_not_solution_c_l98_c9_8daf_return_output;
  assign saw_five_elements_one_hot_counter_mux_solution_c_l98_c5_7ee2_iftrue = const_sl_1_solution_c_l98_c28_f70b_return_output;
  assign saw_five_elements_one_hot_counter_mux_solution_c_l98_c5_7ee2_iffalse = saw_five_elements_one_hot_counter;
  assign saw_five_elements_one_hot_counter_mux_solution_c_l98_c5_7ee2_return_output = _03_;
  assign const_sl_1_solution_c_l98_c28_f70b_x = saw_five_elements_one_hot_counter;
  assign const_sl_1_solution_c_l98_c28_f70b_return_output = _04_;
  assign saw_five_elements_one_hot_counter_mux_solution_c_l100_c5_4ba7_cond = last;
  assign saw_five_elements_one_hot_counter_mux_solution_c_l100_c5_4ba7_iftrue = 5'h01;
  assign saw_five_elements_one_hot_counter_mux_solution_c_l100_c5_4ba7_iffalse = saw_five_elements_one_hot_counter_mux_solution_c_l98_c5_7ee2_return_output;
  assign saw_five_elements_one_hot_counter_mux_solution_c_l100_c5_4ba7_return_output = _05_;
  assign mux_uint1_t_uint8_t_5_uint8_t_5_solution_c_l95_c3_f8af_duplicate_2611_cond = valid;
  assign mux_uint1_t_uint8_t_5_uint8_t_5_solution_c_l95_c3_f8af_duplicate_2611_iftrue = { data[31:0], data_in };
  assign mux_uint1_t_uint8_t_5_uint8_t_5_solution_c_l95_c3_f8af_duplicate_2611_iffalse = data;
  assign mux_uint1_t_uint8_t_5_uint8_t_5_solution_c_l95_c3_f8af_duplicate_2611_return_output = _06_;
  assign \return_output[data]  = io_registers_r[39:0];
  assign \return_output[valid]  = io_registers_r[40];
  assign \return_output[last]  = io_registers_r[41];
endmodule

module solution(\input[data] , \input[valid] , clk, input_ready, \output[data] , \output[valid] );
  wire [9:0] _0_;
  wire _1_;
  input clk;
  wire clk;
  (* dont_touch = "true" *)
  (* keep = "true" *)
  (* syn_keep = 1'h1 *)
  wire clk_335p0;
  wire [9:0] global_to_module;
  input [8:0] \input[data] ;
  wire [8:0] \input[data] ;
  input \input[valid] ;
  wire \input[valid] ;
  output input_ready;
  wire input_ready;
  wire [10:0] module_to_global;
  output [8:0] \output[data] ;
  wire [8:0] \output[data] ;
  output \output[valid] ;
  wire \output[valid] ;
  solution_10clk_fe434456 solution_10clk_fe434456 (
    .clk(clk_335p0),
    .clock_enable(1'h1),
    .\global_to_module[input] (global_to_module),
    .\module_to_global[input_ready] (_1_),
    .\module_to_global[output] (_0_)
  );
  assign clk_335p0 = clk;
  assign module_to_global = { _1_, _0_ };
  assign global_to_module = { \input[valid] , \input[data]  };
  assign input_ready = module_to_global[10];
  assign \output[data]  = module_to_global[8:0];
  assign \output[valid]  = module_to_global[9];
endmodule

module solution_10clk_fe434456(clk, clock_enable, \global_to_module[input] , \module_to_global[output] , \module_to_global[input_ready] );
  reg _00_;
  wire _01_;
  reg _02_;
  wire _03_;
  reg _04_;
  wire _05_;
  reg _06_;
  wire _07_;
  reg _08_;
  wire _09_;
  reg _10_;
  wire _11_;
  reg _12_;
  wire _13_;
  reg _14_;
  wire _15_;
  reg _16_;
  wire _17_;
  reg _18_;
  wire _19_;
  wire [39:0] _20_;
  reg _21_;
  wire _22_;
  reg _23_;
  wire _24_;
  reg _25_;
  wire _26_;
  reg _27_;
  wire _28_;
  reg _29_;
  wire _30_;
  wire _31_;
  reg _32_;
  wire _33_;
  reg _34_;
  wire _35_;
  reg _36_;
  wire _37_;
  wire [7:0] _38_;
  wire [9:0] _39_;
  wire _40_;
  wire _41_;
  wire [7:0] claude_median_solution_c_l108_c26_e0b4_return_output;
  wire [39:0] claude_median_solution_c_l108_c26_e0b4_window;
  input clk;
  wire clk;
  wire clk_en_internal;
  input clock_enable;
  wire clock_enable;
  wire comb_stage1_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  wire comb_stage1_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  wire comb_stage2_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  wire comb_stage2_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  wire comb_stage3_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  wire comb_stage3_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  wire comb_stage4_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  wire comb_stage4_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  wire comb_stage5_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  wire comb_stage5_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  wire comb_stage6_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  wire comb_stage6_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  wire comb_stage7_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  wire comb_stage7_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  wire comb_stage8_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  wire comb_stage8_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  wire comb_stage9_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  wire comb_stage9_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  input [9:0] \global_to_module[input] ;
  wire [9:0] \global_to_module[input] ;
  output \module_to_global[input_ready] ;
  wire \module_to_global[input_ready] ;
  output [9:0] \module_to_global[output] ;
  wire [9:0] \module_to_global[output] ;
  wire reg_stage1_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  wire reg_stage1_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  wire reg_stage2_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  wire reg_stage2_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  wire reg_stage3_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  wire reg_stage3_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  wire reg_stage4_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  wire reg_stage4_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  wire reg_stage5_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  wire reg_stage5_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  wire reg_stage6_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  wire reg_stage6_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  wire reg_stage7_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  wire reg_stage7_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  wire reg_stage8_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  wire reg_stage8_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  wire reg_stage9_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  wire reg_stage9_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  wire sliding_window_solution_c_l107_c16_cf8c_clock_enable;
  wire [7:0] sliding_window_solution_c_l107_c16_cf8c_data_in;
  wire sliding_window_solution_c_l107_c16_cf8c_last;
  wire [41:0] sliding_window_solution_c_l107_c16_cf8c_return_output;
  wire sliding_window_solution_c_l107_c16_cf8c_valid;
  assign _41_ = clk_en_internal ? comb_stage1_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output : reg_stage1_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  always @(posedge clk)
    _00_ <= _41_;
  assign _01_ = clk_en_internal ? comb_stage1_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output : reg_stage1_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  always @(posedge clk)
    _02_ <= _01_;
  assign _03_ = clk_en_internal ? comb_stage2_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output : reg_stage2_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  always @(posedge clk)
    _04_ <= _03_;
  assign _05_ = clk_en_internal ? comb_stage2_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output : reg_stage2_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  always @(posedge clk)
    _06_ <= _05_;
  assign _07_ = clk_en_internal ? comb_stage3_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output : reg_stage3_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  always @(posedge clk)
    _08_ <= _07_;
  assign _09_ = clk_en_internal ? comb_stage3_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output : reg_stage3_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  always @(posedge clk)
    _10_ <= _09_;
  assign _11_ = clk_en_internal ? comb_stage4_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output : reg_stage4_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  always @(posedge clk)
    _12_ <= _11_;
  assign _13_ = clk_en_internal ? comb_stage4_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output : reg_stage4_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  always @(posedge clk)
    _14_ <= _13_;
  assign _15_ = clk_en_internal ? comb_stage5_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output : reg_stage5_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  always @(posedge clk)
    _16_ <= _15_;
  assign _17_ = clk_en_internal ? comb_stage5_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output : reg_stage5_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  always @(posedge clk)
    _18_ <= _17_;
  assign _19_ = clk_en_internal ? comb_stage6_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output : reg_stage6_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  always @(posedge clk)
    _21_ <= _19_;
  assign _22_ = clk_en_internal ? comb_stage6_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output : reg_stage6_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  always @(posedge clk)
    _23_ <= _22_;
  assign _24_ = clk_en_internal ? comb_stage7_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output : reg_stage7_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  always @(posedge clk)
    _25_ <= _24_;
  assign _26_ = clk_en_internal ? comb_stage7_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output : reg_stage7_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  always @(posedge clk)
    _27_ <= _26_;
  assign _28_ = clk_en_internal ? comb_stage8_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output : reg_stage8_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  always @(posedge clk)
    _29_ <= _28_;
  assign _30_ = clk_en_internal ? comb_stage8_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output : reg_stage8_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  always @(posedge clk)
    _32_ <= _30_;
  assign _33_ = clk_en_internal ? comb_stage9_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output : reg_stage9_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  always @(posedge clk)
    _34_ <= _33_;
  assign _35_ = clk_en_internal ? comb_stage9_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output : reg_stage9_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  always @(posedge clk)
    _36_ <= _35_;
  assign _39_ = clk_en_internal ? { reg_stage9_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output, reg_stage9_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output, claude_median_solution_c_l108_c26_e0b4_return_output } : 10'h000;
  assign _40_ = clk_en_internal ? 1'h1 : 1'h0;
  claude_median_9clk_c433c9d8 claude_median_solution_c_l108_c26_e0b4 (
    .clk(clk),
    .return_output(_38_),
    .window(claude_median_solution_c_l108_c26_e0b4_window)
  );
  sliding_window_1clk_f72c93dd sliding_window_solution_c_l107_c16_cf8c (
    .clk(clk),
    .clock_enable(sliding_window_solution_c_l107_c16_cf8c_clock_enable),
    .data_in(sliding_window_solution_c_l107_c16_cf8c_data_in),
    .last(sliding_window_solution_c_l107_c16_cf8c_last),
    .\return_output[data] (_20_),
    .\return_output[last] (_37_),
    .\return_output[valid] (_31_),
    .valid(sliding_window_solution_c_l107_c16_cf8c_valid)
  );
  assign reg_stage1_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output = _00_;
  assign reg_stage1_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output = _02_;
  assign comb_stage1_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output = sliding_window_solution_c_l107_c16_cf8c_return_output[41];
  assign comb_stage1_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output = sliding_window_solution_c_l107_c16_cf8c_return_output[40];
  assign reg_stage2_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output = _04_;
  assign reg_stage2_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output = _06_;
  assign comb_stage2_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output = reg_stage1_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  assign comb_stage2_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output = reg_stage1_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  assign reg_stage3_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output = _08_;
  assign reg_stage3_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output = _10_;
  assign comb_stage3_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output = reg_stage2_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  assign comb_stage3_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output = reg_stage2_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  assign reg_stage4_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output = _12_;
  assign reg_stage4_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output = _14_;
  assign comb_stage4_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output = reg_stage3_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  assign comb_stage4_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output = reg_stage3_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  assign reg_stage5_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output = _16_;
  assign reg_stage5_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output = _18_;
  assign comb_stage5_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output = reg_stage4_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  assign comb_stage5_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output = reg_stage4_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  assign reg_stage6_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output = _21_;
  assign reg_stage6_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output = _23_;
  assign comb_stage6_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output = reg_stage5_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  assign comb_stage6_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output = reg_stage5_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  assign reg_stage7_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output = _25_;
  assign reg_stage7_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output = _27_;
  assign comb_stage7_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output = reg_stage6_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  assign comb_stage7_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output = reg_stage6_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  assign reg_stage8_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output = _29_;
  assign reg_stage8_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output = _32_;
  assign comb_stage8_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output = reg_stage7_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  assign comb_stage8_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output = reg_stage7_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  assign reg_stage9_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output = _34_;
  assign reg_stage9_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output = _36_;
  assign comb_stage9_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output = reg_stage8_const_ref_rd_uint1_t_window_t_last_d41d_solution_c_l109_c22_cab5_return_output;
  assign comb_stage9_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output = reg_stage8_const_ref_rd_uint1_t_window_t_valid_d41d_solution_c_l110_c18_8da5_return_output;
  assign clk_en_internal = clock_enable;
  assign sliding_window_solution_c_l107_c16_cf8c_clock_enable = clk_en_internal;
  assign sliding_window_solution_c_l107_c16_cf8c_data_in = \global_to_module[input] [7:0];
  assign sliding_window_solution_c_l107_c16_cf8c_valid = \global_to_module[input] [9];
  assign sliding_window_solution_c_l107_c16_cf8c_last = \global_to_module[input] [8];
  assign sliding_window_solution_c_l107_c16_cf8c_return_output = { _37_, _31_, _20_ };
  assign claude_median_solution_c_l108_c26_e0b4_window = sliding_window_solution_c_l107_c16_cf8c_return_output[39:0];
  assign claude_median_solution_c_l108_c26_e0b4_return_output = _38_;
  assign \module_to_global[output]  = _39_;
  assign \module_to_global[input_ready]  = _40_;
endmodule

module unary_op_not_uint1_t_0clk_de264c78(expr, return_output);
  wire _0_;
  wire [2:0] \:406.read_pipe ;
  input expr;
  wire expr;
  output return_output;
  wire return_output;
  assign _0_ = ~ expr;
  assign \:406.read_pipe  = { expr, 2'hx };
  assign return_output = _0_;
endmodule

Timing Analysis

Path 1-4.324 ns

From:

inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/_4_[166]$_DFF_P_/Q

To: o_payload_fragment[0]

Data Arrival: 4.325 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/_4_[166]$_DFF_P_/CLK`
0.677	sky130_fd_sc_hvl__dfxtp_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/_4_[166]$_DFF_P_/Q`
0.677	sky130_fd_sc_hvl__xor2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3067/A`
1.027	sky130_fd_sc_hvl__xor2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3067/X`
1.027	sky130_fd_sc_hvl__nor2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3068/B`
1.334	sky130_fd_sc_hvl__nor2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3068/Y`
1.334	sky130_fd_sc_hvl__nor3_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3072/C`
1.511	sky130_fd_sc_hvl__nor3_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3072/Y`
1.511	sky130_fd_sc_hvl__o21ai_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3075/A2`
1.858	sky130_fd_sc_hvl__o21ai_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3075/Y`
1.858	sky130_fd_sc_hvl__o21ai_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3081/A1`
2.094	sky130_fd_sc_hvl__o21ai_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3081/Y`
2.094	sky130_fd_sc_hvl__xnor2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3082/B`
3.236	sky130_fd_sc_hvl__xnor2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3082/Y`
3.236	sky130_fd_sc_hvl__mux2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/mux_solution_c_l46_c19_f623/$abc$3149$auto$blifparse.cc:396:parse_blif$3150/S`
4.054	sky130_fd_sc_hvl__mux2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/mux_solution_c_l46_c19_f623/$abc$3149$auto$blifparse.cc:396:parse_blif$3150/X`
4.054	sky130_fd_sc_hvl__and2_1	`inner/solution_10clk_fe434456/$abc$3241$auto$blifparse.cc:396:parse_blif$3269/B`
4.325	sky130_fd_sc_hvl__and2_1	`inner/solution_10clk_fe434456/$abc$3241$auto$blifparse.cc:396:parse_blif$3269/X`
4.325	Solution	`o_payload_fragment[0]`

Path 2-4.324 ns

From:

inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/_4_[166]$_DFF_P_/Q

To: o_payload_fragment[1]

Data Arrival: 4.325 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/_4_[166]$_DFF_P_/CLK`
0.677	sky130_fd_sc_hvl__dfxtp_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/_4_[166]$_DFF_P_/Q`
0.677	sky130_fd_sc_hvl__xor2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3067/A`
1.027	sky130_fd_sc_hvl__xor2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3067/X`
1.027	sky130_fd_sc_hvl__nor2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3068/B`
1.334	sky130_fd_sc_hvl__nor2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3068/Y`
1.334	sky130_fd_sc_hvl__nor3_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3072/C`
1.511	sky130_fd_sc_hvl__nor3_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3072/Y`
1.511	sky130_fd_sc_hvl__o21ai_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3075/A2`
1.858	sky130_fd_sc_hvl__o21ai_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3075/Y`
1.858	sky130_fd_sc_hvl__o21ai_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3081/A1`
2.094	sky130_fd_sc_hvl__o21ai_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3081/Y`
2.094	sky130_fd_sc_hvl__xnor2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3082/B`
3.236	sky130_fd_sc_hvl__xnor2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3082/Y`
3.236	sky130_fd_sc_hvl__mux2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/mux_solution_c_l46_c19_f623/$abc$3149$auto$blifparse.cc:396:parse_blif$3151/S`
4.054	sky130_fd_sc_hvl__mux2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/mux_solution_c_l46_c19_f623/$abc$3149$auto$blifparse.cc:396:parse_blif$3151/X`
4.054	sky130_fd_sc_hvl__and2_1	`inner/solution_10clk_fe434456/$abc$3241$auto$blifparse.cc:396:parse_blif$3243/B`
4.325	sky130_fd_sc_hvl__and2_1	`inner/solution_10clk_fe434456/$abc$3241$auto$blifparse.cc:396:parse_blif$3243/X`
4.325	Solution	`o_payload_fragment[1]`

Path 3-4.324 ns

From:

inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/_4_[166]$_DFF_P_/Q

To: o_payload_fragment[2]

Data Arrival: 4.325 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/_4_[166]$_DFF_P_/CLK`
0.677	sky130_fd_sc_hvl__dfxtp_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/_4_[166]$_DFF_P_/Q`
0.677	sky130_fd_sc_hvl__xor2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3067/A`
1.027	sky130_fd_sc_hvl__xor2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3067/X`
1.027	sky130_fd_sc_hvl__nor2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3068/B`
1.334	sky130_fd_sc_hvl__nor2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3068/Y`
1.334	sky130_fd_sc_hvl__nor3_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3072/C`
1.511	sky130_fd_sc_hvl__nor3_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3072/Y`
1.511	sky130_fd_sc_hvl__o21ai_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3075/A2`
1.858	sky130_fd_sc_hvl__o21ai_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3075/Y`
1.858	sky130_fd_sc_hvl__o21ai_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3081/A1`
2.094	sky130_fd_sc_hvl__o21ai_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3081/Y`
2.094	sky130_fd_sc_hvl__xnor2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3082/B`
3.236	sky130_fd_sc_hvl__xnor2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/bin_op_lt_uint8_t_uint8_t_solution_c_l46_l47_duplicate_d7e3/bin_op_minus_bin_op_lt_uint8_t_uint8_t_c_l14_c18_bee9/$abc$3043$auto$blifparse.cc:396:parse_blif$3082/Y`
3.236	sky130_fd_sc_hvl__mux2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/mux_solution_c_l46_c19_f623/$abc$3149$auto$blifparse.cc:396:parse_blif$3152/S`
4.054	sky130_fd_sc_hvl__mux2_1	`inner/solution_10clk_fe434456/claude_median_solution_c_l108_c26_e0b4/cas_solution_c_l75_c9_1b24/mux_solution_c_l46_c19_f623/$abc$3149$auto$blifparse.cc:396:parse_blif$3152/X`
4.054	sky130_fd_sc_hvl__and2_1	`inner/solution_10clk_fe434456/$abc$3241$auto$blifparse.cc:396:parse_blif$3244/B`
4.325	sky130_fd_sc_hvl__and2_1	`inner/solution_10clk_fe434456/$abc$3241$auto$blifparse.cc:396:parse_blif$3244/X`
4.325	Solution	`o_payload_fragment[2]`

Post-Synthesis Verilog

Download synth.v