Median Filter - Latchup

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Submission #1

PASSED

RankingPercentile

Latency

64.46 (18 cycles)ns

5th

top 17%

Max Frequency

279.25MHz

5th

top 17%

Area

4667μm²

6th

top 21%

Submitted Solution

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready, // sic
  input wire i_valid,
  input wire [8-1:0] i_payload_stream_fragment,
  input wire i_payload_stream_last,
  output wire [8-1:0] o_payload_fragment,
  output wire o_payload_last,
  output wire o_valid
);

// no idea if people will see this code.  if so, i'm sorry.
// i'm doing this for fun.
// try not to stare directly at the code

reg [31:0] srl;
wire [39:0] ext = {srl, i_payload_stream_fragment};

// input (0) compared to the four existing values.
wire c01 = i_payload_stream_fragment >= srl[8*0 +: 8];
wire c02 = i_payload_stream_fragment >= srl[8*1 +: 8];
wire c03 = i_payload_stream_fragment >= srl[8*2 +: 8];
wire c04 = i_payload_stream_fragment >= srl[8*3 +: 8];

reg c12 = 0;
reg c13 = 0;
reg c14 = 0;
reg c23 = 0;
reg c24 = 0;
reg c34 = 0;
  
reg [3:0] gate = 0;

always@(posedge clk) begin
  if (i_valid) begin
    srl <= ext[31:0]; // shift in
    // shift 
    c12 <= c01;
    c13 <= c02;
    c14 <= c03;
    // shift
    c23 <= c12;
    c24 <= c13;
    // shift
    c34 <= c23;
    
    // gating for valid/last.
    if (!i_payload_stream_last) begin
      gate <= {gate[2:0], 1'b1};
    end else begin
      gate <= 0;
    end
  end

  // hopefully sync?
  if (reset) begin
    gate <= 0;
  end
end

// winners.  due to compare, there will be 0,1,2,3,4 set.
// median will be 2.
wire [3:0] w0 = { c01,  c02,  c03,  c04};
wire [3:0] w1 = {~c01,  c12,  c13,  c14};
wire [3:0] w2 = {~c02, ~c12,  c23,  c24};
wire [3:0] w3 = {~c03, ~c13, ~c23,  c34};
wire [3:0] w4 = {~c04, ~c14, ~c24, ~c34};

// widemux select -- one of these will have exactly two bits set.
wire s0 = (w0 == 4'h3) || (w0 == 4'h5) || (w0 == 4'h9) || (w0 == 4'h6) || (w0 == 4'hA) || (w0 == 4'hC);
wire s1 = (w1 == 4'h3) || (w1 == 4'h5) || (w1 == 4'h9) || (w1 == 4'h6) || (w1 == 4'hA) || (w1 == 4'hC);
wire s2 = (w2 == 4'h3) || (w2 == 4'h5) || (w2 == 4'h9) || (w2 == 4'h6) || (w2 == 4'hA) || (w2 == 4'hC);
wire s3 = (w3 == 4'h3) || (w3 == 4'h5) || (w3 == 4'h9) || (w3 == 4'h6) || (w3 == 4'hA) || (w3 == 4'hC);
wire s4 = (w4 == 4'h3) || (w4 == 4'h5) || (w4 == 4'h9) || (w4 == 4'h6) || (w4 == 4'hA) || (w4 == 4'hC);

// widemux
wire [7:0] result = ({(8){s0}} & ext[8*0+:8])
                  | ({(8){s1}} & ext[8*1+:8])
                  | ({(8){s2}} & ext[8*2+:8])
                  | ({(8){s3}} & ext[8*3+:8])
                  | ({(8){s4}} & ext[8*4+:8]);


// this version has a combinatorial path
assign i_ready = !reset; // no backpressure.  could also be 1'b1 if the checker allows.
assign o_payload_fragment = result;  // not sure if the checker likes output regs
assign o_valid = i_valid && gate[3]; // min lat version
assign o_payload_last = i_payload_stream_last && gate[3]; // gated for best practice

endmodule

Generated Verilog

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready, // sic
  input wire i_valid,
  input wire [8-1:0] i_payload_stream_fragment,
  input wire i_payload_stream_last,
  output wire [8-1:0] o_payload_fragment,
  output wire o_payload_last,
  output wire o_valid
);

// no idea if people will see this code.  if so, i'm sorry.
// i'm doing this for fun.
// try not to stare directly at the code

reg [31:0] srl;
wire [39:0] ext = {srl, i_payload_stream_fragment};

// input (0) compared to the four existing values.
wire c01 = i_payload_stream_fragment >= srl[8*0 +: 8];
wire c02 = i_payload_stream_fragment >= srl[8*1 +: 8];
wire c03 = i_payload_stream_fragment >= srl[8*2 +: 8];
wire c04 = i_payload_stream_fragment >= srl[8*3 +: 8];

reg c12 = 0;
reg c13 = 0;
reg c14 = 0;
reg c23 = 0;
reg c24 = 0;
reg c34 = 0;
  
reg [3:0] gate = 0;

always@(posedge clk) begin
  if (i_valid) begin
    srl <= ext[31:0]; // shift in
    // shift 
    c12 <= c01;
    c13 <= c02;
    c14 <= c03;
    // shift
    c23 <= c12;
    c24 <= c13;
    // shift
    c34 <= c23;
    
    // gating for valid/last.
    if (!i_payload_stream_last) begin
      gate <= {gate[2:0], 1'b1};
    end else begin
      gate <= 0;
    end
  end

  // hopefully sync?
  if (reset) begin
    gate <= 0;
  end
end

// winners.  due to compare, there will be 0,1,2,3,4 set.
// median will be 2.
wire [3:0] w0 = { c01,  c02,  c03,  c04};
wire [3:0] w1 = {~c01,  c12,  c13,  c14};
wire [3:0] w2 = {~c02, ~c12,  c23,  c24};
wire [3:0] w3 = {~c03, ~c13, ~c23,  c34};
wire [3:0] w4 = {~c04, ~c14, ~c24, ~c34};

// widemux select -- one of these will have exactly two bits set.
wire s0 = (w0 == 4'h3) || (w0 == 4'h5) || (w0 == 4'h9) || (w0 == 4'h6) || (w0 == 4'hA) || (w0 == 4'hC);
wire s1 = (w1 == 4'h3) || (w1 == 4'h5) || (w1 == 4'h9) || (w1 == 4'h6) || (w1 == 4'hA) || (w1 == 4'hC);
wire s2 = (w2 == 4'h3) || (w2 == 4'h5) || (w2 == 4'h9) || (w2 == 4'h6) || (w2 == 4'hA) || (w2 == 4'hC);
wire s3 = (w3 == 4'h3) || (w3 == 4'h5) || (w3 == 4'h9) || (w3 == 4'h6) || (w3 == 4'hA) || (w3 == 4'hC);
wire s4 = (w4 == 4'h3) || (w4 == 4'h5) || (w4 == 4'h9) || (w4 == 4'h6) || (w4 == 4'hA) || (w4 == 4'hC);

// widemux
wire [7:0] result = ({(8){s0}} & ext[8*0+:8])
                  | ({(8){s1}} & ext[8*1+:8])
                  | ({(8){s2}} & ext[8*2+:8])
                  | ({(8){s3}} & ext[8*3+:8])
                  | ({(8){s4}} & ext[8*4+:8]);


// this version has a combinatorial path
assign i_ready = !reset; // no backpressure.  could also be 1'b1 if the checker allows.
assign o_payload_fragment = result;  // not sure if the checker likes output regs
assign o_valid = i_valid && gate[3]; // min lat version
assign o_payload_last = i_payload_stream_last && gate[3]; // gated for best practice

endmodule

Timing Analysis

Path 1-3.579 ns

From: srl[2]$_DFFE_PP_/Q

To: o_payload_fragment[1]

Data Arrival: 3.580 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`srl[2]$_DFFE_PP_/CLK`
0.748	sky130_fd_sc_hvl__dfxtp_1	`srl[2]$_DFFE_PP_/Q`
0.748	sky130_fd_sc_hvl__xor2_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1864/B`
1.039	sky130_fd_sc_hvl__xor2_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1864/X`
1.039	sky130_fd_sc_hvl__a21oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1865/B1`
1.227	sky130_fd_sc_hvl__a21oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1865/Y`
1.227	sky130_fd_sc_hvl__o21ai_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1866/B1`
1.403	sky130_fd_sc_hvl__o21ai_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1866/Y`
1.403	sky130_fd_sc_hvl__a21o_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1870/A1`
1.679	sky130_fd_sc_hvl__a21o_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1870/X`
1.679	sky130_fd_sc_hvl__a22oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1871/B2`
1.860	sky130_fd_sc_hvl__a22oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1871/Y`
1.860	sky130_fd_sc_hvl__o21a_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1873/A1`
2.263	sky130_fd_sc_hvl__o21a_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1873/X`
2.263	sky130_fd_sc_hvl__a22oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1887/A2`
2.520	sky130_fd_sc_hvl__a22oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1887/Y`
2.520	sky130_fd_sc_hvl__xor2_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1888/B`
3.181	sky130_fd_sc_hvl__xor2_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1888/X`
3.181	sky130_fd_sc_hvl__a22oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1906/A2`
3.453	sky130_fd_sc_hvl__a22oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1906/Y`
3.453	sky130_fd_sc_hvl__nand3_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1907/C`
3.580	sky130_fd_sc_hvl__nand3_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1907/Y`
3.580	Solution	`o_payload_fragment[1]`

Path 2-3.579 ns

From: srl[2]$_DFFE_PP_/Q

To: o_payload_fragment[3]

Data Arrival: 3.580 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`srl[2]$_DFFE_PP_/CLK`
0.748	sky130_fd_sc_hvl__dfxtp_1	`srl[2]$_DFFE_PP_/Q`
0.748	sky130_fd_sc_hvl__xor2_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1864/B`
1.039	sky130_fd_sc_hvl__xor2_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1864/X`
1.039	sky130_fd_sc_hvl__a21oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1865/B1`
1.227	sky130_fd_sc_hvl__a21oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1865/Y`
1.227	sky130_fd_sc_hvl__o21ai_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1866/B1`
1.403	sky130_fd_sc_hvl__o21ai_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1866/Y`
1.403	sky130_fd_sc_hvl__a21o_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1870/A1`
1.679	sky130_fd_sc_hvl__a21o_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1870/X`
1.679	sky130_fd_sc_hvl__a22oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1871/B2`
1.860	sky130_fd_sc_hvl__a22oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1871/Y`
1.860	sky130_fd_sc_hvl__o21a_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1873/A1`
2.263	sky130_fd_sc_hvl__o21a_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1873/X`
2.263	sky130_fd_sc_hvl__a22oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1887/A2`
2.520	sky130_fd_sc_hvl__a22oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1887/Y`
2.520	sky130_fd_sc_hvl__xor2_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1888/B`
3.181	sky130_fd_sc_hvl__xor2_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1888/X`
3.181	sky130_fd_sc_hvl__a22oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1914/A2`
3.453	sky130_fd_sc_hvl__a22oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1914/Y`
3.453	sky130_fd_sc_hvl__nand3_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1915/C`
3.580	sky130_fd_sc_hvl__nand3_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1915/Y`
3.580	Solution	`o_payload_fragment[3]`

Path 3-3.579 ns

From: srl[2]$_DFFE_PP_/Q

To: o_payload_fragment[4]

Data Arrival: 3.580 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`srl[2]$_DFFE_PP_/CLK`
0.748	sky130_fd_sc_hvl__dfxtp_1	`srl[2]$_DFFE_PP_/Q`
0.748	sky130_fd_sc_hvl__xor2_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1864/B`
1.039	sky130_fd_sc_hvl__xor2_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1864/X`
1.039	sky130_fd_sc_hvl__a21oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1865/B1`
1.227	sky130_fd_sc_hvl__a21oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1865/Y`
1.227	sky130_fd_sc_hvl__o21ai_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1866/B1`
1.403	sky130_fd_sc_hvl__o21ai_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1866/Y`
1.403	sky130_fd_sc_hvl__a21o_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1870/A1`
1.679	sky130_fd_sc_hvl__a21o_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1870/X`
1.679	sky130_fd_sc_hvl__a22oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1871/B2`
1.860	sky130_fd_sc_hvl__a22oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1871/Y`
1.860	sky130_fd_sc_hvl__o21a_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1873/A1`
2.263	sky130_fd_sc_hvl__o21a_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1873/X`
2.263	sky130_fd_sc_hvl__a22oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1887/A2`
2.520	sky130_fd_sc_hvl__a22oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1887/Y`
2.520	sky130_fd_sc_hvl__xor2_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1888/B`
3.181	sky130_fd_sc_hvl__xor2_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1888/X`
3.181	sky130_fd_sc_hvl__a22oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1918/A2`
3.453	sky130_fd_sc_hvl__a22oi_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1918/Y`
3.453	sky130_fd_sc_hvl__nand3_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1919/C`
3.580	sky130_fd_sc_hvl__nand3_1	`$abc$1796$auto$blifparse.cc:396:parse_blif$1919/Y`
3.580	Solution	`o_payload_fragment[4]`

Post-Synthesis Verilog

Download synth.v