SpinalHDL
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Submission #1

PASSED
RankingPercentile
Latency
123.88 (36 cycles)ns
7th
top 46%
Throughput
58.12 (20.0%)MHz
2nd
top 8%
Area
57084μm²
13th
top 92%
Score
84.20
6th
top 38%
Submitted Solution
Generated Verilog

Timing Analysis

Path 1-3.440 ns
From: window_pl[11][15]$_SDFF_PP0_/Q
To: window_pl[12][0]$_SDFF_PP0_/D
Data Arrival: 3.291 ns
Arrival (ns)CellPin
0.000Solutionclk
0.000sky130_fd_sc_hvl__dfxtp_1window_pl[11][15]$_SDFF_PP0_/CLK
0.736sky130_fd_sc_hvl__dfxtp_1window_pl[11][15]$_SDFF_PP0_/Q
0.736sky130_fd_sc_hvl__or2_1$abc$4398$auto$blifparse.cc:396:parse_blif$6033/A
1.259sky130_fd_sc_hvl__or2_1$abc$4398$auto$blifparse.cc:396:parse_blif$6033/X
1.259sky130_fd_sc_hvl__a22oi_1$abc$4398$auto$blifparse.cc:396:parse_blif$6042/B1
1.548sky130_fd_sc_hvl__a22oi_1$abc$4398$auto$blifparse.cc:396:parse_blif$6042/Y
1.548sky130_fd_sc_hvl__nand3_1$abc$4398$auto$blifparse.cc:396:parse_blif$6080/A
1.765sky130_fd_sc_hvl__nand3_1$abc$4398$auto$blifparse.cc:396:parse_blif$6080/Y
1.765sky130_fd_sc_hvl__a21oi_1$abc$4398$auto$blifparse.cc:396:parse_blif$6089/B1
2.976sky130_fd_sc_hvl__a21oi_1$abc$4398$auto$blifparse.cc:396:parse_blif$6089/Y
2.976sky130_fd_sc_hvl__o21ai_1$abc$4398$auto$blifparse.cc:396:parse_blif$6090/A2
3.106sky130_fd_sc_hvl__o21ai_1$abc$4398$auto$blifparse.cc:396:parse_blif$6090/Y
3.106sky130_fd_sc_hvl__a21oi_1$abc$4398$auto$blifparse.cc:396:parse_blif$6091/A1
3.291sky130_fd_sc_hvl__a21oi_1$abc$4398$auto$blifparse.cc:396:parse_blif$6091/Y
3.291sky130_fd_sc_hvl__dfxtp_1window_pl[12][0]$_SDFF_PP0_/D
Path 2-3.440 ns
From: window_pl[11][15]$_SDFF_PP0_/Q
To: window_pl[12][10]$_SDFF_PP0_/D
Data Arrival: 3.291 ns
Arrival (ns)CellPin
0.000Solutionclk
0.000sky130_fd_sc_hvl__dfxtp_1window_pl[11][15]$_SDFF_PP0_/CLK
0.736sky130_fd_sc_hvl__dfxtp_1window_pl[11][15]$_SDFF_PP0_/Q
0.736sky130_fd_sc_hvl__or2_1$abc$4398$auto$blifparse.cc:396:parse_blif$6033/A
1.259sky130_fd_sc_hvl__or2_1$abc$4398$auto$blifparse.cc:396:parse_blif$6033/X
1.259sky130_fd_sc_hvl__a22oi_1$abc$4398$auto$blifparse.cc:396:parse_blif$6042/B1
1.548sky130_fd_sc_hvl__a22oi_1$abc$4398$auto$blifparse.cc:396:parse_blif$6042/Y
1.548sky130_fd_sc_hvl__nand3_1$abc$4398$auto$blifparse.cc:396:parse_blif$6080/A
1.765sky130_fd_sc_hvl__nand3_1$abc$4398$auto$blifparse.cc:396:parse_blif$6080/Y
1.765sky130_fd_sc_hvl__a21oi_1$abc$4398$auto$blifparse.cc:396:parse_blif$6089/B1
2.976sky130_fd_sc_hvl__a21oi_1$abc$4398$auto$blifparse.cc:396:parse_blif$6089/Y
2.976sky130_fd_sc_hvl__o21ai_1$abc$4398$auto$blifparse.cc:396:parse_blif$6120/A2
3.106sky130_fd_sc_hvl__o21ai_1$abc$4398$auto$blifparse.cc:396:parse_blif$6120/Y
3.106sky130_fd_sc_hvl__a21oi_1$abc$4398$auto$blifparse.cc:396:parse_blif$6121/A1
3.291sky130_fd_sc_hvl__a21oi_1$abc$4398$auto$blifparse.cc:396:parse_blif$6121/Y
3.291sky130_fd_sc_hvl__dfxtp_1window_pl[12][10]$_SDFF_PP0_/D
Path 3-3.440 ns
From: window_pl[11][15]$_SDFF_PP0_/Q
To: window_pl[12][11]$_SDFF_PP0_/D
Data Arrival: 3.291 ns
Arrival (ns)CellPin
0.000Solutionclk
0.000sky130_fd_sc_hvl__dfxtp_1window_pl[11][15]$_SDFF_PP0_/CLK
0.736sky130_fd_sc_hvl__dfxtp_1window_pl[11][15]$_SDFF_PP0_/Q
0.736sky130_fd_sc_hvl__or2_1$abc$4398$auto$blifparse.cc:396:parse_blif$6033/A
1.259sky130_fd_sc_hvl__or2_1$abc$4398$auto$blifparse.cc:396:parse_blif$6033/X
1.259sky130_fd_sc_hvl__a22oi_1$abc$4398$auto$blifparse.cc:396:parse_blif$6042/B1
1.548sky130_fd_sc_hvl__a22oi_1$abc$4398$auto$blifparse.cc:396:parse_blif$6042/Y
1.548sky130_fd_sc_hvl__nand3_1$abc$4398$auto$blifparse.cc:396:parse_blif$6080/A
1.765sky130_fd_sc_hvl__nand3_1$abc$4398$auto$blifparse.cc:396:parse_blif$6080/Y
1.765sky130_fd_sc_hvl__a21oi_1$abc$4398$auto$blifparse.cc:396:parse_blif$6089/B1
2.976sky130_fd_sc_hvl__a21oi_1$abc$4398$auto$blifparse.cc:396:parse_blif$6089/Y
2.976sky130_fd_sc_hvl__o21ai_1$abc$4398$auto$blifparse.cc:396:parse_blif$6123/A2
3.106sky130_fd_sc_hvl__o21ai_1$abc$4398$auto$blifparse.cc:396:parse_blif$6123/Y
3.106sky130_fd_sc_hvl__a21oi_1$abc$4398$auto$blifparse.cc:396:parse_blif$6124/A1
3.291sky130_fd_sc_hvl__a21oi_1$abc$4398$auto$blifparse.cc:396:parse_blif$6124/Y
3.291sky130_fd_sc_hvl__dfxtp_1window_pl[12][11]$_SDFF_PP0_/D

Post-Synthesis Verilog