Barrel Shifter - Latchup

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Submission #2

PASSED

RankingPercentile

Latency

12.96 (1 cycles)ns

4th

top 100%

Throughput

77.15 (100.0%)MHz

4th

top 100%

Area

30935μm²

4th

top 100%

Score

85.13

4th

top 100%

Submitted Solution

// PipelineC solution template.
#include "uintN_t.h"
#include "intN_t.h"
#include "stream/stream.h"

// Input stream interface:
//   input.valid (input): Asserted when input data is valid
//   input.data.* (input): Input payload fields
//   input_ready (output): Assert when ready to accept input
//
// Output flow interface (no backpressure):
//   output.valid (output): Assert when output data is valid
//   output.data.* (output): Output payload fields

typedef struct input_payload_t {
  uint32_t data;
  uint5_t shift_amount;
  uint1_t direction;
  uint1_t rotate;
} input_payload_t;
DECL_STREAM_TYPE(input_payload_t)

typedef struct output_payload_t {
  uint32_t result;
} output_payload_t;
DECL_STREAM_TYPE(output_payload_t)

DECL_INPUT(stream(input_payload_t), input)
DECL_OUTPUT(uint1_t, input_ready)

DECL_OUTPUT(stream(output_payload_t), output)

#define CLK_RATE_MHZ 0.001
DECL_INPUT(uint1_t, clk)
CLK_MHZ(clk, CLK_RATE_MHZ)
MAIN_MHZ(solution, CLK_RATE_MHZ)
void solution()
{
  // Your implementation here
  uint32_t result = 0;
  input_ready = 1;
  if (input.valid) {
    if (input.data.rotate) {
      if (input.data.direction) {
        // rotate left
        result = (input.data.data << input.data.shift_amount) | (input.data.data >> (32 - input.data.shift_amount));
      }
      else {
        // rotate right
        result = (input.data.data >> input.data.shift_amount) | (input.data.data << (32 - input.data.shift_amount));
      }
    }
    else {
      if (input.data.direction) {
        // shift left
        result = input.data.data << input.data.shift_amount;
      }
      else {
        // shift right
        result = input.data.data >> input.data.shift_amount;
      }
    }
    output.data.result = result;
    output.valid = 1;
  }
}

Compile Log

/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/C_TO_LOGIC.py:7114: SyntaxWarning: invalid escape sequence '\/'
  
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/C_TO_LOGIC.py:7485: SyntaxWarning: invalid escape sequence '\d'
  )
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/C_TO_LOGIC.py:10680: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + "_WRITE" + f"\s?\("
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/C_TO_LOGIC.py:10680: SyntaxWarning: invalid escape sequence '\s'
  r = f"\w+" + "_WRITE" + f"\s?\("
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/C_TO_LOGIC.py:10682: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + "_WRITE_[0-9]+" + f"\s?\("
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/C_TO_LOGIC.py:10682: SyntaxWarning: invalid escape sequence '\s'
  r = f"\w+" + "_WRITE_[0-9]+" + f"\s?\("
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/C_TO_LOGIC.py:10688: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + "_READ" + f"\s?\("
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/C_TO_LOGIC.py:10688: SyntaxWarning: invalid escape sequence '\s'
  r = f"\w+" + "_READ" + f"\s?\("
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/C_TO_LOGIC.py:10690: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + "_READ_[0-9]+" + f"\s?\("
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/C_TO_LOGIC.py:10690: SyntaxWarning: invalid escape sequence '\s'
  r = f"\w+" + "_READ_[0-9]+" + f"\s?\("
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:272: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_SINGLE_INST.h"
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:348: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_array(_[0-9]+)+_t"
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:374: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_array_N_t.h"
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:404: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_bytes_t.h"
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:434: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + C_TO_FSM.FSM_EXT + ".h"
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:526: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + C_TO_FSM.FSM_EXT
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:598: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_bytes_t"
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:652: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_bytes_t"
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:1469: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_array_[0-9]+_t"
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:1902: SyntaxWarning: invalid escape sequence '\s'
  for type_regex in [f"uint[0-9]+_negate\s?\("]:  # DO int,float negate?
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:1963: SyntaxWarning: invalid escape sequence '\s'
  for type_regex in [f"int[0-9]+_abs\s?\("]:  # Float abs is bit manip func
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:2049: SyntaxWarning: invalid escape sequence '\w'
  for type_regex in [f"\w+_mux[0-9]+\s?\("]:
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:2245: SyntaxWarning: invalid escape sequence '\s'
  for type_regex in [f"count0s_uint[0-9]+\s?\("]:
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:2474: SyntaxWarning: invalid escape sequence '\s'
  regex = type_regex + "_" + op_regex + f"[0-9]+\s?\("
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:2841: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_[0-9]+_[0-9]+\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:2877: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"u?int[0-9]+_u?int[0-9]+\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:2915: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"[^_][u?]int[0-9]+_[0-9]+\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:2955: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"[^_]rotl[0-9]+_[0-9]+\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:2988: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"[^_]rotr[0-9]+_[0-9]+\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:3023: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"u?int[0-9]+_uint[0-9]+_[0-9]+\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:3064: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_uint[0-9]+_uint[0-9]+\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:3110: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_uint[0-9]+\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:3147: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_abs\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:3183: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_sign\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:3215: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"bswap_[0-9]+\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SW_LIB.py:3249: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"uint[0-9]+_array[0-9]+_(?:be|le)\s?\(")
/nix/store/ggkrks6v5i8jy5065myyijygjclzhxhg-pipelinec-unstable-2026-03-15/lib/pipelinec/src/SYN.py:1183: SyntaxWarning: invalid escape sequence '\/'
  

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Output directory: /submission/user/pipelinec_output
================== Parsing C Code to Logical Hierarchy ================================
Parsing: /submission/user/Solution.c
Preprocessing file...
Parsing C syntax...
Parsing non-function definitions...
Parsing derived fsm logic functions...
Doing old-style code generation based on PipelineC supported text patterns...
Elaborating function dataflow...
Defaulting to pyrtl based timing estimates...
Using PYRTL synthesizing for part: None
Elaborating dataflow of function: solution
Elaborating user function hierarchies down to raw HDL logic...
... found: BIN_OP_SL_uint32_t_uint5_t
... found: BIN_OP_SR_uint32_t_uint6_t
... found: BIN_OP_GT_uint6_t_uint5_t
... found: BIN_OP_SR_uint32_t_uint5_t
... found: BIN_OP_SL_uint32_t_uint6_t
Doing obvious logic trimming/collapsing...
Writing generated PipelineC code from elaboration to output directories...
Writing cache of parsed information to file...
================== Writing Resulting Logic to File ================================
Writing output files before adding pipelining...
Writing log of integer module instances: /submission/user/pipelinec_output/integer_module_instances.log
Writing VHDL files for all functions (before any added pipelining)...
Writing multi main top level files...
Writing the constant struct+enum definitions as defined from C code...
Writing global wire definitions as parsed from C code...
================== Adding Timing Information from Synthesis Tool ================================
Synthesizing before pipelining to get path delays...

Synthesizing function: solution
Function 1/1, elapsed time 0:00:14.257097...
...Waiting on synthesis for: solution
Running: /submission/user/pipelinec_output/solution/pyrtl_0CLK_6064c2b8.log
solution FMAX: 80.000 MHz (12.500 ns path delay)
================== Beginning Throughput Sweep ================================
Function: solution Target MHz: 0.001
Starting with no added pipelining...
Starting with blank sweep state...
Starting middle out sweep...
Starting from timing params without added pipelining...
Collecting modules to pipeline...
Pipelining modules...
Updating output files...
Estimated register usage: /submission/user/pipelinec_output/solution/solution_bcc5_registers.log
Running syn w timing params...
Elapsed time: 0:00:22.001740...
Running: /submission/user/pipelinec_output/solution/pyrtl_bcc5.log
solution Clock Goal: 0.00 (MHz) Current: 79.66 (MHz)(12.55 ns) 0 clks
Met timing...
================== Writing Results of Throughput Sweep ================================
Output VHDL files: /submission/user/pipelinec_output/vhdl_files.txt
Done.

Generated Verilog

module Solution(
    input clk,
    input reset,
    input i_valid,
    output i_ready,
    input [31:0] i_payload_data,
    input [4:0] i_payload_shift_amount,
    input i_payload_direction,
    input i_payload_rotate,
    output o_valid,
    output [31:0] o_payload
);

    wire [38:0] input_data;
    assign input_data = { i_payload_rotate, i_payload_direction, i_payload_shift_amount, i_payload_data };

    wire [31:0] output_data;
    wire output_valid;
    wire output_input_ready;

    solution inner(
        .clk(clk),
        .\input[data] (input_data),
        .\input[valid] (i_valid),
        .\output[data] (output_data),
        .\output[valid] (output_valid),
        .input_ready(output_input_ready)
    );

    assign i_ready = output_input_ready;
    assign o_valid = output_valid;
    assign o_payload = output_data[31:0];

endmodule


/* Generated by Yosys 0.55 (git sha1 60f126cd00c94892782470192d6c9f7abebe7c05, g++ 14.3.0 -fPIC -O3) */

module bin_op_eq_uint1_t_uint1_t_0clk_de264c78(left, right, return_output);
  wire _0_;
  wire _1_;
  wire _2_;
  wire [5:0] \:987.read_pipe ;
  input left;
  wire left;
  output return_output;
  wire return_output;
  input right;
  wire right;
  assign _0_ = left == right;
  assign _1_ = _0_ & 1'h1;
  assign _2_ = _1_ ? 1'h1 : 1'h0;
  assign \:987.read_pipe  = { left, right, 4'bx011 };
  assign return_output = _2_;
endmodule

module bin_op_gt_uint6_t_uint5_t_0clk_5af1a430(left, right, return_output);
  wire [5:0] _0_;
  wire _1_;
  wire _2_;
  wire [6:0] _3_;
  wire bin_op_eq_bin_op_gt_uint6_t_uint5_t_c_l15_c6_300c_left;
  wire bin_op_eq_bin_op_gt_uint6_t_uint5_t_c_l15_c6_300c_return_output;
  wire bin_op_eq_bin_op_gt_uint6_t_uint5_t_c_l15_c6_300c_right;
  wire [5:0] bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a_left;
  wire [6:0] bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a_return_output;
  wire [5:0] bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a_right;
  wire [5:0] const_sr_5_bin_op_gt_uint6_t_uint5_t_c_l13_c9_f873_return_output;
  wire [5:0] const_sr_5_bin_op_gt_uint6_t_uint5_t_c_l13_c9_f873_x;
  input [5:0] left;
  wire [5:0] left;
  output return_output;
  wire return_output;
  input [4:0] right;
  wire [4:0] right;
  wire rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09_cond;
  wire rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09_iffalse;
  wire rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09_iftrue;
  wire rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09_return_output;
  bin_op_eq_uint1_t_uint1_t_0clk_de264c78 bin_op_eq_bin_op_gt_uint6_t_uint5_t_c_l15_c6_300c (
    .left(bin_op_eq_bin_op_gt_uint6_t_uint5_t_c_l15_c6_300c_left),
    .return_output(_1_),
    .right(bin_op_eq_bin_op_gt_uint6_t_uint5_t_c_l15_c6_300c_right)
  );
  bin_op_minus_int6_t_int6_t_0clk_de264c78 bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a (
    .left(bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a_left),
    .return_output(_3_),
    .right(bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a_right)
  );
  const_sr_5_uint6_t_0clk_de264c78 const_sr_5_bin_op_gt_uint6_t_uint5_t_c_l13_c9_f873 (
    .return_output(_0_),
    .x(const_sr_5_bin_op_gt_uint6_t_uint5_t_c_l13_c9_f873_x)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09 (
    .cond(rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09_cond),
    .iffalse(rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09_iffalse),
    .iftrue(rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09_iftrue),
    .return_output(_2_)
  );
  assign const_sr_5_bin_op_gt_uint6_t_uint5_t_c_l13_c9_f873_x = left;
  assign const_sr_5_bin_op_gt_uint6_t_uint5_t_c_l13_c9_f873_return_output = _0_;
  assign bin_op_eq_bin_op_gt_uint6_t_uint5_t_c_l15_c6_300c_left = const_sr_5_bin_op_gt_uint6_t_uint5_t_c_l13_c9_f873_return_output[0];
  assign bin_op_eq_bin_op_gt_uint6_t_uint5_t_c_l15_c6_300c_right = 1'h0;
  assign bin_op_eq_bin_op_gt_uint6_t_uint5_t_c_l15_c6_300c_return_output = _1_;
  assign rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09_cond = bin_op_eq_bin_op_gt_uint6_t_uint5_t_c_l15_c6_300c_return_output;
  assign rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09_iftrue = bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a_return_output[5];
  assign rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09_iffalse = 1'h1;
  assign rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09_return_output = _2_;
  assign bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a_left = { 1'h0, right };
  assign bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a_right = { 1'h0, left[4:0] };
  assign bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a_return_output = _3_;
  assign return_output = rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09_return_output;
endmodule

module bin_op_minus_int6_t_int6_t_0clk_de264c78(left, right, return_output);
  wire [6:0] _0_;
  wire [6:0] _1_;
  wire [57:0] \:1046.read_pipe ;
  input [5:0] left;
  wire [5:0] left;
  output [6:0] return_output;
  wire [6:0] return_output;
  input [5:0] right;
  wire [5:0] right;
  assign _0_ = { left[5], left } - { right[5], right };
  assign _1_ = _0_ - 7'h00;
  assign \:1046.read_pipe  = { left, right, 46'hxxxxxxxxxxxx };
  assign return_output = _1_;
endmodule

module bin_op_minus_uint6_t_uint5_t_0clk_de264c78(left, right, return_output);
  wire [6:0] _0_;
  wire [6:0] _1_;
  wire [54:0] \:174.read_pipe ;
  input [5:0] left;
  wire [5:0] left;
  output [5:0] return_output;
  wire [5:0] return_output;
  input [4:0] right;
  wire [4:0] right;
  assign _0_ = { 1'h0, left } - { 2'h0, right };
  assign _1_ = _0_ - 7'h00;
  assign \:174.read_pipe  = { left, right, 44'hxxxxxxxxxxx };
  assign return_output = _1_[5:0];
endmodule

module bin_op_or_uint32_t_uint32_t_0clk_de264c78(left, right, return_output);
  wire [31:0] _0_;
  wire [159:0] \:358.read_pipe ;
  input [31:0] left;
  wire [31:0] left;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [31:0] right;
  wire [31:0] right;
  assign _0_ = left | right;
  assign \:358.read_pipe  = { left, right, 96'hxxxxxxxxxxxxxxxxxxxxxxxx };
  assign return_output = _0_;
endmodule

module bin_op_sl_uint32_t_uint5_t_0clk_295015b8(left, right, return_output);
  wire [31:0] _0_;
  wire [31:0] _1_;
  wire [31:0] _2_;
  wire [31:0] _3_;
  wire [31:0] _4_;
  wire [31:0] _5_;
  wire [31:0] _6_;
  wire [31:0] _7_;
  wire [31:0] _8_;
  wire [31:0] _9_;
  wire [31:0] const_sl_16_bin_op_sl_uint32_t_uint5_t_c_l22_c55_9b93_return_output;
  wire [31:0] const_sl_16_bin_op_sl_uint32_t_uint5_t_c_l22_c55_9b93_x;
  wire [31:0] const_sl_1_bin_op_sl_uint32_t_uint5_t_c_l18_c55_5c4b_return_output;
  wire [31:0] const_sl_1_bin_op_sl_uint32_t_uint5_t_c_l18_c55_5c4b_x;
  wire [31:0] const_sl_2_bin_op_sl_uint32_t_uint5_t_c_l19_c55_6bbe_return_output;
  wire [31:0] const_sl_2_bin_op_sl_uint32_t_uint5_t_c_l19_c55_6bbe_x;
  wire [31:0] const_sl_4_bin_op_sl_uint32_t_uint5_t_c_l20_c55_3af6_return_output;
  wire [31:0] const_sl_4_bin_op_sl_uint32_t_uint5_t_c_l20_c55_3af6_x;
  wire [31:0] const_sl_8_bin_op_sl_uint32_t_uint5_t_c_l21_c55_a59a_return_output;
  wire [31:0] const_sl_8_bin_op_sl_uint32_t_uint5_t_c_l21_c55_a59a_x;
  input [31:0] left;
  wire [31:0] left;
  wire mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_0c2b_cond;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_0c2b_iffalse;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_0c2b_iftrue;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_0c2b_return_output;
  wire mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_9aef_cond;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_9aef_iffalse;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_9aef_iftrue;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_9aef_return_output;
  wire mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_afab_cond;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_afab_iffalse;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_afab_iftrue;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_afab_return_output;
  wire mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_4756_cond;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_4756_iffalse;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_4756_iftrue;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_4756_return_output;
  wire mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_99a9_cond;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_99a9_iffalse;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_99a9_iftrue;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_99a9_return_output;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [4:0] right;
  wire [4:0] right;
  const_sl_16_uint32_t_0clk_de264c78 const_sl_16_bin_op_sl_uint32_t_uint5_t_c_l22_c55_9b93 (
    .return_output(_8_),
    .x(const_sl_16_bin_op_sl_uint32_t_uint5_t_c_l22_c55_9b93_x)
  );
  const_sl_1_uint32_t_0clk_de264c78 const_sl_1_bin_op_sl_uint32_t_uint5_t_c_l18_c55_5c4b (
    .return_output(_0_),
    .x(const_sl_1_bin_op_sl_uint32_t_uint5_t_c_l18_c55_5c4b_x)
  );
  const_sl_2_uint32_t_0clk_de264c78 const_sl_2_bin_op_sl_uint32_t_uint5_t_c_l19_c55_6bbe (
    .return_output(_2_),
    .x(const_sl_2_bin_op_sl_uint32_t_uint5_t_c_l19_c55_6bbe_x)
  );
  const_sl_4_uint32_t_0clk_de264c78 const_sl_4_bin_op_sl_uint32_t_uint5_t_c_l20_c55_3af6 (
    .return_output(_4_),
    .x(const_sl_4_bin_op_sl_uint32_t_uint5_t_c_l20_c55_3af6_x)
  );
  const_sl_8_uint32_t_0clk_de264c78 const_sl_8_bin_op_sl_uint32_t_uint5_t_c_l21_c55_a59a (
    .return_output(_6_),
    .x(const_sl_8_bin_op_sl_uint32_t_uint5_t_c_l21_c55_a59a_x)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_0c2b (
    .cond(mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_0c2b_cond),
    .iffalse(mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_0c2b_iffalse),
    .iftrue(mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_0c2b_iftrue),
    .return_output(_1_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_9aef (
    .cond(mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_9aef_cond),
    .iffalse(mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_9aef_iffalse),
    .iftrue(mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_9aef_iftrue),
    .return_output(_3_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_afab (
    .cond(mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_afab_cond),
    .iffalse(mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_afab_iffalse),
    .iftrue(mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_afab_iftrue),
    .return_output(_5_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_4756 (
    .cond(mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_4756_cond),
    .iffalse(mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_4756_iffalse),
    .iftrue(mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_4756_iftrue),
    .return_output(_7_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_99a9 (
    .cond(mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_99a9_cond),
    .iffalse(mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_99a9_iffalse),
    .iftrue(mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_99a9_iftrue),
    .return_output(_9_)
  );
  assign const_sl_1_bin_op_sl_uint32_t_uint5_t_c_l18_c55_5c4b_x = left;
  assign const_sl_1_bin_op_sl_uint32_t_uint5_t_c_l18_c55_5c4b_return_output = _0_;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_0c2b_cond = right[0];
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_0c2b_iftrue = const_sl_1_bin_op_sl_uint32_t_uint5_t_c_l18_c55_5c4b_return_output;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_0c2b_iffalse = left;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_0c2b_return_output = _1_;
  assign const_sl_2_bin_op_sl_uint32_t_uint5_t_c_l19_c55_6bbe_x = mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_0c2b_return_output;
  assign const_sl_2_bin_op_sl_uint32_t_uint5_t_c_l19_c55_6bbe_return_output = _2_;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_9aef_cond = right[1];
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_9aef_iftrue = const_sl_2_bin_op_sl_uint32_t_uint5_t_c_l19_c55_6bbe_return_output;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_9aef_iffalse = mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_0c2b_return_output;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_9aef_return_output = _3_;
  assign const_sl_4_bin_op_sl_uint32_t_uint5_t_c_l20_c55_3af6_x = mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_9aef_return_output;
  assign const_sl_4_bin_op_sl_uint32_t_uint5_t_c_l20_c55_3af6_return_output = _4_;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_afab_cond = right[2];
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_afab_iftrue = const_sl_4_bin_op_sl_uint32_t_uint5_t_c_l20_c55_3af6_return_output;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_afab_iffalse = mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_9aef_return_output;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_afab_return_output = _5_;
  assign const_sl_8_bin_op_sl_uint32_t_uint5_t_c_l21_c55_a59a_x = mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_afab_return_output;
  assign const_sl_8_bin_op_sl_uint32_t_uint5_t_c_l21_c55_a59a_return_output = _6_;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_4756_cond = right[3];
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_4756_iftrue = const_sl_8_bin_op_sl_uint32_t_uint5_t_c_l21_c55_a59a_return_output;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_4756_iffalse = mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_afab_return_output;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_4756_return_output = _7_;
  assign const_sl_16_bin_op_sl_uint32_t_uint5_t_c_l22_c55_9b93_x = mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_4756_return_output;
  assign const_sl_16_bin_op_sl_uint32_t_uint5_t_c_l22_c55_9b93_return_output = _8_;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_99a9_cond = right[4];
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_99a9_iftrue = const_sl_16_bin_op_sl_uint32_t_uint5_t_c_l22_c55_9b93_return_output;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_99a9_iffalse = mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_4756_return_output;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_99a9_return_output = _9_;
  assign return_output = mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_99a9_return_output;
endmodule

module bin_op_sl_uint32_t_uint6_t_0clk_91f7f59e(left, right, return_output);
  wire _00_;
  wire [31:0] _01_;
  wire [31:0] _02_;
  wire [31:0] _03_;
  wire [31:0] _04_;
  wire [31:0] _05_;
  wire [31:0] _06_;
  wire [31:0] _07_;
  wire [31:0] _08_;
  wire [31:0] _09_;
  wire [31:0] _10_;
  wire [31:0] _11_;
  wire [5:0] bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa_left;
  wire bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa_return_output;
  wire [4:0] bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa_right;
  wire [31:0] const_sl_16_bin_op_sl_uint32_t_uint6_t_c_l30_c55_5621_return_output;
  wire [31:0] const_sl_16_bin_op_sl_uint32_t_uint6_t_c_l30_c55_5621_x;
  wire [31:0] const_sl_1_bin_op_sl_uint32_t_uint6_t_c_l26_c55_3bff_return_output;
  wire [31:0] const_sl_1_bin_op_sl_uint32_t_uint6_t_c_l26_c55_3bff_x;
  wire [31:0] const_sl_2_bin_op_sl_uint32_t_uint6_t_c_l27_c55_5b9c_return_output;
  wire [31:0] const_sl_2_bin_op_sl_uint32_t_uint6_t_c_l27_c55_5b9c_x;
  wire [31:0] const_sl_4_bin_op_sl_uint32_t_uint6_t_c_l28_c55_fc70_return_output;
  wire [31:0] const_sl_4_bin_op_sl_uint32_t_uint6_t_c_l28_c55_fc70_x;
  wire [31:0] const_sl_8_bin_op_sl_uint32_t_uint6_t_c_l29_c55_f22f_return_output;
  wire [31:0] const_sl_8_bin_op_sl_uint32_t_uint6_t_c_l29_c55_f22f_x;
  input [31:0] left;
  wire [31:0] left;
  wire mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_4622_cond;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_4622_iffalse;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_4622_iftrue;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_4622_return_output;
  wire mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_1ab8_cond;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_1ab8_iffalse;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_1ab8_iftrue;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_1ab8_return_output;
  wire mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_936b_cond;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_936b_iffalse;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_936b_iftrue;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_936b_return_output;
  wire mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_14ec_cond;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_14ec_iffalse;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_14ec_iftrue;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_14ec_return_output;
  wire mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_2093_cond;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_2093_iffalse;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_2093_iftrue;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_2093_return_output;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [5:0] right;
  wire [5:0] right;
  wire rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_8366_cond;
  wire [31:0] rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_8366_iffalse;
  wire [31:0] rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_8366_iftrue;
  wire [31:0] rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_8366_return_output;
  bin_op_gt_uint6_t_uint5_t_0clk_5af1a430 bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa (
    .left(bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa_left),
    .return_output(_00_),
    .right(bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa_right)
  );
  const_sl_16_uint32_t_0clk_de264c78 const_sl_16_bin_op_sl_uint32_t_uint6_t_c_l30_c55_5621 (
    .return_output(_10_),
    .x(const_sl_16_bin_op_sl_uint32_t_uint6_t_c_l30_c55_5621_x)
  );
  const_sl_1_uint32_t_0clk_de264c78 const_sl_1_bin_op_sl_uint32_t_uint6_t_c_l26_c55_3bff (
    .return_output(_02_),
    .x(const_sl_1_bin_op_sl_uint32_t_uint6_t_c_l26_c55_3bff_x)
  );
  const_sl_2_uint32_t_0clk_de264c78 const_sl_2_bin_op_sl_uint32_t_uint6_t_c_l27_c55_5b9c (
    .return_output(_04_),
    .x(const_sl_2_bin_op_sl_uint32_t_uint6_t_c_l27_c55_5b9c_x)
  );
  const_sl_4_uint32_t_0clk_de264c78 const_sl_4_bin_op_sl_uint32_t_uint6_t_c_l28_c55_fc70 (
    .return_output(_06_),
    .x(const_sl_4_bin_op_sl_uint32_t_uint6_t_c_l28_c55_fc70_x)
  );
  const_sl_8_uint32_t_0clk_de264c78 const_sl_8_bin_op_sl_uint32_t_uint6_t_c_l29_c55_f22f (
    .return_output(_08_),
    .x(const_sl_8_bin_op_sl_uint32_t_uint6_t_c_l29_c55_f22f_x)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_4622 (
    .cond(mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_4622_cond),
    .iffalse(mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_4622_iffalse),
    .iftrue(mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_4622_iftrue),
    .return_output(_03_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_1ab8 (
    .cond(mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_1ab8_cond),
    .iffalse(mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_1ab8_iffalse),
    .iftrue(mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_1ab8_iftrue),
    .return_output(_05_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_936b (
    .cond(mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_936b_cond),
    .iffalse(mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_936b_iffalse),
    .iftrue(mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_936b_iftrue),
    .return_output(_07_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_14ec (
    .cond(mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_14ec_cond),
    .iffalse(mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_14ec_iffalse),
    .iftrue(mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_14ec_iftrue),
    .return_output(_09_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_2093 (
    .cond(mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_2093_cond),
    .iffalse(mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_2093_iffalse),
    .iftrue(mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_2093_iftrue),
    .return_output(_11_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_8366 (
    .cond(rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_8366_cond),
    .iffalse(rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_8366_iffalse),
    .iftrue(rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_8366_iftrue),
    .return_output(_01_)
  );
  assign bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa_left = right;
  assign bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa_right = 5'h1f;
  assign bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa_return_output = _00_;
  assign rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_8366_cond = bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa_return_output;
  assign rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_8366_iftrue = 32'd0;
  assign rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_8366_iffalse = mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_2093_return_output;
  assign rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_8366_return_output = _01_;
  assign const_sl_1_bin_op_sl_uint32_t_uint6_t_c_l26_c55_3bff_x = left;
  assign const_sl_1_bin_op_sl_uint32_t_uint6_t_c_l26_c55_3bff_return_output = _02_;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_4622_cond = right[0];
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_4622_iftrue = const_sl_1_bin_op_sl_uint32_t_uint6_t_c_l26_c55_3bff_return_output;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_4622_iffalse = left;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_4622_return_output = _03_;
  assign const_sl_2_bin_op_sl_uint32_t_uint6_t_c_l27_c55_5b9c_x = mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_4622_return_output;
  assign const_sl_2_bin_op_sl_uint32_t_uint6_t_c_l27_c55_5b9c_return_output = _04_;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_1ab8_cond = right[1];
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_1ab8_iftrue = const_sl_2_bin_op_sl_uint32_t_uint6_t_c_l27_c55_5b9c_return_output;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_1ab8_iffalse = mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_4622_return_output;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_1ab8_return_output = _05_;
  assign const_sl_4_bin_op_sl_uint32_t_uint6_t_c_l28_c55_fc70_x = mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_1ab8_return_output;
  assign const_sl_4_bin_op_sl_uint32_t_uint6_t_c_l28_c55_fc70_return_output = _06_;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_936b_cond = right[2];
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_936b_iftrue = const_sl_4_bin_op_sl_uint32_t_uint6_t_c_l28_c55_fc70_return_output;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_936b_iffalse = mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_1ab8_return_output;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_936b_return_output = _07_;
  assign const_sl_8_bin_op_sl_uint32_t_uint6_t_c_l29_c55_f22f_x = mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_936b_return_output;
  assign const_sl_8_bin_op_sl_uint32_t_uint6_t_c_l29_c55_f22f_return_output = _08_;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_14ec_cond = right[3];
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_14ec_iftrue = const_sl_8_bin_op_sl_uint32_t_uint6_t_c_l29_c55_f22f_return_output;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_14ec_iffalse = mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_936b_return_output;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_14ec_return_output = _09_;
  assign const_sl_16_bin_op_sl_uint32_t_uint6_t_c_l30_c55_5621_x = mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_14ec_return_output;
  assign const_sl_16_bin_op_sl_uint32_t_uint6_t_c_l30_c55_5621_return_output = _10_;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_2093_cond = right[4];
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_2093_iftrue = const_sl_16_bin_op_sl_uint32_t_uint6_t_c_l30_c55_5621_return_output;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_2093_iffalse = mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_14ec_return_output;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_2093_return_output = _11_;
  assign return_output = rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_8366_return_output;
endmodule

module bin_op_sr_uint32_t_uint5_t_0clk_295015b8(left, right, return_output);
  wire [31:0] _0_;
  wire [31:0] _1_;
  wire [31:0] _2_;
  wire [31:0] _3_;
  wire [31:0] _4_;
  wire [31:0] _5_;
  wire [31:0] _6_;
  wire [31:0] _7_;
  wire [31:0] _8_;
  wire [31:0] _9_;
  wire [31:0] const_sr_16_bin_op_sr_uint32_t_uint5_t_c_l22_c55_5931_return_output;
  wire [31:0] const_sr_16_bin_op_sr_uint32_t_uint5_t_c_l22_c55_5931_x;
  wire [31:0] const_sr_1_bin_op_sr_uint32_t_uint5_t_c_l18_c55_9e8e_return_output;
  wire [31:0] const_sr_1_bin_op_sr_uint32_t_uint5_t_c_l18_c55_9e8e_x;
  wire [31:0] const_sr_2_bin_op_sr_uint32_t_uint5_t_c_l19_c55_65ef_return_output;
  wire [31:0] const_sr_2_bin_op_sr_uint32_t_uint5_t_c_l19_c55_65ef_x;
  wire [31:0] const_sr_4_bin_op_sr_uint32_t_uint5_t_c_l20_c55_2943_return_output;
  wire [31:0] const_sr_4_bin_op_sr_uint32_t_uint5_t_c_l20_c55_2943_x;
  wire [31:0] const_sr_8_bin_op_sr_uint32_t_uint5_t_c_l21_c55_d854_return_output;
  wire [31:0] const_sr_8_bin_op_sr_uint32_t_uint5_t_c_l21_c55_d854_x;
  input [31:0] left;
  wire [31:0] left;
  wire mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_a2a0_cond;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_a2a0_iffalse;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_a2a0_iftrue;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_a2a0_return_output;
  wire mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_3178_cond;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_3178_iffalse;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_3178_iftrue;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_3178_return_output;
  wire mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_76bf_cond;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_76bf_iffalse;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_76bf_iftrue;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_76bf_return_output;
  wire mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_df1b_cond;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_df1b_iffalse;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_df1b_iftrue;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_df1b_return_output;
  wire mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_816c_cond;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_816c_iffalse;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_816c_iftrue;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_816c_return_output;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [4:0] right;
  wire [4:0] right;
  const_sr_16_uint32_t_0clk_de264c78 const_sr_16_bin_op_sr_uint32_t_uint5_t_c_l22_c55_5931 (
    .return_output(_8_),
    .x(const_sr_16_bin_op_sr_uint32_t_uint5_t_c_l22_c55_5931_x)
  );
  const_sr_1_uint32_t_0clk_de264c78 const_sr_1_bin_op_sr_uint32_t_uint5_t_c_l18_c55_9e8e (
    .return_output(_0_),
    .x(const_sr_1_bin_op_sr_uint32_t_uint5_t_c_l18_c55_9e8e_x)
  );
  const_sr_2_uint32_t_0clk_de264c78 const_sr_2_bin_op_sr_uint32_t_uint5_t_c_l19_c55_65ef (
    .return_output(_2_),
    .x(const_sr_2_bin_op_sr_uint32_t_uint5_t_c_l19_c55_65ef_x)
  );
  const_sr_4_uint32_t_0clk_de264c78 const_sr_4_bin_op_sr_uint32_t_uint5_t_c_l20_c55_2943 (
    .return_output(_4_),
    .x(const_sr_4_bin_op_sr_uint32_t_uint5_t_c_l20_c55_2943_x)
  );
  const_sr_8_uint32_t_0clk_de264c78 const_sr_8_bin_op_sr_uint32_t_uint5_t_c_l21_c55_d854 (
    .return_output(_6_),
    .x(const_sr_8_bin_op_sr_uint32_t_uint5_t_c_l21_c55_d854_x)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_a2a0 (
    .cond(mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_a2a0_cond),
    .iffalse(mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_a2a0_iffalse),
    .iftrue(mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_a2a0_iftrue),
    .return_output(_1_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_3178 (
    .cond(mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_3178_cond),
    .iffalse(mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_3178_iffalse),
    .iftrue(mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_3178_iftrue),
    .return_output(_3_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_76bf (
    .cond(mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_76bf_cond),
    .iffalse(mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_76bf_iffalse),
    .iftrue(mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_76bf_iftrue),
    .return_output(_5_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_df1b (
    .cond(mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_df1b_cond),
    .iffalse(mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_df1b_iffalse),
    .iftrue(mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_df1b_iftrue),
    .return_output(_7_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_816c (
    .cond(mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_816c_cond),
    .iffalse(mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_816c_iffalse),
    .iftrue(mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_816c_iftrue),
    .return_output(_9_)
  );
  assign const_sr_1_bin_op_sr_uint32_t_uint5_t_c_l18_c55_9e8e_x = left;
  assign const_sr_1_bin_op_sr_uint32_t_uint5_t_c_l18_c55_9e8e_return_output = _0_;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_a2a0_cond = right[0];
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_a2a0_iftrue = const_sr_1_bin_op_sr_uint32_t_uint5_t_c_l18_c55_9e8e_return_output;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_a2a0_iffalse = left;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_a2a0_return_output = _1_;
  assign const_sr_2_bin_op_sr_uint32_t_uint5_t_c_l19_c55_65ef_x = mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_a2a0_return_output;
  assign const_sr_2_bin_op_sr_uint32_t_uint5_t_c_l19_c55_65ef_return_output = _2_;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_3178_cond = right[1];
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_3178_iftrue = const_sr_2_bin_op_sr_uint32_t_uint5_t_c_l19_c55_65ef_return_output;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_3178_iffalse = mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_a2a0_return_output;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_3178_return_output = _3_;
  assign const_sr_4_bin_op_sr_uint32_t_uint5_t_c_l20_c55_2943_x = mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_3178_return_output;
  assign const_sr_4_bin_op_sr_uint32_t_uint5_t_c_l20_c55_2943_return_output = _4_;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_76bf_cond = right[2];
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_76bf_iftrue = const_sr_4_bin_op_sr_uint32_t_uint5_t_c_l20_c55_2943_return_output;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_76bf_iffalse = mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_3178_return_output;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_76bf_return_output = _5_;
  assign const_sr_8_bin_op_sr_uint32_t_uint5_t_c_l21_c55_d854_x = mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_76bf_return_output;
  assign const_sr_8_bin_op_sr_uint32_t_uint5_t_c_l21_c55_d854_return_output = _6_;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_df1b_cond = right[3];
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_df1b_iftrue = const_sr_8_bin_op_sr_uint32_t_uint5_t_c_l21_c55_d854_return_output;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_df1b_iffalse = mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_76bf_return_output;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_df1b_return_output = _7_;
  assign const_sr_16_bin_op_sr_uint32_t_uint5_t_c_l22_c55_5931_x = mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_df1b_return_output;
  assign const_sr_16_bin_op_sr_uint32_t_uint5_t_c_l22_c55_5931_return_output = _8_;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_816c_cond = right[4];
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_816c_iftrue = const_sr_16_bin_op_sr_uint32_t_uint5_t_c_l22_c55_5931_return_output;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_816c_iffalse = mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_df1b_return_output;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_816c_return_output = _9_;
  assign return_output = mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_816c_return_output;
endmodule

module bin_op_sr_uint32_t_uint6_t_0clk_9f6ea3e6(left, right, return_output);
  wire _00_;
  wire [31:0] _01_;
  wire [31:0] _02_;
  wire [31:0] _03_;
  wire [31:0] _04_;
  wire [31:0] _05_;
  wire [31:0] _06_;
  wire [31:0] _07_;
  wire [31:0] _08_;
  wire [31:0] _09_;
  wire [31:0] _10_;
  wire [31:0] _11_;
  wire [5:0] bin_op_gt_bin_op_sr_uint32_t_uint6_t_c_l17_c6_0dcd_left;
  wire bin_op_gt_bin_op_sr_uint32_t_uint6_t_c_l17_c6_0dcd_return_output;
  wire [4:0] bin_op_gt_bin_op_sr_uint32_t_uint6_t_c_l17_c6_0dcd_right;
  wire [31:0] const_sr_16_bin_op_sr_uint32_t_uint6_t_c_l35_c55_07c2_return_output;
  wire [31:0] const_sr_16_bin_op_sr_uint32_t_uint6_t_c_l35_c55_07c2_x;
  wire [31:0] const_sr_1_bin_op_sr_uint32_t_uint6_t_c_l31_c55_8f1e_return_output;
  wire [31:0] const_sr_1_bin_op_sr_uint32_t_uint6_t_c_l31_c55_8f1e_x;
  wire [31:0] const_sr_2_bin_op_sr_uint32_t_uint6_t_c_l32_c55_d64b_return_output;
  wire [31:0] const_sr_2_bin_op_sr_uint32_t_uint6_t_c_l32_c55_d64b_x;
  wire [31:0] const_sr_4_bin_op_sr_uint32_t_uint6_t_c_l33_c55_5e94_return_output;
  wire [31:0] const_sr_4_bin_op_sr_uint32_t_uint6_t_c_l33_c55_5e94_x;
  wire [31:0] const_sr_8_bin_op_sr_uint32_t_uint6_t_c_l34_c55_1fe4_return_output;
  wire [31:0] const_sr_8_bin_op_sr_uint32_t_uint6_t_c_l34_c55_1fe4_x;
  input [31:0] left;
  wire [31:0] left;
  wire mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_fd38_cond;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_fd38_iffalse;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_fd38_iftrue;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_fd38_return_output;
  wire mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_90d0_cond;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_90d0_iffalse;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_90d0_iftrue;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_90d0_return_output;
  wire mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_455e_cond;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_455e_iffalse;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_455e_iftrue;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_455e_return_output;
  wire mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_5ee6_cond;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_5ee6_iffalse;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_5ee6_iftrue;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_5ee6_return_output;
  wire mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_8db0_cond;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_8db0_iffalse;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_8db0_iftrue;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_8db0_return_output;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [5:0] right;
  wire [5:0] right;
  wire rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_68cd_cond;
  wire [31:0] rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_68cd_iffalse;
  wire [31:0] rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_68cd_iftrue;
  wire [31:0] rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_68cd_return_output;
  bin_op_gt_uint6_t_uint5_t_0clk_5af1a430 bin_op_gt_bin_op_sr_uint32_t_uint6_t_c_l17_c6_0dcd (
    .left(bin_op_gt_bin_op_sr_uint32_t_uint6_t_c_l17_c6_0dcd_left),
    .return_output(_00_),
    .right(bin_op_gt_bin_op_sr_uint32_t_uint6_t_c_l17_c6_0dcd_right)
  );
  const_sr_16_uint32_t_0clk_de264c78 const_sr_16_bin_op_sr_uint32_t_uint6_t_c_l35_c55_07c2 (
    .return_output(_10_),
    .x(const_sr_16_bin_op_sr_uint32_t_uint6_t_c_l35_c55_07c2_x)
  );
  const_sr_1_uint32_t_0clk_de264c78 const_sr_1_bin_op_sr_uint32_t_uint6_t_c_l31_c55_8f1e (
    .return_output(_02_),
    .x(const_sr_1_bin_op_sr_uint32_t_uint6_t_c_l31_c55_8f1e_x)
  );
  const_sr_2_uint32_t_0clk_de264c78 const_sr_2_bin_op_sr_uint32_t_uint6_t_c_l32_c55_d64b (
    .return_output(_04_),
    .x(const_sr_2_bin_op_sr_uint32_t_uint6_t_c_l32_c55_d64b_x)
  );
  const_sr_4_uint32_t_0clk_de264c78 const_sr_4_bin_op_sr_uint32_t_uint6_t_c_l33_c55_5e94 (
    .return_output(_06_),
    .x(const_sr_4_bin_op_sr_uint32_t_uint6_t_c_l33_c55_5e94_x)
  );
  const_sr_8_uint32_t_0clk_de264c78 const_sr_8_bin_op_sr_uint32_t_uint6_t_c_l34_c55_1fe4 (
    .return_output(_08_),
    .x(const_sr_8_bin_op_sr_uint32_t_uint6_t_c_l34_c55_1fe4_x)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_fd38 (
    .cond(mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_fd38_cond),
    .iffalse(mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_fd38_iffalse),
    .iftrue(mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_fd38_iftrue),
    .return_output(_03_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_90d0 (
    .cond(mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_90d0_cond),
    .iffalse(mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_90d0_iffalse),
    .iftrue(mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_90d0_iftrue),
    .return_output(_05_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_455e (
    .cond(mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_455e_cond),
    .iffalse(mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_455e_iffalse),
    .iftrue(mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_455e_iftrue),
    .return_output(_07_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_5ee6 (
    .cond(mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_5ee6_cond),
    .iffalse(mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_5ee6_iffalse),
    .iftrue(mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_5ee6_iftrue),
    .return_output(_09_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_8db0 (
    .cond(mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_8db0_cond),
    .iffalse(mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_8db0_iffalse),
    .iftrue(mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_8db0_iftrue),
    .return_output(_11_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_68cd (
    .cond(rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_68cd_cond),
    .iffalse(rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_68cd_iffalse),
    .iftrue(rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_68cd_iftrue),
    .return_output(_01_)
  );
  assign bin_op_gt_bin_op_sr_uint32_t_uint6_t_c_l17_c6_0dcd_left = right;
  assign bin_op_gt_bin_op_sr_uint32_t_uint6_t_c_l17_c6_0dcd_right = 5'h1f;
  assign bin_op_gt_bin_op_sr_uint32_t_uint6_t_c_l17_c6_0dcd_return_output = _00_;
  assign rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_68cd_cond = bin_op_gt_bin_op_sr_uint32_t_uint6_t_c_l17_c6_0dcd_return_output;
  assign rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_68cd_iftrue = 32'd0;
  assign rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_68cd_iffalse = mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_8db0_return_output;
  assign rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_68cd_return_output = _01_;
  assign const_sr_1_bin_op_sr_uint32_t_uint6_t_c_l31_c55_8f1e_x = left;
  assign const_sr_1_bin_op_sr_uint32_t_uint6_t_c_l31_c55_8f1e_return_output = _02_;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_fd38_cond = right[0];
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_fd38_iftrue = const_sr_1_bin_op_sr_uint32_t_uint6_t_c_l31_c55_8f1e_return_output;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_fd38_iffalse = left;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_fd38_return_output = _03_;
  assign const_sr_2_bin_op_sr_uint32_t_uint6_t_c_l32_c55_d64b_x = mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_fd38_return_output;
  assign const_sr_2_bin_op_sr_uint32_t_uint6_t_c_l32_c55_d64b_return_output = _04_;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_90d0_cond = right[1];
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_90d0_iftrue = const_sr_2_bin_op_sr_uint32_t_uint6_t_c_l32_c55_d64b_return_output;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_90d0_iffalse = mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_fd38_return_output;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_90d0_return_output = _05_;
  assign const_sr_4_bin_op_sr_uint32_t_uint6_t_c_l33_c55_5e94_x = mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_90d0_return_output;
  assign const_sr_4_bin_op_sr_uint32_t_uint6_t_c_l33_c55_5e94_return_output = _06_;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_455e_cond = right[2];
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_455e_iftrue = const_sr_4_bin_op_sr_uint32_t_uint6_t_c_l33_c55_5e94_return_output;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_455e_iffalse = mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_90d0_return_output;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_455e_return_output = _07_;
  assign const_sr_8_bin_op_sr_uint32_t_uint6_t_c_l34_c55_1fe4_x = mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_455e_return_output;
  assign const_sr_8_bin_op_sr_uint32_t_uint6_t_c_l34_c55_1fe4_return_output = _08_;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_5ee6_cond = right[3];
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_5ee6_iftrue = const_sr_8_bin_op_sr_uint32_t_uint6_t_c_l34_c55_1fe4_return_output;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_5ee6_iffalse = mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_455e_return_output;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_5ee6_return_output = _09_;
  assign const_sr_16_bin_op_sr_uint32_t_uint6_t_c_l35_c55_07c2_x = mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_5ee6_return_output;
  assign const_sr_16_bin_op_sr_uint32_t_uint6_t_c_l35_c55_07c2_return_output = _10_;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_8db0_cond = right[4];
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_8db0_iftrue = const_sr_16_bin_op_sr_uint32_t_uint6_t_c_l35_c55_07c2_return_output;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_8db0_iffalse = mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_5ee6_return_output;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_8db0_return_output = _11_;
  assign return_output = rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_68cd_return_output;
endmodule

module const_sl_16_uint32_t_0clk_de264c78(x, return_output);
  wire [31:0] _0_;
  wire [63:0] \:949.read_pipe ;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [31:0] x;
  wire [31:0] x;
  assign _0_ = x << 31'h00000010;
  assign \:949.read_pipe  = { 32'hxxxxxxxx, x };
  assign return_output = _0_;
endmodule

module const_sl_1_uint32_t_0clk_de264c78(x, return_output);
  wire [31:0] _0_;
  wire [63:0] \:873.read_pipe ;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [31:0] x;
  wire [31:0] x;
  assign _0_ = x << 31'h00000001;
  assign \:873.read_pipe  = { 32'hxxxxxxxx, x };
  assign return_output = _0_;
endmodule

module const_sl_2_uint32_t_0clk_de264c78(x, return_output);
  wire [31:0] _0_;
  wire [63:0] \:892.read_pipe ;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [31:0] x;
  wire [31:0] x;
  assign _0_ = x << 31'h00000002;
  assign \:892.read_pipe  = { 32'hxxxxxxxx, x };
  assign return_output = _0_;
endmodule

module const_sl_4_uint32_t_0clk_de264c78(x, return_output);
  wire [31:0] _0_;
  wire [63:0] \:911.read_pipe ;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [31:0] x;
  wire [31:0] x;
  assign _0_ = x << 31'h00000004;
  assign \:911.read_pipe  = { 32'hxxxxxxxx, x };
  assign return_output = _0_;
endmodule

module const_sl_8_uint32_t_0clk_de264c78(x, return_output);
  wire [31:0] _0_;
  wire [63:0] \:930.read_pipe ;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [31:0] x;
  wire [31:0] x;
  assign _0_ = x << 31'h00000008;
  assign \:930.read_pipe  = { 32'hxxxxxxxx, x };
  assign return_output = _0_;
endmodule

module const_sr_16_uint32_t_0clk_de264c78(x, return_output);
  wire [31:0] _0_;
  wire [63:0] \:854.read_pipe ;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [31:0] x;
  wire [31:0] x;
  assign _0_ = x >> 31'h00000010;
  assign \:854.read_pipe  = { 32'hxxxxxxxx, x };
  assign return_output = _0_;
endmodule

module const_sr_1_uint32_t_0clk_de264c78(x, return_output);
  wire [31:0] _0_;
  wire [63:0] \:778.read_pipe ;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [31:0] x;
  wire [31:0] x;
  assign _0_ = x >> 31'h00000001;
  assign \:778.read_pipe  = { 32'hxxxxxxxx, x };
  assign return_output = _0_;
endmodule

module const_sr_2_uint32_t_0clk_de264c78(x, return_output);
  wire [31:0] _0_;
  wire [63:0] \:797.read_pipe ;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [31:0] x;
  wire [31:0] x;
  assign _0_ = x >> 31'h00000002;
  assign \:797.read_pipe  = { 32'hxxxxxxxx, x };
  assign return_output = _0_;
endmodule

module const_sr_4_uint32_t_0clk_de264c78(x, return_output);
  wire [31:0] _0_;
  wire [63:0] \:816.read_pipe ;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [31:0] x;
  wire [31:0] x;
  assign _0_ = x >> 31'h00000004;
  assign \:816.read_pipe  = { 32'hxxxxxxxx, x };
  assign return_output = _0_;
endmodule

module const_sr_5_uint6_t_0clk_de264c78(x, return_output);
  wire [5:0] _0_;
  wire [11:0] \:968.read_pipe ;
  output [5:0] return_output;
  wire [5:0] return_output;
  input [5:0] x;
  wire [5:0] x;
  assign _0_ = x >> 31'h00000005;
  assign \:968.read_pipe  = { 6'hxx, x };
  assign return_output = _0_;
endmodule

module const_sr_8_uint32_t_0clk_de264c78(x, return_output);
  wire [31:0] _0_;
  wire [63:0] \:835.read_pipe ;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [31:0] x;
  wire [31:0] x;
  assign _0_ = x >> 31'h00000008;
  assign \:835.read_pipe  = { 32'hxxxxxxxx, x };
  assign return_output = _0_;
endmodule

module mux_uint1_t_output_payload_t_stream_t_output_payload_t_stream_t_0clk_de264c78(cond, \iftrue[data] , \iftrue[valid] , \iffalse[data] , \iffalse[valid] , \return_output[data] , \return_output[valid] );
  wire _0_;
  wire [32:0] _1_;
  wire [99:0] \:130.read_pipe ;
  input cond;
  wire cond;
  input [31:0] \iffalse[data] ;
  wire [31:0] \iffalse[data] ;
  input \iffalse[valid] ;
  wire \iffalse[valid] ;
  input [31:0] \iftrue[data] ;
  wire [31:0] \iftrue[data] ;
  input \iftrue[valid] ;
  wire \iftrue[valid] ;
  output [31:0] \return_output[data] ;
  wire [31:0] \return_output[data] ;
  output \return_output[valid] ;
  wire \return_output[valid] ;
  assign _0_ = cond == 1'h1;
  assign _1_ = _0_ ? { \iftrue[valid] , \iftrue[data]  } : { \iffalse[valid] , \iffalse[data]  };
  assign \:130.read_pipe  = { \iffalse[valid] , \iffalse[data] , \iftrue[valid] , \iftrue[data] , cond, 33'hxxxxxxxxx };
  assign \return_output[data]  = _1_[31:0];
  assign \return_output[valid]  = _1_[32];
endmodule

module mux_uint1_t_uint1_t_uint1_t_0clk_de264c78(cond, iftrue, iffalse, return_output);
  wire _0_;
  wire _1_;
  wire [3:0] \:1024.read_pipe ;
  input cond;
  wire cond;
  input iffalse;
  wire iffalse;
  input iftrue;
  wire iftrue;
  output return_output;
  wire return_output;
  assign _0_ = cond == 1'h1;
  assign _1_ = _0_ ? iftrue : iffalse;
  assign \:1024.read_pipe  = { iffalse, iftrue, cond, 1'hx };
  assign return_output = _1_;
endmodule

module mux_uint1_t_uint32_t_uint32_t_0clk_de264c78(cond, iftrue, iffalse, return_output);
  wire _0_;
  wire [31:0] _1_;
  wire [96:0] \:152.read_pipe ;
  input cond;
  wire cond;
  input [31:0] iffalse;
  wire [31:0] iffalse;
  input [31:0] iftrue;
  wire [31:0] iftrue;
  output [31:0] return_output;
  wire [31:0] return_output;
  assign _0_ = cond == 1'h1;
  assign _1_ = _0_ ? iftrue : iffalse;
  assign \:152.read_pipe  = { iffalse, iftrue, cond, 32'hxxxxxxxx };
  assign return_output = _1_;
endmodule

module solution(\input[data] , \input[valid] , clk, input_ready, \output[data] , \output[valid] );
  wire [32:0] _0_;
  wire _1_;
  input clk;
  wire clk;
  (* dont_touch = "true" *)
  (* keep = "true" *)
  (* syn_keep = 1'h1 *)
  wire clk_1p0khz;
  wire [39:0] global_to_module;
  input [38:0] \input[data] ;
  wire [38:0] \input[data] ;
  input \input[valid] ;
  wire \input[valid] ;
  output input_ready;
  wire input_ready;
  wire [33:0] module_to_global;
  output [31:0] \output[data] ;
  wire [31:0] \output[data] ;
  output \output[valid] ;
  wire \output[valid] ;
  solution_0clk_6064c2b8 solution_0clk_6064c2b8 (
    .clk(clk_1p0khz),
    .clock_enable(1'h1),
    .\global_to_module[input] (global_to_module),
    .\module_to_global[input_ready] (_1_),
    .\module_to_global[output] (_0_)
  );
  assign clk_1p0khz = clk;
  assign module_to_global = { _1_, _0_ };
  assign global_to_module = { \input[valid] , \input[data]  };
  assign input_ready = module_to_global[33];
  assign \output[data]  = module_to_global[31:0];
  assign \output[valid]  = module_to_global[32];
endmodule

module solution_0clk_6064c2b8(clk, clock_enable, \global_to_module[input] , \module_to_global[output] , \module_to_global[input_ready] );
  wire [5:0] _00_;
  wire [31:0] _01_;
  wire [31:0] _02_;
  wire [31:0] _03_;
  wire [31:0] _04_;
  wire [31:0] _05_;
  wire _06_;
  wire [32:0] _07_;
  wire [32:0] _08_;
  reg [32:0] _09_ = 33'h000000000;
  wire [31:0] _10_;
  wire _11_;
  wire [31:0] _12_;
  wire [31:0] _13_;
  wire [5:0] _14_;
  wire [31:0] _15_;
  wire [31:0] _16_;
  wire [5:0] bin_op_minus_solution_c_l46_c86_44bd_left;
  wire [5:0] bin_op_minus_solution_c_l46_c86_44bd_return_output;
  wire [4:0] bin_op_minus_solution_c_l46_c86_44bd_right;
  wire [5:0] bin_op_minus_solution_c_l50_c86_05e0_left;
  wire [5:0] bin_op_minus_solution_c_l50_c86_05e0_return_output;
  wire [4:0] bin_op_minus_solution_c_l50_c86_05e0_right;
  wire [31:0] bin_op_or_solution_c_l46_c19_27ae_left;
  wire [31:0] bin_op_or_solution_c_l46_c19_27ae_return_output;
  wire [31:0] bin_op_or_solution_c_l46_c19_27ae_right;
  wire [31:0] bin_op_or_solution_c_l50_c19_6eaf_left;
  wire [31:0] bin_op_or_solution_c_l50_c19_6eaf_return_output;
  wire [31:0] bin_op_or_solution_c_l50_c19_6eaf_right;
  wire [31:0] bin_op_sl_solution_c_l50_c66_640a_left;
  wire [31:0] bin_op_sl_solution_c_l50_c66_640a_return_output;
  wire [5:0] bin_op_sl_solution_c_l50_c66_640a_right;
  wire [31:0] bin_op_sl_uint32_t_uint5_t_solution_c_l46_l56_duplicate_ae85_left;
  wire [31:0] bin_op_sl_uint32_t_uint5_t_solution_c_l46_l56_duplicate_ae85_return_output;
  wire [4:0] bin_op_sl_uint32_t_uint5_t_solution_c_l46_l56_duplicate_ae85_right;
  wire [31:0] bin_op_sr_solution_c_l46_c66_05f6_left;
  wire [31:0] bin_op_sr_solution_c_l46_c66_05f6_return_output;
  wire [5:0] bin_op_sr_solution_c_l46_c66_05f6_right;
  wire [31:0] bin_op_sr_uint32_t_uint5_t_solution_c_l60_l50_duplicate_ab24_left;
  wire [31:0] bin_op_sr_uint32_t_uint5_t_solution_c_l60_l50_duplicate_ab24_return_output;
  wire [4:0] bin_op_sr_uint32_t_uint5_t_solution_c_l60_l50_duplicate_ab24_right;
  input clk;
  wire clk;
  wire clk_en_internal;
  input clock_enable;
  wire clock_enable;
  input [39:0] \global_to_module[input] ;
  wire [39:0] \global_to_module[input] ;
  output \module_to_global[input_ready] ;
  wire \module_to_global[input_ready] ;
  output [32:0] \module_to_global[output] ;
  wire [32:0] \module_to_global[output] ;
  wire [32:0] \output ;
  wire output_mux_solution_c_l42_c3_bfe2_cond;
  wire [32:0] output_mux_solution_c_l42_c3_bfe2_iffalse;
  wire [32:0] output_mux_solution_c_l42_c3_bfe2_iftrue;
  wire [32:0] output_mux_solution_c_l42_c3_bfe2_return_output;
  wire [32:0] reg_comb_output;
  wire result_mux_solution_c_l43_c5_3592_cond;
  wire [31:0] result_mux_solution_c_l43_c5_3592_iffalse;
  wire [31:0] result_mux_solution_c_l43_c5_3592_iftrue;
  wire [31:0] result_mux_solution_c_l43_c5_3592_return_output;
  wire result_mux_solution_c_l44_c7_bd2b_cond;
  wire [31:0] result_mux_solution_c_l44_c7_bd2b_iffalse;
  wire [31:0] result_mux_solution_c_l44_c7_bd2b_iftrue;
  wire [31:0] result_mux_solution_c_l44_c7_bd2b_return_output;
  wire result_mux_solution_c_l54_c7_032b_cond;
  wire [31:0] result_mux_solution_c_l54_c7_032b_iffalse;
  wire [31:0] result_mux_solution_c_l54_c7_032b_iftrue;
  wire [31:0] result_mux_solution_c_l54_c7_032b_return_output;
  assign _06_ = clk_en_internal ? 1'h1 : 1'h0;
  assign _07_ = clk_en_internal ? reg_comb_output : \output ;
  assign _08_ = clk_en_internal ? reg_comb_output : \output ;
  always @(posedge clk)
    _09_ <= _08_;
  bin_op_minus_uint6_t_uint5_t_0clk_de264c78 bin_op_minus_solution_c_l46_c86_44bd (
    .left(bin_op_minus_solution_c_l46_c86_44bd_left),
    .return_output(_14_),
    .right(bin_op_minus_solution_c_l46_c86_44bd_right)
  );
  bin_op_minus_uint6_t_uint5_t_0clk_de264c78 bin_op_minus_solution_c_l50_c86_05e0 (
    .left(bin_op_minus_solution_c_l50_c86_05e0_left),
    .return_output(_00_),
    .right(bin_op_minus_solution_c_l50_c86_05e0_right)
  );
  bin_op_or_uint32_t_uint32_t_0clk_de264c78 bin_op_or_solution_c_l46_c19_27ae (
    .left(bin_op_or_solution_c_l46_c19_27ae_left),
    .return_output(_16_),
    .right(bin_op_or_solution_c_l46_c19_27ae_right)
  );
  bin_op_or_uint32_t_uint32_t_0clk_de264c78 bin_op_or_solution_c_l50_c19_6eaf (
    .left(bin_op_or_solution_c_l50_c19_6eaf_left),
    .return_output(_02_),
    .right(bin_op_or_solution_c_l50_c19_6eaf_right)
  );
  bin_op_sl_uint32_t_uint6_t_0clk_91f7f59e bin_op_sl_solution_c_l50_c66_640a (
    .left(bin_op_sl_solution_c_l50_c66_640a_left),
    .return_output(_01_),
    .right(bin_op_sl_solution_c_l50_c66_640a_right)
  );
  bin_op_sl_uint32_t_uint5_t_0clk_295015b8 bin_op_sl_uint32_t_uint5_t_solution_c_l46_l56_duplicate_ae85 (
    .left(bin_op_sl_uint32_t_uint5_t_solution_c_l46_l56_duplicate_ae85_left),
    .return_output(_04_),
    .right(bin_op_sl_uint32_t_uint5_t_solution_c_l46_l56_duplicate_ae85_right)
  );
  bin_op_sr_uint32_t_uint6_t_0clk_9f6ea3e6 bin_op_sr_solution_c_l46_c66_05f6 (
    .left(bin_op_sr_solution_c_l46_c66_05f6_left),
    .return_output(_15_),
    .right(bin_op_sr_solution_c_l46_c66_05f6_right)
  );
  bin_op_sr_uint32_t_uint5_t_0clk_295015b8 bin_op_sr_uint32_t_uint5_t_solution_c_l60_l50_duplicate_ab24 (
    .left(bin_op_sr_uint32_t_uint5_t_solution_c_l60_l50_duplicate_ab24_left),
    .return_output(_05_),
    .right(bin_op_sr_uint32_t_uint5_t_solution_c_l60_l50_duplicate_ab24_right)
  );
  mux_uint1_t_output_payload_t_stream_t_output_payload_t_stream_t_0clk_de264c78 output_mux_solution_c_l42_c3_bfe2 (
    .cond(output_mux_solution_c_l42_c3_bfe2_cond),
    .\iffalse[data] (output_mux_solution_c_l42_c3_bfe2_iffalse[31:0]),
    .\iffalse[valid] (output_mux_solution_c_l42_c3_bfe2_iffalse[32]),
    .\iftrue[data] (output_mux_solution_c_l42_c3_bfe2_iftrue[31:0]),
    .\iftrue[valid] (output_mux_solution_c_l42_c3_bfe2_iftrue[32]),
    .\return_output[data] (_10_),
    .\return_output[valid] (_11_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 result_mux_solution_c_l43_c5_3592 (
    .cond(result_mux_solution_c_l43_c5_3592_cond),
    .iffalse(result_mux_solution_c_l43_c5_3592_iffalse),
    .iftrue(result_mux_solution_c_l43_c5_3592_iftrue),
    .return_output(_12_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 result_mux_solution_c_l44_c7_bd2b (
    .cond(result_mux_solution_c_l44_c7_bd2b_cond),
    .iffalse(result_mux_solution_c_l44_c7_bd2b_iffalse),
    .iftrue(result_mux_solution_c_l44_c7_bd2b_iftrue),
    .return_output(_13_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 result_mux_solution_c_l54_c7_032b (
    .cond(result_mux_solution_c_l54_c7_032b_cond),
    .iffalse(result_mux_solution_c_l54_c7_032b_iffalse),
    .iftrue(result_mux_solution_c_l54_c7_032b_iftrue),
    .return_output(_03_)
  );
  assign \output  = _09_;
  assign reg_comb_output = output_mux_solution_c_l42_c3_bfe2_return_output;
  assign clk_en_internal = clock_enable;
  assign output_mux_solution_c_l42_c3_bfe2_cond = \global_to_module[input] [39];
  assign output_mux_solution_c_l42_c3_bfe2_iftrue = { 1'h1, result_mux_solution_c_l43_c5_3592_return_output };
  assign output_mux_solution_c_l42_c3_bfe2_iffalse = \output ;
  assign output_mux_solution_c_l42_c3_bfe2_return_output = { _11_, _10_ };
  assign result_mux_solution_c_l43_c5_3592_cond = \global_to_module[input] [38];
  assign result_mux_solution_c_l43_c5_3592_iftrue = result_mux_solution_c_l44_c7_bd2b_return_output;
  assign result_mux_solution_c_l43_c5_3592_iffalse = result_mux_solution_c_l54_c7_032b_return_output;
  assign result_mux_solution_c_l43_c5_3592_return_output = _12_;
  assign result_mux_solution_c_l44_c7_bd2b_cond = \global_to_module[input] [37];
  assign result_mux_solution_c_l44_c7_bd2b_iftrue = bin_op_or_solution_c_l46_c19_27ae_return_output;
  assign result_mux_solution_c_l44_c7_bd2b_iffalse = bin_op_or_solution_c_l50_c19_6eaf_return_output;
  assign result_mux_solution_c_l44_c7_bd2b_return_output = _13_;
  assign bin_op_minus_solution_c_l46_c86_44bd_left = 6'h20;
  assign bin_op_minus_solution_c_l46_c86_44bd_right = \global_to_module[input] [36:32];
  assign bin_op_minus_solution_c_l46_c86_44bd_return_output = _14_;
  assign bin_op_sr_solution_c_l46_c66_05f6_left = \global_to_module[input] [31:0];
  assign bin_op_sr_solution_c_l46_c66_05f6_right = bin_op_minus_solution_c_l46_c86_44bd_return_output;
  assign bin_op_sr_solution_c_l46_c66_05f6_return_output = _15_;
  assign bin_op_or_solution_c_l46_c19_27ae_left = bin_op_sl_uint32_t_uint5_t_solution_c_l46_l56_duplicate_ae85_return_output;
  assign bin_op_or_solution_c_l46_c19_27ae_right = bin_op_sr_solution_c_l46_c66_05f6_return_output;
  assign bin_op_or_solution_c_l46_c19_27ae_return_output = _16_;
  assign bin_op_minus_solution_c_l50_c86_05e0_left = 6'h20;
  assign bin_op_minus_solution_c_l50_c86_05e0_right = \global_to_module[input] [36:32];
  assign bin_op_minus_solution_c_l50_c86_05e0_return_output = _00_;
  assign bin_op_sl_solution_c_l50_c66_640a_left = \global_to_module[input] [31:0];
  assign bin_op_sl_solution_c_l50_c66_640a_right = bin_op_minus_solution_c_l50_c86_05e0_return_output;
  assign bin_op_sl_solution_c_l50_c66_640a_return_output = _01_;
  assign bin_op_or_solution_c_l50_c19_6eaf_left = bin_op_sr_uint32_t_uint5_t_solution_c_l60_l50_duplicate_ab24_return_output;
  assign bin_op_or_solution_c_l50_c19_6eaf_right = bin_op_sl_solution_c_l50_c66_640a_return_output;
  assign bin_op_or_solution_c_l50_c19_6eaf_return_output = _02_;
  assign result_mux_solution_c_l54_c7_032b_cond = \global_to_module[input] [37];
  assign result_mux_solution_c_l54_c7_032b_iftrue = bin_op_sl_uint32_t_uint5_t_solution_c_l46_l56_duplicate_ae85_return_output;
  assign result_mux_solution_c_l54_c7_032b_iffalse = bin_op_sr_uint32_t_uint5_t_solution_c_l60_l50_duplicate_ab24_return_output;
  assign result_mux_solution_c_l54_c7_032b_return_output = _03_;
  assign bin_op_sl_uint32_t_uint5_t_solution_c_l46_l56_duplicate_ae85_left = \global_to_module[input] [31:0];
  assign bin_op_sl_uint32_t_uint5_t_solution_c_l46_l56_duplicate_ae85_right = \global_to_module[input] [36:32];
  assign bin_op_sl_uint32_t_uint5_t_solution_c_l46_l56_duplicate_ae85_return_output = _04_;
  assign bin_op_sr_uint32_t_uint5_t_solution_c_l60_l50_duplicate_ab24_left = \global_to_module[input] [31:0];
  assign bin_op_sr_uint32_t_uint5_t_solution_c_l60_l50_duplicate_ab24_right = \global_to_module[input] [36:32];
  assign bin_op_sr_uint32_t_uint5_t_solution_c_l60_l50_duplicate_ab24_return_output = _05_;
  assign \module_to_global[output]  = _07_;
  assign \module_to_global[input_ready]  = _06_;
endmodule

Timing Analysis

Path 1-12.960 ns

From: i_payload_shift_amount[1]

To: inner/solution_0clk_6064c2b8/_09_[0]$_DFF_P_/D

Data Arrival: 12.830 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`i_payload_shift_amount[1]`
0.000	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$529/A`
0.063	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$529/Y`
0.063	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$531/A`
0.178	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$531/Y`
0.178	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$533/B`
0.391	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$533/Y`
0.391	sky130_fd_sc_hvl__a21o_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$543/A1`
0.751	sky130_fd_sc_hvl__a21o_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$543/X`
0.751	sky130_fd_sc_hvl__a21oi_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$551/A1`
0.993	sky130_fd_sc_hvl__a21oi_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$551/Y`
0.993	sky130_fd_sc_hvl__xor2_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$552/B`
5.435	sky130_fd_sc_hvl__xor2_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$552/X`
5.435	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$487/A`
6.271	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$487/Y`
6.271	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$488/A`
6.683	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$488/Y`
6.683	sky130_fd_sc_hvl__a21oi_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$508/A1`
6.964	sky130_fd_sc_hvl__a21oi_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$508/Y`
6.964	sky130_fd_sc_hvl__a22o_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$516/B2`
7.322	sky130_fd_sc_hvl__a22o_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$516/X`
7.322	sky130_fd_sc_hvl__nand3_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$517/A`
7.428	sky130_fd_sc_hvl__nand3_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$517/Y`
7.428	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$518/A`
7.556	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$518/Y`
7.556	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09/$abc$786$auto$blifparse.cc:396:parse_blif$788/A`
7.652	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09/$abc$786$auto$blifparse.cc:396:parse_blif$788/Y`
7.652	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09/$abc$786$auto$blifparse.cc:396:parse_blif$789/B1`
10.950	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09/$abc$786$auto$blifparse.cc:396:parse_blif$789/Y`
10.950	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_8366/$abc$790$auto$blifparse.cc:396:parse_blif$793/A1`
11.610	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_8366/$abc$790$auto$blifparse.cc:396:parse_blif$793/Y`
11.610	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_6064c2b8/bin_op_or_solution_c_l50_c19_6eaf/$abc$574$auto$blifparse.cc:396:parse_blif$576/A`
11.750	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_6064c2b8/bin_op_or_solution_c_l50_c19_6eaf/$abc$574$auto$blifparse.cc:396:parse_blif$576/Y`
11.750	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_or_solution_c_l50_c19_6eaf/$abc$574$auto$blifparse.cc:396:parse_blif$577/B`
11.870	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_or_solution_c_l50_c19_6eaf/$abc$574$auto$blifparse.cc:396:parse_blif$577/Y`
11.870	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l44_c7_bd2b/$abc$790$auto$blifparse.cc:396:parse_blif$791/A`
11.950	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l44_c7_bd2b/$abc$790$auto$blifparse.cc:396:parse_blif$791/Y`
11.950	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l44_c7_bd2b/$abc$790$auto$blifparse.cc:396:parse_blif$793/A2`
12.130	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l44_c7_bd2b/$abc$790$auto$blifparse.cc:396:parse_blif$793/Y`
12.130	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l43_c5_3592/$abc$790$auto$blifparse.cc:396:parse_blif$792/A`
12.260	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l43_c5_3592/$abc$790$auto$blifparse.cc:396:parse_blif$792/Y`
12.260	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l43_c5_3592/$abc$790$auto$blifparse.cc:396:parse_blif$793/B1`
12.370	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l43_c5_3592/$abc$790$auto$blifparse.cc:396:parse_blif$793/Y`
12.370	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/output_mux_solution_c_l42_c3_bfe2/$abc$686$auto$blifparse.cc:396:parse_blif$688/A`
12.500	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/output_mux_solution_c_l42_c3_bfe2/$abc$686$auto$blifparse.cc:396:parse_blif$688/Y`
12.500	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/output_mux_solution_c_l42_c3_bfe2/$abc$686$auto$blifparse.cc:396:parse_blif$689/B1`
12.610	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/output_mux_solution_c_l42_c3_bfe2/$abc$686$auto$blifparse.cc:396:parse_blif$689/Y`
12.610	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/$abc$888$auto$blifparse.cc:396:parse_blif$890/A`
12.740	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/$abc$888$auto$blifparse.cc:396:parse_blif$890/Y`
12.740	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/$abc$888$auto$blifparse.cc:396:parse_blif$891/B1`
12.830	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/$abc$888$auto$blifparse.cc:396:parse_blif$891/Y`
12.830	sky130_fd_sc_hvl__dfxtp_1	`inner/solution_0clk_6064c2b8/_09_[0]$_DFF_P_/D`

Path 2-12.930 ns

From: i_payload_shift_amount[1]

To: inner/solution_0clk_6064c2b8/_09_[10]$_DFF_P_/D

Data Arrival: 12.800 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`i_payload_shift_amount[1]`
0.000	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$529/A`
0.063	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$529/Y`
0.063	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$531/A`
0.178	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$531/Y`
0.178	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$533/B`
0.391	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$533/Y`
0.391	sky130_fd_sc_hvl__a21o_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$543/A1`
0.751	sky130_fd_sc_hvl__a21o_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$543/X`
0.751	sky130_fd_sc_hvl__a21oi_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$551/A1`
0.993	sky130_fd_sc_hvl__a21oi_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$551/Y`
0.993	sky130_fd_sc_hvl__xor2_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$552/B`
5.435	sky130_fd_sc_hvl__xor2_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$552/X`
5.435	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$487/A`
6.271	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$487/Y`
6.271	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$488/A`
6.683	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$488/Y`
6.683	sky130_fd_sc_hvl__a21oi_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$508/A1`
6.964	sky130_fd_sc_hvl__a21oi_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$508/Y`
6.964	sky130_fd_sc_hvl__a22o_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$516/B2`
7.322	sky130_fd_sc_hvl__a22o_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$516/X`
7.322	sky130_fd_sc_hvl__nand3_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$517/A`
7.428	sky130_fd_sc_hvl__nand3_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$517/Y`
7.428	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$518/A`
7.556	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$518/Y`
7.556	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09/$abc$786$auto$blifparse.cc:396:parse_blif$788/A`
7.652	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09/$abc$786$auto$blifparse.cc:396:parse_blif$788/Y`
7.652	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09/$abc$786$auto$blifparse.cc:396:parse_blif$789/B1`
10.950	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09/$abc$786$auto$blifparse.cc:396:parse_blif$789/Y`
10.950	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_8366/$abc$790$auto$blifparse.cc:396:parse_blif$823/A1`
11.610	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_8366/$abc$790$auto$blifparse.cc:396:parse_blif$823/Y`
11.610	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_6064c2b8/bin_op_or_solution_c_l50_c19_6eaf/$abc$574$auto$blifparse.cc:396:parse_blif$606/A`
11.750	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_6064c2b8/bin_op_or_solution_c_l50_c19_6eaf/$abc$574$auto$blifparse.cc:396:parse_blif$606/Y`
11.750	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_or_solution_c_l50_c19_6eaf/$abc$574$auto$blifparse.cc:396:parse_blif$607/B`
11.870	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_or_solution_c_l50_c19_6eaf/$abc$574$auto$blifparse.cc:396:parse_blif$607/Y`
11.870	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l44_c7_bd2b/$abc$790$auto$blifparse.cc:396:parse_blif$821/A`
11.950	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l44_c7_bd2b/$abc$790$auto$blifparse.cc:396:parse_blif$821/Y`
11.950	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l44_c7_bd2b/$abc$790$auto$blifparse.cc:396:parse_blif$823/A2`
12.120	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l44_c7_bd2b/$abc$790$auto$blifparse.cc:396:parse_blif$823/Y`
12.120	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l43_c5_3592/$abc$790$auto$blifparse.cc:396:parse_blif$822/B`
12.250	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l43_c5_3592/$abc$790$auto$blifparse.cc:396:parse_blif$822/Y`
12.250	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l43_c5_3592/$abc$790$auto$blifparse.cc:396:parse_blif$823/B1`
12.350	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l43_c5_3592/$abc$790$auto$blifparse.cc:396:parse_blif$823/Y`
12.350	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/output_mux_solution_c_l42_c3_bfe2/$abc$686$auto$blifparse.cc:396:parse_blif$718/B`
12.490	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/output_mux_solution_c_l42_c3_bfe2/$abc$686$auto$blifparse.cc:396:parse_blif$718/Y`
12.490	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/output_mux_solution_c_l42_c3_bfe2/$abc$686$auto$blifparse.cc:396:parse_blif$719/B1`
12.590	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/output_mux_solution_c_l42_c3_bfe2/$abc$686$auto$blifparse.cc:396:parse_blif$719/Y`
12.590	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/$abc$888$auto$blifparse.cc:396:parse_blif$920/B`
12.720	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/$abc$888$auto$blifparse.cc:396:parse_blif$920/Y`
12.720	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/$abc$888$auto$blifparse.cc:396:parse_blif$921/B1`
12.800	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/$abc$888$auto$blifparse.cc:396:parse_blif$921/Y`
12.800	sky130_fd_sc_hvl__dfxtp_1	`inner/solution_0clk_6064c2b8/_09_[10]$_DFF_P_/D`

Path 3-12.930 ns

From: i_payload_shift_amount[1]

To: inner/solution_0clk_6064c2b8/_09_[11]$_DFF_P_/D

Data Arrival: 12.800 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`i_payload_shift_amount[1]`
0.000	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$529/A`
0.063	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$529/Y`
0.063	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$531/A`
0.178	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$531/Y`
0.178	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$533/B`
0.391	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$533/Y`
0.391	sky130_fd_sc_hvl__a21o_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$543/A1`
0.751	sky130_fd_sc_hvl__a21o_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$543/X`
0.751	sky130_fd_sc_hvl__a21oi_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$551/A1`
0.993	sky130_fd_sc_hvl__a21oi_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$551/Y`
0.993	sky130_fd_sc_hvl__xor2_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$552/B`
5.435	sky130_fd_sc_hvl__xor2_1	`inner/solution_0clk_6064c2b8/bin_op_minus_solution_c_l50_c86_05e0/$abc$527$auto$blifparse.cc:396:parse_blif$552/X`
5.435	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$487/A`
6.271	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$487/Y`
6.271	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$488/A`
6.683	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$488/Y`
6.683	sky130_fd_sc_hvl__a21oi_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$508/A1`
6.964	sky130_fd_sc_hvl__a21oi_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$508/Y`
6.964	sky130_fd_sc_hvl__a22o_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$516/B2`
7.322	sky130_fd_sc_hvl__a22o_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$516/X`
7.322	sky130_fd_sc_hvl__nand3_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$517/A`
7.428	sky130_fd_sc_hvl__nand3_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$517/Y`
7.428	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$518/A`
7.556	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_6f3a/$abc$463$auto$blifparse.cc:396:parse_blif$518/Y`
7.556	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09/$abc$786$auto$blifparse.cc:396:parse_blif$788/A`
7.652	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09/$abc$786$auto$blifparse.cc:396:parse_blif$788/Y`
7.652	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09/$abc$786$auto$blifparse.cc:396:parse_blif$789/B1`
10.950	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_20aa/rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_fb09/$abc$786$auto$blifparse.cc:396:parse_blif$789/Y`
10.950	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_8366/$abc$790$auto$blifparse.cc:396:parse_blif$826/A1`
11.610	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/bin_op_sl_solution_c_l50_c66_640a/rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_8366/$abc$790$auto$blifparse.cc:396:parse_blif$826/Y`
11.610	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_6064c2b8/bin_op_or_solution_c_l50_c19_6eaf/$abc$574$auto$blifparse.cc:396:parse_blif$609/A`
11.750	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_6064c2b8/bin_op_or_solution_c_l50_c19_6eaf/$abc$574$auto$blifparse.cc:396:parse_blif$609/Y`
11.750	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_or_solution_c_l50_c19_6eaf/$abc$574$auto$blifparse.cc:396:parse_blif$610/B`
11.870	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/bin_op_or_solution_c_l50_c19_6eaf/$abc$574$auto$blifparse.cc:396:parse_blif$610/Y`
11.870	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l44_c7_bd2b/$abc$790$auto$blifparse.cc:396:parse_blif$824/A`
11.950	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l44_c7_bd2b/$abc$790$auto$blifparse.cc:396:parse_blif$824/Y`
11.950	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l44_c7_bd2b/$abc$790$auto$blifparse.cc:396:parse_blif$826/A2`
12.120	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l44_c7_bd2b/$abc$790$auto$blifparse.cc:396:parse_blif$826/Y`
12.120	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l43_c5_3592/$abc$790$auto$blifparse.cc:396:parse_blif$825/B`
12.250	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l43_c5_3592/$abc$790$auto$blifparse.cc:396:parse_blif$825/Y`
12.250	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l43_c5_3592/$abc$790$auto$blifparse.cc:396:parse_blif$826/B1`
12.350	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/result_mux_solution_c_l43_c5_3592/$abc$790$auto$blifparse.cc:396:parse_blif$826/Y`
12.350	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/output_mux_solution_c_l42_c3_bfe2/$abc$686$auto$blifparse.cc:396:parse_blif$721/B`
12.490	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/output_mux_solution_c_l42_c3_bfe2/$abc$686$auto$blifparse.cc:396:parse_blif$721/Y`
12.490	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/output_mux_solution_c_l42_c3_bfe2/$abc$686$auto$blifparse.cc:396:parse_blif$722/B1`
12.590	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/output_mux_solution_c_l42_c3_bfe2/$abc$686$auto$blifparse.cc:396:parse_blif$722/Y`
12.590	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/$abc$888$auto$blifparse.cc:396:parse_blif$923/B`
12.720	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_6064c2b8/$abc$888$auto$blifparse.cc:396:parse_blif$923/Y`
12.720	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/$abc$888$auto$blifparse.cc:396:parse_blif$924/B1`
12.800	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_6064c2b8/$abc$888$auto$blifparse.cc:396:parse_blif$924/Y`
12.800	sky130_fd_sc_hvl__dfxtp_1	`inner/solution_0clk_6064c2b8/_09_[11]$_DFF_P_/D`

Post-Synthesis Verilog

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