SpinalHDL
|
|---|
| 1 | piasa-dev | Verilog | 6.13 (1 cycles) | 163.11 (100.0%) | 6859 | 99.57 |
| 2 | Julian Kemmerer | PipelineC | 8.28 (1 cycles) | 120.76 (100.0%) | 26631 | 90.16 |
| 3 | aej | VHDL | 11.26 (1 cycles) | 88.80 (100.0%) | 15797 | 89.71 |
| 4 | ciccio-87 | PipelineC | 12.96 (1 cycles) | 77.15 (100.0%) | 30935 | 85.13 |