SpinalHDL
|
|---|
| 1 | piasa-dev | Verilog | 6.13 (1 cycles) | 163.11 (100.0%) | 6859 | 94.59 |
| 2 | CoHDL | Verilog | 7.58 (1 cycles) | 131.91 (100.0%) | 31054 | 85.29 |
| 3 | Julian Kemmerer | PipelineC | 8.28 (1 cycles) | 120.76 (100.0%) | 26631 | 85.18 |
| 4 | JLNuijens | SpinalHDL | 9.24 (2 cycles) | 108.20 (50.0%) | 7869 | 89.98 |
| 5 | Kishore | Verilog | 10.98 (1 cycles) | 91.07 (100.0%) | 16543 | 84.75 |
| 6 | aej | VHDL | 11.26 (1 cycles) | 88.80 (100.0%) | 15797 | 84.73 |
| 7 | ciccio-87 | PipelineC | 12.96 (1 cycles) | 77.15 (100.0%) | 30935 | 80.15 |