Barrel Shifter - Latchup

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Submission #11

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Submitted Solution

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready,
  input wire i_valid,
  input wire [32-1:0] i_payload_data,
  input wire [5-1:0] i_payload_shift_amount,
  input wire [1-1:0] i_payload_direction,
  input wire [1-1:0] i_payload_rotate,
  output wire [32-1:0] o_payload,
  output wire o_valid
);

// Define your design here
// this one was just for fun.  at least originally.  that missing ready was annoying.
  
// D X | amt' = amt.  left rotate/shift
// X D | amt' = 32-amt.  SR0 becomes an issue since X might not D.

// this is the basic shifter in a few lines.  probably can do better.
  
// this uses the trick of making an extended vector and then masking/indexing it.
//
// I'm mainly submitting this to show how extending vectors in what seems like 
// trivial manners can be very useful in logic design.
// technically, this only needs to be 63 bits.  you can't shift a full 32 spaces with a 4b shift input.
wire left_mask = i_payload_rotate || i_payload_direction;
wire right_mask = i_payload_rotate || !i_payload_direction;
wire [63:0] ext = {i_payload_data, i_payload_data} 
                  & {{(32){left_mask}}, {(32){right_mask}}};

// shift amount changes based on direction.  this is more obvious for rotate where rotl 1 = rotr 31.
wire [4:0] shift_amt = i_payload_direction 
  ? i_payload_shift_amount 
  : (~i_payload_shift_amount + 1);
  
// synthesis tools should already understand what a mux is and have a decent implementation.
// at least for the case where shift granularity is 1.
//
// not sure where the best place to correct for shift-right-0.  i placed it here since the
// result is used very late in the path.  but this can also be done in the "left_mask" expression.
assign o_payload = (i_payload_shift_amount)
                   ? ext[63-shift_amt-:32]
                  : i_payload_data; // handle SR0 

// this is a combinatorial version.  you can easily pipeline muxes if you want the higher throughput.
// tools probably support ext[63-shift_amt[4:2]*4-:36] for the first stage.
// then [35-shift_amt_d[1:0]-:32] for the second.  note that the above used 64b for convenience
// but only needed 63b.  a 4b value maxes out at 31.  so (63-31)-:32 = 32:1.
// and then the stages are 16, 24, 28, 30, 31 bits smaller.  which is why the example for pipeline
// used a number other than -:32 in an intermediate stage.
assign o_valid = i_valid;
assign i_ready = ~reset; // this was the line I forgot.

endmodule

Generated Verilog

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready,
  input wire i_valid,
  input wire [32-1:0] i_payload_data,
  input wire [5-1:0] i_payload_shift_amount,
  input wire [1-1:0] i_payload_direction,
  input wire [1-1:0] i_payload_rotate,
  output wire [32-1:0] o_payload,
  output wire o_valid
);

// Define your design here
// this one was just for fun.  at least originally.  that missing ready was annoying.
  
// D X | amt' = amt.  left rotate/shift
// X D | amt' = 32-amt.  SR0 becomes an issue since X might not D.

// this is the basic shifter in a few lines.  probably can do better.
  
// this uses the trick of making an extended vector and then masking/indexing it.
//
// I'm mainly submitting this to show how extending vectors in what seems like 
// trivial manners can be very useful in logic design.
// technically, this only needs to be 63 bits.  you can't shift a full 32 spaces with a 4b shift input.
wire left_mask = i_payload_rotate || i_payload_direction;
wire right_mask = i_payload_rotate || !i_payload_direction;
wire [63:0] ext = {i_payload_data, i_payload_data} 
                  & {{(32){left_mask}}, {(32){right_mask}}};

// shift amount changes based on direction.  this is more obvious for rotate where rotl 1 = rotr 31.
wire [4:0] shift_amt = i_payload_direction 
  ? i_payload_shift_amount 
  : (~i_payload_shift_amount + 1);
  
// synthesis tools should already understand what a mux is and have a decent implementation.
// at least for the case where shift granularity is 1.
//
// not sure where the best place to correct for shift-right-0.  i placed it here since the
// result is used very late in the path.  but this can also be done in the "left_mask" expression.
assign o_payload = (i_payload_shift_amount)
                   ? ext[63-shift_amt-:32]
                  : i_payload_data; // handle SR0 

// this is a combinatorial version.  you can easily pipeline muxes if you want the higher throughput.
// tools probably support ext[63-shift_amt[4:2]*4-:36] for the first stage.
// then [35-shift_amt_d[1:0]-:32] for the second.  note that the above used 64b for convenience
// but only needed 63b.  a 4b value maxes out at 31.  so (63-31)-:32 = 32:1.
// and then the stages are 16, 24, 28, 30, 31 bits smaller.  which is why the example for pipeline
// used a number other than -:32 in an intermediate stage.
assign o_valid = i_valid;
assign i_ready = ~reset; // this was the line I forgot.

endmodule

Timing Analysis

Path 1-6.128 ns

From: i_payload_shift_amount[1]

To: o_payload[11]

Data Arrival: 6.129 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`i_payload_shift_amount[1]`
0.000	sky130_fd_sc_hvl__or3_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2665/A`
0.803	sky130_fd_sc_hvl__or3_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2665/X`
0.803	sky130_fd_sc_hvl__o21ai_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2667/A2`
1.074	sky130_fd_sc_hvl__o21ai_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2667/Y`
1.074	sky130_fd_sc_hvl__xnor2_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2668/B`
3.736	sky130_fd_sc_hvl__xnor2_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2668/Y`
3.736	sky130_fd_sc_hvl__mux4_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2849/S0`
5.625	sky130_fd_sc_hvl__mux4_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2849/X`
5.625	sky130_fd_sc_hvl__mux2_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2850/A0`
6.129	sky130_fd_sc_hvl__mux2_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2850/X`
6.129	Solution	`o_payload[11]`

Path 2-6.128 ns

From: i_payload_shift_amount[1]

To: o_payload[13]

Data Arrival: 6.129 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`i_payload_shift_amount[1]`
0.000	sky130_fd_sc_hvl__or3_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2665/A`
0.803	sky130_fd_sc_hvl__or3_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2665/X`
0.803	sky130_fd_sc_hvl__o21ai_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2667/A2`
1.074	sky130_fd_sc_hvl__o21ai_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2667/Y`
1.074	sky130_fd_sc_hvl__xnor2_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2668/B`
3.736	sky130_fd_sc_hvl__xnor2_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2668/Y`
3.736	sky130_fd_sc_hvl__mux4_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2860/S0`
5.625	sky130_fd_sc_hvl__mux4_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2860/X`
5.625	sky130_fd_sc_hvl__mux2_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2861/A0`
6.129	sky130_fd_sc_hvl__mux2_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2861/X`
6.129	Solution	`o_payload[13]`

Path 3-6.128 ns

From: i_payload_shift_amount[1]

To: o_payload[15]

Data Arrival: 6.129 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`i_payload_shift_amount[1]`
0.000	sky130_fd_sc_hvl__or3_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2665/A`
0.803	sky130_fd_sc_hvl__or3_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2665/X`
0.803	sky130_fd_sc_hvl__o21ai_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2667/A2`
1.074	sky130_fd_sc_hvl__o21ai_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2667/Y`
1.074	sky130_fd_sc_hvl__xnor2_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2668/B`
3.736	sky130_fd_sc_hvl__xnor2_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2668/Y`
3.736	sky130_fd_sc_hvl__mux4_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2871/S0`
5.625	sky130_fd_sc_hvl__mux4_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2871/X`
5.625	sky130_fd_sc_hvl__mux2_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2872/A0`
6.129	sky130_fd_sc_hvl__mux2_1	`$abc$2661$auto$blifparse.cc:396:parse_blif$2872/X`
6.129	Solution	`o_payload[15]`

Post-Synthesis Verilog

Download synth.v