Barrel Shifter - Latchup

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Submitted Solution

// PipelineC solution template.
#include "uintN_t.h"
#include "intN_t.h"
#include "stream/stream.h"

// Input stream interface:
//   input.valid (input): Asserted when input data is valid
//   input.data.* (input): Input payload fields
//   input_ready (output): Assert when ready to accept input
//
// Output flow interface (no backpressure):
//   output.valid (output): Assert when output data is valid
//   output.data.* (output): Output payload fields

typedef struct input_payload_t {
  uint32_t data;
  uint5_t shift_amount;
  uint1_t direction;
  uint1_t rotate;
} input_payload_t;
DECL_STREAM_TYPE(input_payload_t)

typedef struct output_payload_t {
  uint32_t result;
} output_payload_t;
DECL_STREAM_TYPE(output_payload_t)

DECL_INPUT(stream(input_payload_t), input)
DECL_OUTPUT(uint1_t, input_ready)

DECL_OUTPUT(stream(output_payload_t), output)

#define CLK_RATE_MHZ 175 // ~ 1 stage pipeline given current timing model estimates
DECL_INPUT(uint1_t, clk)
CLK_MHZ(clk, CLK_RATE_MHZ)
MAIN_MHZ(solution, CLK_RATE_MHZ)
  
// See: https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Latchup-Solutions

// Some rotate functions Google spit out - yes, not efficient.
#define UINT_BITS 32
uint32_t leftRotate(uint32_t n, uint5_t d) {
    return (n << d) | (n >> (UINT_BITS - d));
}
uint32_t rightRotate(uint32_t n, uint5_t d) {
    return (n >> d) | (n << (UINT_BITS - d));
}

uint32_t latchup_rotate(input_payload_t i) {
  uint32_t rv = i.data;
  if(i.rotate){
    if(i.direction){
      rv = leftRotate(rv, i.shift_amount);
    }else{
      rv = rightRotate(rv, i.shift_amount);
    }
  }else{
    if(i.direction){
      rv = rv << i.shift_amount; 
    }else{
      rv = rv >> i.shift_amount; 
    }
  }
  return rv;
}
  
void solution()
{
  output.valid = input.valid;
  output.data.result = latchup_rotate(input.data);
  input_ready = 1;
}

Compile Log

/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:7114: SyntaxWarning: invalid escape sequence '\/'
  
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:7485: SyntaxWarning: invalid escape sequence '\d'
  )
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10680: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + "_WRITE" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10680: SyntaxWarning: invalid escape sequence '\s'
  r = f"\w+" + "_WRITE" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10682: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + "_WRITE_[0-9]+" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10682: SyntaxWarning: invalid escape sequence '\s'
  r = f"\w+" + "_WRITE_[0-9]+" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10688: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + "_READ" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10688: SyntaxWarning: invalid escape sequence '\s'
  r = f"\w+" + "_READ" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10690: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + "_READ_[0-9]+" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/C_TO_LOGIC.py:10690: SyntaxWarning: invalid escape sequence '\s'
  r = f"\w+" + "_READ_[0-9]+" + f"\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:272: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_SINGLE_INST.h"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:348: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_array(_[0-9]+)+_t"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:374: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_array_N_t.h"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:404: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_bytes_t.h"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:434: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + C_TO_FSM.FSM_EXT + ".h"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:526: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+" + C_TO_FSM.FSM_EXT
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:598: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_bytes_t"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:652: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_bytes_t"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:1469: SyntaxWarning: invalid escape sequence '\w'
  r = f"\w+_array_[0-9]+_t"
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:1902: SyntaxWarning: invalid escape sequence '\s'
  for type_regex in [f"uint[0-9]+_negate\s?\("]:  # DO int,float negate?
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:1963: SyntaxWarning: invalid escape sequence '\s'
  for type_regex in [f"int[0-9]+_abs\s?\("]:  # Float abs is bit manip func
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2049: SyntaxWarning: invalid escape sequence '\w'
  for type_regex in [f"\w+_mux[0-9]+\s?\("]:
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2245: SyntaxWarning: invalid escape sequence '\s'
  for type_regex in [f"count0s_uint[0-9]+\s?\("]:
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2474: SyntaxWarning: invalid escape sequence '\s'
  regex = type_regex + "_" + op_regex + f"[0-9]+\s?\("
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2841: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_[0-9]+_[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2877: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"u?int[0-9]+_u?int[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2915: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"[^_][u?]int[0-9]+_[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2955: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"[^_]rotl[0-9]+_[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:2988: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"[^_]rotr[0-9]+_[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:3023: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"u?int[0-9]+_uint[0-9]+_[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:3064: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_uint[0-9]+_uint[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:3110: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_uint[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:3147: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_abs\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:3183: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(type_regex + f"_sign\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:3215: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"bswap_[0-9]+\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SW_LIB.py:3249: SyntaxWarning: invalid escape sequence '\s'
  p = re.compile(f"uint[0-9]+_array[0-9]+_(?:be|le)\s?\(")
/nix/store/n38cf7i8ji5qxq74vjiiqs4p8qx3qkv3-pipelinec-unstable-2026-03-05/lib/pipelinec/src/SYN.py:1183: SyntaxWarning: invalid escape sequence '\/'
  

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Output directory: /submission/user/pipelinec_output
================== Parsing C Code to Logical Hierarchy ================================
Parsing: /submission/user/Solution.c
Preprocessing file...
Parsing C syntax...
Parsing non-function definitions...
Parsing derived fsm logic functions...
Doing old-style code generation based on PipelineC supported text patterns...
Elaborating function dataflow...
Defaulting to pyrtl based timing estimates...
Using PYRTL synthesizing for part: None
Elaborating dataflow of function: leftRotate
Elaborating dataflow of function: rightRotate
Elaborating dataflow of function: latchup_rotate
Elaborating dataflow of function: solution
Elaborating user function hierarchies down to raw HDL logic...
... found: BIN_OP_SL_uint32_t_uint5_t
... found: BIN_OP_SR_uint32_t_uint6_t
... found: BIN_OP_GT_uint6_t_uint5_t
... found: BIN_OP_SR_uint32_t_uint5_t
... found: BIN_OP_SL_uint32_t_uint6_t
Doing obvious logic trimming/collapsing...
Writing generated PipelineC code from elaboration to output directories...
Writing cache of parsed information to file...
================== Writing Resulting Logic to File ================================
Writing output files before adding pipelining...
Writing log of integer module instances: /submission/user/pipelinec_output/integer_module_instances.log
Writing VHDL files for all functions (before any added pipelining)...
Writing multi main top level files...
Writing the constant struct+enum definitions as defined from C code...
Writing global wire definitions as parsed from C code...
================== Adding Timing Information from Synthesis Tool ================================
Synthesizing before pipelining to get path delays...

Synthesizing function: MUX_uint1_t_uint32_t_uint32_t
Synthesizing function: BIN_OP_SL_uint32_t_uint5_t
Synthesizing function: BIN_OP_MINUS_uint6_t_uint5_t
Synthesizing function: BIN_OP_EQ_uint1_t_uint1_t
Synthesizing function: MUX_uint1_t_uint1_t_uint1_t
Synthesizing function: BIN_OP_MINUS_int6_t_int6_t
Synthesizing function: BIN_OP_GT_uint6_t_uint5_t
Running: /submission/user/pipelinec_output/built_in/MUX_uint1_t_uint32_t_uint32_t/pyrtl_0CLK_de264c78.log
Synthesizing function: BIN_OP_SR_uint32_t_uint6_t
Synthesizing function: BIN_OP_OR_uint32_t_uint32_t
Synthesizing function: leftRotate
Synthesizing function: BIN_OP_SR_uint32_t_uint5_t
Synthesizing function: BIN_OP_SL_uint32_t_uint6_t
Synthesizing function: rightRotate
Synthesizing function: latchup_rotate
Synthesizing function: solution
Running: /submission/user/pipelinec_output/built_in/BIN_OP_SL_uint32_t_uint5_t/pyrtl_0CLK_295015b8.log
Function 27/41, elapsed time 0:00:14.873797...
...Waiting on synthesis for: MUX_uint1_t_uint32_t_uint32_t
Running: /submission/user/pipelinec_output/built_in/BIN_OP_EQ_uint1_t_uint1_t/pyrtl_0CLK_de264c78.log
Running: /submission/user/pipelinec_output/built_in/BIN_OP_MINUS_uint6_t_uint5_t/pyrtl_0CLK_de264c78.log
Running: /submission/user/pipelinec_output/built_in/MUX_uint1_t_uint1_t_uint1_t/pyrtl_0CLK_de264c78.log
Running: /submission/user/pipelinec_output/built_in/BIN_OP_MINUS_int6_t_int6_t/pyrtl_0CLK_de264c78.log
MUX_uint1_t_uint32_t_uint32_t Path delay (maybe to be pipelined): 0.505 ns
Function 28/41, elapsed time 0:00:15.944479...
...Waiting on synthesis for: BIN_OP_SL_uint32_t_uint5_t
Running: /submission/user/pipelinec_output/built_in/BIN_OP_GT_uint6_t_uint5_t/pyrtl_0CLK_5af1a430.log
Running: /submission/user/pipelinec_output/built_in/BIN_OP_SR_uint32_t_uint6_t/pyrtl_0CLK_9f6ea3e6.log
Running: /submission/user/pipelinec_output/built_in/BIN_OP_OR_uint32_t_uint32_t/pyrtl_0CLK_de264c78.log
BIN_OP_SL_uint32_t_uint5_t Path delay (maybe to be pipelined): 2.135 ns
Function 29/41, elapsed time 0:00:16.802773...
...Waiting on synthesis for: BIN_OP_MINUS_uint6_t_uint5_t
BIN_OP_MINUS_uint6_t_uint5_t Path delay (maybe to be pipelined): 2.261 ns
Function 30/41, elapsed time 0:00:16.803427...
...Waiting on synthesis for: BIN_OP_EQ_uint1_t_uint1_t
BIN_OP_EQ_uint1_t_uint1_t Path delay (maybe to be pipelined): 0.505 ns
Running: /submission/user/pipelinec_output/leftRotate/pyrtl_0CLK_5bc0299e.log
Function 31/41, elapsed time 0:00:16.803776...
...Waiting on synthesis for: MUX_uint1_t_uint1_t_uint1_t
MUX_uint1_t_uint1_t_uint1_t Path delay (maybe to be pipelined): 0.505 ns
Function 32/41, elapsed time 0:00:16.804050...
...Waiting on synthesis for: BIN_OP_MINUS_int6_t_int6_t
BIN_OP_MINUS_int6_t_int6_t Path delay (maybe to be pipelined): 2.261 ns
Function 33/41, elapsed time 0:00:16.804363...
...Waiting on synthesis for: BIN_OP_GT_uint6_t_uint5_t
BIN_OP_GT_uint6_t_uint5_t Path delay (maybe to be pipelined): 2.669 ns
Function 34/41, elapsed time 0:00:17.030005...
...Waiting on synthesis for: BIN_OP_SR_uint32_t_uint6_t
Running: /submission/user/pipelinec_output/built_in/BIN_OP_SR_uint32_t_uint5_t/pyrtl_0CLK_295015b8.log
Running: /submission/user/pipelinec_output/built_in/BIN_OP_SL_uint32_t_uint6_t/pyrtl_0CLK_91f7f59e.log
BIN_OP_SR_uint32_t_uint6_t Path delay (maybe to be pipelined): 3.174 ns
Function 35/41, elapsed time 0:00:18.832693...
...Waiting on synthesis for: BIN_OP_OR_uint32_t_uint32_t
BIN_OP_OR_uint32_t_uint32_t Path delay (maybe to be pipelined): 0.211 ns
Function 36/41, elapsed time 0:00:18.833248...
...Waiting on synthesis for: leftRotate
Running: /submission/user/pipelinec_output/rightRotate/pyrtl_0CLK_cbe809a7.log
Running: /submission/user/pipelinec_output/latchup_rotate/pyrtl_0CLK_1bbb502d.log
Running: /submission/user/pipelinec_output/solution/pyrtl_0CLK_83914a8b.log
leftRotate Path delay (maybe to be pipelined): 4.723 ns
Function 37/41, elapsed time 0:00:20.730711...
...Waiting on synthesis for: BIN_OP_SR_uint32_t_uint5_t
BIN_OP_SR_uint32_t_uint5_t Path delay (maybe to be pipelined): 2.135 ns
Function 38/41, elapsed time 0:00:20.730949...
...Waiting on synthesis for: BIN_OP_SL_uint32_t_uint6_t
BIN_OP_SL_uint32_t_uint6_t Path delay (maybe to be pipelined): 3.174 ns
Function 39/41, elapsed time 0:00:20.731122...
...Waiting on synthesis for: rightRotate
rightRotate Path delay (maybe to be pipelined): 4.723 ns
Function 40/41, elapsed time 0:00:23.375571...
...Waiting on synthesis for: latchup_rotate
latchup_rotate Path delay (maybe to be pipelined): 5.538 ns
Function 41/41, elapsed time 0:00:26.915182...
...Waiting on synthesis for: solution
solution Path delay (maybe to be pipelined): 5.538 ns
================== Beginning Throughput Sweep ================================
Function: solution Target MHz: 175.0
Starting with no added pipelining...
Starting with blank sweep state...
Starting middle out sweep...
Starting from timing params without added pipelining...
Collecting modules to pipeline...
Pipelining modules...
Updating output files...
Estimated register usage: /submission/user/pipelinec_output/solution/solution_7184_registers.log
Running syn w timing params...
Elapsed time: 0:00:28.156177...
Running: /submission/user/pipelinec_output/solution/pyrtl_7184.log
solution Clock Goal: 175.00 (MHz) Current: 180.56 (MHz)(5.54 ns) 0 clks
Met timing...
================== Writing Results of Throughput Sweep ================================
Output VHDL files: /submission/user/pipelinec_output/vhdl_files.txt
Done.

Generated Verilog

module Solution(
    input clk,
    input reset,
    input i_valid,
    output i_ready,
    input [31:0] i_payload_data,
    input [4:0] i_payload_shift_amount,
    input i_payload_direction,
    input i_payload_rotate,
    output o_valid,
    output [31:0] o_payload
);

    wire [38:0] input_data;
    assign input_data = { i_payload_rotate, i_payload_direction, i_payload_shift_amount, i_payload_data };

    wire [31:0] output_data;
    wire output_valid;
    wire output_input_ready;

    solution inner(
        .clk(clk),
        .\input[data] (input_data),
        .\input[valid] (i_valid),
        .\output[data] (output_data),
        .\output[valid] (output_valid),
        .input_ready(output_input_ready)
    );

    assign i_ready = output_input_ready;
    assign o_valid = output_valid;
    assign o_payload = output_data[31:0];

endmodule


/* Generated by Yosys 0.55 (git sha1 60f126cd00c94892782470192d6c9f7abebe7c05, g++ 14.3.0 -fPIC -O3) */

module bin_op_eq_uint1_t_uint1_t_0clk_de264c78(left, right, return_output);
  wire _0_;
  wire _1_;
  wire _2_;
  wire [5:0] \:982.read_pipe ;
  input left;
  wire left;
  output return_output;
  wire return_output;
  input right;
  wire right;
  assign _0_ = left == right;
  assign _1_ = _0_ & 1'h1;
  assign _2_ = _1_ ? 1'h1 : 1'h0;
  assign \:982.read_pipe  = { left, right, 4'bx011 };
  assign return_output = _2_;
endmodule

module bin_op_gt_uint6_t_uint5_t_0clk_5af1a430(left, right, return_output);
  wire [5:0] _0_;
  wire _1_;
  wire _2_;
  wire [6:0] _3_;
  wire bin_op_eq_bin_op_gt_uint6_t_uint5_t_c_l15_c6_0414_left;
  wire bin_op_eq_bin_op_gt_uint6_t_uint5_t_c_l15_c6_0414_return_output;
  wire bin_op_eq_bin_op_gt_uint6_t_uint5_t_c_l15_c6_0414_right;
  wire [5:0] bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2_left;
  wire [6:0] bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2_return_output;
  wire [5:0] bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2_right;
  wire [5:0] const_sr_5_bin_op_gt_uint6_t_uint5_t_c_l13_c9_42cd_return_output;
  wire [5:0] const_sr_5_bin_op_gt_uint6_t_uint5_t_c_l13_c9_42cd_x;
  input [5:0] left;
  wire [5:0] left;
  output return_output;
  wire return_output;
  input [4:0] right;
  wire [4:0] right;
  wire rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_8843_cond;
  wire rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_8843_iffalse;
  wire rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_8843_iftrue;
  wire rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_8843_return_output;
  bin_op_eq_uint1_t_uint1_t_0clk_de264c78 bin_op_eq_bin_op_gt_uint6_t_uint5_t_c_l15_c6_0414 (
    .left(bin_op_eq_bin_op_gt_uint6_t_uint5_t_c_l15_c6_0414_left),
    .return_output(_1_),
    .right(bin_op_eq_bin_op_gt_uint6_t_uint5_t_c_l15_c6_0414_right)
  );
  bin_op_minus_int6_t_int6_t_0clk_de264c78 bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2 (
    .left(bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2_left),
    .return_output(_3_),
    .right(bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2_right)
  );
  const_sr_5_uint6_t_0clk_de264c78 const_sr_5_bin_op_gt_uint6_t_uint5_t_c_l13_c9_42cd (
    .return_output(_0_),
    .x(const_sr_5_bin_op_gt_uint6_t_uint5_t_c_l13_c9_42cd_x)
  );
  mux_uint1_t_uint1_t_uint1_t_0clk_de264c78 rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_8843 (
    .cond(rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_8843_cond),
    .iffalse(rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_8843_iffalse),
    .iftrue(rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_8843_iftrue),
    .return_output(_2_)
  );
  assign const_sr_5_bin_op_gt_uint6_t_uint5_t_c_l13_c9_42cd_x = left;
  assign const_sr_5_bin_op_gt_uint6_t_uint5_t_c_l13_c9_42cd_return_output = _0_;
  assign bin_op_eq_bin_op_gt_uint6_t_uint5_t_c_l15_c6_0414_left = const_sr_5_bin_op_gt_uint6_t_uint5_t_c_l13_c9_42cd_return_output[0];
  assign bin_op_eq_bin_op_gt_uint6_t_uint5_t_c_l15_c6_0414_right = 1'h0;
  assign bin_op_eq_bin_op_gt_uint6_t_uint5_t_c_l15_c6_0414_return_output = _1_;
  assign rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_8843_cond = bin_op_eq_bin_op_gt_uint6_t_uint5_t_c_l15_c6_0414_return_output;
  assign rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_8843_iftrue = bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2_return_output[5];
  assign rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_8843_iffalse = 1'h1;
  assign rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_8843_return_output = _2_;
  assign bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2_left = { 1'h0, right };
  assign bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2_right = { 1'h0, left[4:0] };
  assign bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2_return_output = _3_;
  assign return_output = rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_8843_return_output;
endmodule

module bin_op_minus_int6_t_int6_t_0clk_de264c78(left, right, return_output);
  wire [6:0] _0_;
  wire [6:0] _1_;
  wire [57:0] \:1041.read_pipe ;
  input [5:0] left;
  wire [5:0] left;
  output [6:0] return_output;
  wire [6:0] return_output;
  input [5:0] right;
  wire [5:0] right;
  assign _0_ = { left[5], left } - { right[5], right };
  assign _1_ = _0_ - 7'h00;
  assign \:1041.read_pipe  = { left, right, 46'hxxxxxxxxxxxx };
  assign return_output = _1_;
endmodule

module bin_op_minus_uint6_t_uint5_t_0clk_de264c78(left, right, return_output);
  wire [6:0] _0_;
  wire [6:0] _1_;
  wire [54:0] \:383.read_pipe ;
  input [5:0] left;
  wire [5:0] left;
  output [5:0] return_output;
  wire [5:0] return_output;
  input [4:0] right;
  wire [4:0] right;
  assign _0_ = { 1'h0, left } - { 2'h0, right };
  assign _1_ = _0_ - 7'h00;
  assign \:383.read_pipe  = { left, right, 44'hxxxxxxxxxxx };
  assign return_output = _1_[5:0];
endmodule

module bin_op_or_uint32_t_uint32_t_0clk_de264c78(left, right, return_output);
  wire [31:0] _0_;
  wire [159:0] \:567.read_pipe ;
  input [31:0] left;
  wire [31:0] left;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [31:0] right;
  wire [31:0] right;
  assign _0_ = left | right;
  assign \:567.read_pipe  = { left, right, 96'hxxxxxxxxxxxxxxxxxxxxxxxx };
  assign return_output = _0_;
endmodule

module bin_op_sl_uint32_t_uint5_t_0clk_295015b8(left, right, return_output);
  wire [31:0] _0_;
  wire [31:0] _1_;
  wire [31:0] _2_;
  wire [31:0] _3_;
  wire [31:0] _4_;
  wire [31:0] _5_;
  wire [31:0] _6_;
  wire [31:0] _7_;
  wire [31:0] _8_;
  wire [31:0] _9_;
  wire [31:0] const_sl_16_bin_op_sl_uint32_t_uint5_t_c_l22_c55_e8b4_return_output;
  wire [31:0] const_sl_16_bin_op_sl_uint32_t_uint5_t_c_l22_c55_e8b4_x;
  wire [31:0] const_sl_1_bin_op_sl_uint32_t_uint5_t_c_l18_c55_c6db_return_output;
  wire [31:0] const_sl_1_bin_op_sl_uint32_t_uint5_t_c_l18_c55_c6db_x;
  wire [31:0] const_sl_2_bin_op_sl_uint32_t_uint5_t_c_l19_c55_d35d_return_output;
  wire [31:0] const_sl_2_bin_op_sl_uint32_t_uint5_t_c_l19_c55_d35d_x;
  wire [31:0] const_sl_4_bin_op_sl_uint32_t_uint5_t_c_l20_c55_0031_return_output;
  wire [31:0] const_sl_4_bin_op_sl_uint32_t_uint5_t_c_l20_c55_0031_x;
  wire [31:0] const_sl_8_bin_op_sl_uint32_t_uint5_t_c_l21_c55_5229_return_output;
  wire [31:0] const_sl_8_bin_op_sl_uint32_t_uint5_t_c_l21_c55_5229_x;
  input [31:0] left;
  wire [31:0] left;
  wire mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_f621_cond;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_f621_iffalse;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_f621_iftrue;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_f621_return_output;
  wire mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_39c5_cond;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_39c5_iffalse;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_39c5_iftrue;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_39c5_return_output;
  wire mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_3b6b_cond;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_3b6b_iffalse;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_3b6b_iftrue;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_3b6b_return_output;
  wire mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_09fc_cond;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_09fc_iffalse;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_09fc_iftrue;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_09fc_return_output;
  wire mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_db8e_cond;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_db8e_iffalse;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_db8e_iftrue;
  wire [31:0] mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_db8e_return_output;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [4:0] right;
  wire [4:0] right;
  const_sl_16_uint32_t_0clk_de264c78 const_sl_16_bin_op_sl_uint32_t_uint5_t_c_l22_c55_e8b4 (
    .return_output(_8_),
    .x(const_sl_16_bin_op_sl_uint32_t_uint5_t_c_l22_c55_e8b4_x)
  );
  const_sl_1_uint32_t_0clk_de264c78 const_sl_1_bin_op_sl_uint32_t_uint5_t_c_l18_c55_c6db (
    .return_output(_0_),
    .x(const_sl_1_bin_op_sl_uint32_t_uint5_t_c_l18_c55_c6db_x)
  );
  const_sl_2_uint32_t_0clk_de264c78 const_sl_2_bin_op_sl_uint32_t_uint5_t_c_l19_c55_d35d (
    .return_output(_2_),
    .x(const_sl_2_bin_op_sl_uint32_t_uint5_t_c_l19_c55_d35d_x)
  );
  const_sl_4_uint32_t_0clk_de264c78 const_sl_4_bin_op_sl_uint32_t_uint5_t_c_l20_c55_0031 (
    .return_output(_4_),
    .x(const_sl_4_bin_op_sl_uint32_t_uint5_t_c_l20_c55_0031_x)
  );
  const_sl_8_uint32_t_0clk_de264c78 const_sl_8_bin_op_sl_uint32_t_uint5_t_c_l21_c55_5229 (
    .return_output(_6_),
    .x(const_sl_8_bin_op_sl_uint32_t_uint5_t_c_l21_c55_5229_x)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_f621 (
    .cond(mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_f621_cond),
    .iffalse(mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_f621_iffalse),
    .iftrue(mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_f621_iftrue),
    .return_output(_1_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_39c5 (
    .cond(mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_39c5_cond),
    .iffalse(mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_39c5_iffalse),
    .iftrue(mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_39c5_iftrue),
    .return_output(_3_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_3b6b (
    .cond(mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_3b6b_cond),
    .iffalse(mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_3b6b_iffalse),
    .iftrue(mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_3b6b_iftrue),
    .return_output(_5_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_09fc (
    .cond(mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_09fc_cond),
    .iffalse(mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_09fc_iffalse),
    .iftrue(mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_09fc_iftrue),
    .return_output(_7_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_db8e (
    .cond(mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_db8e_cond),
    .iffalse(mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_db8e_iffalse),
    .iftrue(mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_db8e_iftrue),
    .return_output(_9_)
  );
  assign const_sl_1_bin_op_sl_uint32_t_uint5_t_c_l18_c55_c6db_x = left;
  assign const_sl_1_bin_op_sl_uint32_t_uint5_t_c_l18_c55_c6db_return_output = _0_;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_f621_cond = right[0];
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_f621_iftrue = const_sl_1_bin_op_sl_uint32_t_uint5_t_c_l18_c55_c6db_return_output;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_f621_iffalse = left;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_f621_return_output = _1_;
  assign const_sl_2_bin_op_sl_uint32_t_uint5_t_c_l19_c55_d35d_x = mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_f621_return_output;
  assign const_sl_2_bin_op_sl_uint32_t_uint5_t_c_l19_c55_d35d_return_output = _2_;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_39c5_cond = right[1];
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_39c5_iftrue = const_sl_2_bin_op_sl_uint32_t_uint5_t_c_l19_c55_d35d_return_output;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_39c5_iffalse = mux_bin_op_sl_uint32_t_uint5_t_c_l18_c19_f621_return_output;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_39c5_return_output = _3_;
  assign const_sl_4_bin_op_sl_uint32_t_uint5_t_c_l20_c55_0031_x = mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_39c5_return_output;
  assign const_sl_4_bin_op_sl_uint32_t_uint5_t_c_l20_c55_0031_return_output = _4_;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_3b6b_cond = right[2];
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_3b6b_iftrue = const_sl_4_bin_op_sl_uint32_t_uint5_t_c_l20_c55_0031_return_output;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_3b6b_iffalse = mux_bin_op_sl_uint32_t_uint5_t_c_l19_c19_39c5_return_output;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_3b6b_return_output = _5_;
  assign const_sl_8_bin_op_sl_uint32_t_uint5_t_c_l21_c55_5229_x = mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_3b6b_return_output;
  assign const_sl_8_bin_op_sl_uint32_t_uint5_t_c_l21_c55_5229_return_output = _6_;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_09fc_cond = right[3];
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_09fc_iftrue = const_sl_8_bin_op_sl_uint32_t_uint5_t_c_l21_c55_5229_return_output;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_09fc_iffalse = mux_bin_op_sl_uint32_t_uint5_t_c_l20_c19_3b6b_return_output;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_09fc_return_output = _7_;
  assign const_sl_16_bin_op_sl_uint32_t_uint5_t_c_l22_c55_e8b4_x = mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_09fc_return_output;
  assign const_sl_16_bin_op_sl_uint32_t_uint5_t_c_l22_c55_e8b4_return_output = _8_;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_db8e_cond = right[4];
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_db8e_iftrue = const_sl_16_bin_op_sl_uint32_t_uint5_t_c_l22_c55_e8b4_return_output;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_db8e_iffalse = mux_bin_op_sl_uint32_t_uint5_t_c_l21_c19_09fc_return_output;
  assign mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_db8e_return_output = _9_;
  assign return_output = mux_bin_op_sl_uint32_t_uint5_t_c_l22_c19_db8e_return_output;
endmodule

module bin_op_sl_uint32_t_uint6_t_0clk_91f7f59e(left, right, return_output);
  wire _00_;
  wire [31:0] _01_;
  wire [31:0] _02_;
  wire [31:0] _03_;
  wire [31:0] _04_;
  wire [31:0] _05_;
  wire [31:0] _06_;
  wire [31:0] _07_;
  wire [31:0] _08_;
  wire [31:0] _09_;
  wire [31:0] _10_;
  wire [31:0] _11_;
  wire [5:0] bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900_left;
  wire bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900_return_output;
  wire [4:0] bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900_right;
  wire [31:0] const_sl_16_bin_op_sl_uint32_t_uint6_t_c_l30_c55_cf78_return_output;
  wire [31:0] const_sl_16_bin_op_sl_uint32_t_uint6_t_c_l30_c55_cf78_x;
  wire [31:0] const_sl_1_bin_op_sl_uint32_t_uint6_t_c_l26_c55_85c5_return_output;
  wire [31:0] const_sl_1_bin_op_sl_uint32_t_uint6_t_c_l26_c55_85c5_x;
  wire [31:0] const_sl_2_bin_op_sl_uint32_t_uint6_t_c_l27_c55_6e3b_return_output;
  wire [31:0] const_sl_2_bin_op_sl_uint32_t_uint6_t_c_l27_c55_6e3b_x;
  wire [31:0] const_sl_4_bin_op_sl_uint32_t_uint6_t_c_l28_c55_5136_return_output;
  wire [31:0] const_sl_4_bin_op_sl_uint32_t_uint6_t_c_l28_c55_5136_x;
  wire [31:0] const_sl_8_bin_op_sl_uint32_t_uint6_t_c_l29_c55_98a9_return_output;
  wire [31:0] const_sl_8_bin_op_sl_uint32_t_uint6_t_c_l29_c55_98a9_x;
  input [31:0] left;
  wire [31:0] left;
  wire mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_2a99_cond;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_2a99_iffalse;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_2a99_iftrue;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_2a99_return_output;
  wire mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_ccae_cond;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_ccae_iffalse;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_ccae_iftrue;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_ccae_return_output;
  wire mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_ee49_cond;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_ee49_iffalse;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_ee49_iftrue;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_ee49_return_output;
  wire mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_1952_cond;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_1952_iffalse;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_1952_iftrue;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_1952_return_output;
  wire mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_0e19_cond;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_0e19_iffalse;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_0e19_iftrue;
  wire [31:0] mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_0e19_return_output;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [5:0] right;
  wire [5:0] right;
  wire rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_2502_cond;
  wire [31:0] rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_2502_iffalse;
  wire [31:0] rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_2502_iftrue;
  wire [31:0] rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_2502_return_output;
  bin_op_gt_uint6_t_uint5_t_0clk_5af1a430 bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900 (
    .left(bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900_left),
    .return_output(_00_),
    .right(bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900_right)
  );
  const_sl_16_uint32_t_0clk_de264c78 const_sl_16_bin_op_sl_uint32_t_uint6_t_c_l30_c55_cf78 (
    .return_output(_10_),
    .x(const_sl_16_bin_op_sl_uint32_t_uint6_t_c_l30_c55_cf78_x)
  );
  const_sl_1_uint32_t_0clk_de264c78 const_sl_1_bin_op_sl_uint32_t_uint6_t_c_l26_c55_85c5 (
    .return_output(_02_),
    .x(const_sl_1_bin_op_sl_uint32_t_uint6_t_c_l26_c55_85c5_x)
  );
  const_sl_2_uint32_t_0clk_de264c78 const_sl_2_bin_op_sl_uint32_t_uint6_t_c_l27_c55_6e3b (
    .return_output(_04_),
    .x(const_sl_2_bin_op_sl_uint32_t_uint6_t_c_l27_c55_6e3b_x)
  );
  const_sl_4_uint32_t_0clk_de264c78 const_sl_4_bin_op_sl_uint32_t_uint6_t_c_l28_c55_5136 (
    .return_output(_06_),
    .x(const_sl_4_bin_op_sl_uint32_t_uint6_t_c_l28_c55_5136_x)
  );
  const_sl_8_uint32_t_0clk_de264c78 const_sl_8_bin_op_sl_uint32_t_uint6_t_c_l29_c55_98a9 (
    .return_output(_08_),
    .x(const_sl_8_bin_op_sl_uint32_t_uint6_t_c_l29_c55_98a9_x)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_2a99 (
    .cond(mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_2a99_cond),
    .iffalse(mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_2a99_iffalse),
    .iftrue(mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_2a99_iftrue),
    .return_output(_03_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_ccae (
    .cond(mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_ccae_cond),
    .iffalse(mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_ccae_iffalse),
    .iftrue(mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_ccae_iftrue),
    .return_output(_05_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_ee49 (
    .cond(mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_ee49_cond),
    .iffalse(mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_ee49_iffalse),
    .iftrue(mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_ee49_iftrue),
    .return_output(_07_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_1952 (
    .cond(mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_1952_cond),
    .iffalse(mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_1952_iffalse),
    .iftrue(mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_1952_iftrue),
    .return_output(_09_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_0e19 (
    .cond(mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_0e19_cond),
    .iffalse(mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_0e19_iffalse),
    .iftrue(mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_0e19_iftrue),
    .return_output(_11_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_2502 (
    .cond(rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_2502_cond),
    .iffalse(rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_2502_iffalse),
    .iftrue(rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_2502_iftrue),
    .return_output(_01_)
  );
  assign bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900_left = right;
  assign bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900_right = 5'h1f;
  assign bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900_return_output = _00_;
  assign rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_2502_cond = bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900_return_output;
  assign rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_2502_iftrue = 32'd0;
  assign rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_2502_iffalse = mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_0e19_return_output;
  assign rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_2502_return_output = _01_;
  assign const_sl_1_bin_op_sl_uint32_t_uint6_t_c_l26_c55_85c5_x = left;
  assign const_sl_1_bin_op_sl_uint32_t_uint6_t_c_l26_c55_85c5_return_output = _02_;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_2a99_cond = right[0];
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_2a99_iftrue = const_sl_1_bin_op_sl_uint32_t_uint6_t_c_l26_c55_85c5_return_output;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_2a99_iffalse = left;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_2a99_return_output = _03_;
  assign const_sl_2_bin_op_sl_uint32_t_uint6_t_c_l27_c55_6e3b_x = mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_2a99_return_output;
  assign const_sl_2_bin_op_sl_uint32_t_uint6_t_c_l27_c55_6e3b_return_output = _04_;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_ccae_cond = right[1];
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_ccae_iftrue = const_sl_2_bin_op_sl_uint32_t_uint6_t_c_l27_c55_6e3b_return_output;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_ccae_iffalse = mux_bin_op_sl_uint32_t_uint6_t_c_l26_c19_2a99_return_output;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_ccae_return_output = _05_;
  assign const_sl_4_bin_op_sl_uint32_t_uint6_t_c_l28_c55_5136_x = mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_ccae_return_output;
  assign const_sl_4_bin_op_sl_uint32_t_uint6_t_c_l28_c55_5136_return_output = _06_;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_ee49_cond = right[2];
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_ee49_iftrue = const_sl_4_bin_op_sl_uint32_t_uint6_t_c_l28_c55_5136_return_output;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_ee49_iffalse = mux_bin_op_sl_uint32_t_uint6_t_c_l27_c19_ccae_return_output;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_ee49_return_output = _07_;
  assign const_sl_8_bin_op_sl_uint32_t_uint6_t_c_l29_c55_98a9_x = mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_ee49_return_output;
  assign const_sl_8_bin_op_sl_uint32_t_uint6_t_c_l29_c55_98a9_return_output = _08_;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_1952_cond = right[3];
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_1952_iftrue = const_sl_8_bin_op_sl_uint32_t_uint6_t_c_l29_c55_98a9_return_output;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_1952_iffalse = mux_bin_op_sl_uint32_t_uint6_t_c_l28_c19_ee49_return_output;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_1952_return_output = _09_;
  assign const_sl_16_bin_op_sl_uint32_t_uint6_t_c_l30_c55_cf78_x = mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_1952_return_output;
  assign const_sl_16_bin_op_sl_uint32_t_uint6_t_c_l30_c55_cf78_return_output = _10_;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_0e19_cond = right[4];
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_0e19_iftrue = const_sl_16_bin_op_sl_uint32_t_uint6_t_c_l30_c55_cf78_return_output;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_0e19_iffalse = mux_bin_op_sl_uint32_t_uint6_t_c_l29_c19_1952_return_output;
  assign mux_bin_op_sl_uint32_t_uint6_t_c_l30_c19_0e19_return_output = _11_;
  assign return_output = rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_2502_return_output;
endmodule

module bin_op_sr_uint32_t_uint5_t_0clk_295015b8(left, right, return_output);
  wire [31:0] _0_;
  wire [31:0] _1_;
  wire [31:0] _2_;
  wire [31:0] _3_;
  wire [31:0] _4_;
  wire [31:0] _5_;
  wire [31:0] _6_;
  wire [31:0] _7_;
  wire [31:0] _8_;
  wire [31:0] _9_;
  wire [31:0] const_sr_16_bin_op_sr_uint32_t_uint5_t_c_l22_c55_3d75_return_output;
  wire [31:0] const_sr_16_bin_op_sr_uint32_t_uint5_t_c_l22_c55_3d75_x;
  wire [31:0] const_sr_1_bin_op_sr_uint32_t_uint5_t_c_l18_c55_a389_return_output;
  wire [31:0] const_sr_1_bin_op_sr_uint32_t_uint5_t_c_l18_c55_a389_x;
  wire [31:0] const_sr_2_bin_op_sr_uint32_t_uint5_t_c_l19_c55_d69f_return_output;
  wire [31:0] const_sr_2_bin_op_sr_uint32_t_uint5_t_c_l19_c55_d69f_x;
  wire [31:0] const_sr_4_bin_op_sr_uint32_t_uint5_t_c_l20_c55_182c_return_output;
  wire [31:0] const_sr_4_bin_op_sr_uint32_t_uint5_t_c_l20_c55_182c_x;
  wire [31:0] const_sr_8_bin_op_sr_uint32_t_uint5_t_c_l21_c55_6043_return_output;
  wire [31:0] const_sr_8_bin_op_sr_uint32_t_uint5_t_c_l21_c55_6043_x;
  input [31:0] left;
  wire [31:0] left;
  wire mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_c70c_cond;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_c70c_iffalse;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_c70c_iftrue;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_c70c_return_output;
  wire mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_69ee_cond;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_69ee_iffalse;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_69ee_iftrue;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_69ee_return_output;
  wire mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_f0a5_cond;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_f0a5_iffalse;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_f0a5_iftrue;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_f0a5_return_output;
  wire mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_49a7_cond;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_49a7_iffalse;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_49a7_iftrue;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_49a7_return_output;
  wire mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_2b4f_cond;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_2b4f_iffalse;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_2b4f_iftrue;
  wire [31:0] mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_2b4f_return_output;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [4:0] right;
  wire [4:0] right;
  const_sr_16_uint32_t_0clk_de264c78 const_sr_16_bin_op_sr_uint32_t_uint5_t_c_l22_c55_3d75 (
    .return_output(_8_),
    .x(const_sr_16_bin_op_sr_uint32_t_uint5_t_c_l22_c55_3d75_x)
  );
  const_sr_1_uint32_t_0clk_de264c78 const_sr_1_bin_op_sr_uint32_t_uint5_t_c_l18_c55_a389 (
    .return_output(_0_),
    .x(const_sr_1_bin_op_sr_uint32_t_uint5_t_c_l18_c55_a389_x)
  );
  const_sr_2_uint32_t_0clk_de264c78 const_sr_2_bin_op_sr_uint32_t_uint5_t_c_l19_c55_d69f (
    .return_output(_2_),
    .x(const_sr_2_bin_op_sr_uint32_t_uint5_t_c_l19_c55_d69f_x)
  );
  const_sr_4_uint32_t_0clk_de264c78 const_sr_4_bin_op_sr_uint32_t_uint5_t_c_l20_c55_182c (
    .return_output(_4_),
    .x(const_sr_4_bin_op_sr_uint32_t_uint5_t_c_l20_c55_182c_x)
  );
  const_sr_8_uint32_t_0clk_de264c78 const_sr_8_bin_op_sr_uint32_t_uint5_t_c_l21_c55_6043 (
    .return_output(_6_),
    .x(const_sr_8_bin_op_sr_uint32_t_uint5_t_c_l21_c55_6043_x)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_c70c (
    .cond(mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_c70c_cond),
    .iffalse(mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_c70c_iffalse),
    .iftrue(mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_c70c_iftrue),
    .return_output(_1_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_69ee (
    .cond(mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_69ee_cond),
    .iffalse(mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_69ee_iffalse),
    .iftrue(mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_69ee_iftrue),
    .return_output(_3_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_f0a5 (
    .cond(mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_f0a5_cond),
    .iffalse(mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_f0a5_iffalse),
    .iftrue(mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_f0a5_iftrue),
    .return_output(_5_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_49a7 (
    .cond(mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_49a7_cond),
    .iffalse(mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_49a7_iffalse),
    .iftrue(mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_49a7_iftrue),
    .return_output(_7_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_2b4f (
    .cond(mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_2b4f_cond),
    .iffalse(mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_2b4f_iffalse),
    .iftrue(mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_2b4f_iftrue),
    .return_output(_9_)
  );
  assign const_sr_1_bin_op_sr_uint32_t_uint5_t_c_l18_c55_a389_x = left;
  assign const_sr_1_bin_op_sr_uint32_t_uint5_t_c_l18_c55_a389_return_output = _0_;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_c70c_cond = right[0];
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_c70c_iftrue = const_sr_1_bin_op_sr_uint32_t_uint5_t_c_l18_c55_a389_return_output;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_c70c_iffalse = left;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_c70c_return_output = _1_;
  assign const_sr_2_bin_op_sr_uint32_t_uint5_t_c_l19_c55_d69f_x = mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_c70c_return_output;
  assign const_sr_2_bin_op_sr_uint32_t_uint5_t_c_l19_c55_d69f_return_output = _2_;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_69ee_cond = right[1];
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_69ee_iftrue = const_sr_2_bin_op_sr_uint32_t_uint5_t_c_l19_c55_d69f_return_output;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_69ee_iffalse = mux_bin_op_sr_uint32_t_uint5_t_c_l18_c19_c70c_return_output;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_69ee_return_output = _3_;
  assign const_sr_4_bin_op_sr_uint32_t_uint5_t_c_l20_c55_182c_x = mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_69ee_return_output;
  assign const_sr_4_bin_op_sr_uint32_t_uint5_t_c_l20_c55_182c_return_output = _4_;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_f0a5_cond = right[2];
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_f0a5_iftrue = const_sr_4_bin_op_sr_uint32_t_uint5_t_c_l20_c55_182c_return_output;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_f0a5_iffalse = mux_bin_op_sr_uint32_t_uint5_t_c_l19_c19_69ee_return_output;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_f0a5_return_output = _5_;
  assign const_sr_8_bin_op_sr_uint32_t_uint5_t_c_l21_c55_6043_x = mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_f0a5_return_output;
  assign const_sr_8_bin_op_sr_uint32_t_uint5_t_c_l21_c55_6043_return_output = _6_;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_49a7_cond = right[3];
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_49a7_iftrue = const_sr_8_bin_op_sr_uint32_t_uint5_t_c_l21_c55_6043_return_output;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_49a7_iffalse = mux_bin_op_sr_uint32_t_uint5_t_c_l20_c19_f0a5_return_output;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_49a7_return_output = _7_;
  assign const_sr_16_bin_op_sr_uint32_t_uint5_t_c_l22_c55_3d75_x = mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_49a7_return_output;
  assign const_sr_16_bin_op_sr_uint32_t_uint5_t_c_l22_c55_3d75_return_output = _8_;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_2b4f_cond = right[4];
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_2b4f_iftrue = const_sr_16_bin_op_sr_uint32_t_uint5_t_c_l22_c55_3d75_return_output;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_2b4f_iffalse = mux_bin_op_sr_uint32_t_uint5_t_c_l21_c19_49a7_return_output;
  assign mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_2b4f_return_output = _9_;
  assign return_output = mux_bin_op_sr_uint32_t_uint5_t_c_l22_c19_2b4f_return_output;
endmodule

module bin_op_sr_uint32_t_uint6_t_0clk_9f6ea3e6(left, right, return_output);
  wire _00_;
  wire [31:0] _01_;
  wire [31:0] _02_;
  wire [31:0] _03_;
  wire [31:0] _04_;
  wire [31:0] _05_;
  wire [31:0] _06_;
  wire [31:0] _07_;
  wire [31:0] _08_;
  wire [31:0] _09_;
  wire [31:0] _10_;
  wire [31:0] _11_;
  wire [5:0] bin_op_gt_bin_op_sr_uint32_t_uint6_t_c_l17_c6_aafb_left;
  wire bin_op_gt_bin_op_sr_uint32_t_uint6_t_c_l17_c6_aafb_return_output;
  wire [4:0] bin_op_gt_bin_op_sr_uint32_t_uint6_t_c_l17_c6_aafb_right;
  wire [31:0] const_sr_16_bin_op_sr_uint32_t_uint6_t_c_l35_c55_7d1d_return_output;
  wire [31:0] const_sr_16_bin_op_sr_uint32_t_uint6_t_c_l35_c55_7d1d_x;
  wire [31:0] const_sr_1_bin_op_sr_uint32_t_uint6_t_c_l31_c55_fb3c_return_output;
  wire [31:0] const_sr_1_bin_op_sr_uint32_t_uint6_t_c_l31_c55_fb3c_x;
  wire [31:0] const_sr_2_bin_op_sr_uint32_t_uint6_t_c_l32_c55_285b_return_output;
  wire [31:0] const_sr_2_bin_op_sr_uint32_t_uint6_t_c_l32_c55_285b_x;
  wire [31:0] const_sr_4_bin_op_sr_uint32_t_uint6_t_c_l33_c55_cfa4_return_output;
  wire [31:0] const_sr_4_bin_op_sr_uint32_t_uint6_t_c_l33_c55_cfa4_x;
  wire [31:0] const_sr_8_bin_op_sr_uint32_t_uint6_t_c_l34_c55_17f7_return_output;
  wire [31:0] const_sr_8_bin_op_sr_uint32_t_uint6_t_c_l34_c55_17f7_x;
  input [31:0] left;
  wire [31:0] left;
  wire mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_aeb3_cond;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_aeb3_iffalse;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_aeb3_iftrue;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_aeb3_return_output;
  wire mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_1cc9_cond;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_1cc9_iffalse;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_1cc9_iftrue;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_1cc9_return_output;
  wire mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_25db_cond;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_25db_iffalse;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_25db_iftrue;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_25db_return_output;
  wire mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_4e1f_cond;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_4e1f_iffalse;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_4e1f_iftrue;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_4e1f_return_output;
  wire mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_2294_cond;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_2294_iffalse;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_2294_iftrue;
  wire [31:0] mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_2294_return_output;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [5:0] right;
  wire [5:0] right;
  wire rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_d345_cond;
  wire [31:0] rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_d345_iffalse;
  wire [31:0] rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_d345_iftrue;
  wire [31:0] rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_d345_return_output;
  bin_op_gt_uint6_t_uint5_t_0clk_5af1a430 bin_op_gt_bin_op_sr_uint32_t_uint6_t_c_l17_c6_aafb (
    .left(bin_op_gt_bin_op_sr_uint32_t_uint6_t_c_l17_c6_aafb_left),
    .return_output(_00_),
    .right(bin_op_gt_bin_op_sr_uint32_t_uint6_t_c_l17_c6_aafb_right)
  );
  const_sr_16_uint32_t_0clk_de264c78 const_sr_16_bin_op_sr_uint32_t_uint6_t_c_l35_c55_7d1d (
    .return_output(_10_),
    .x(const_sr_16_bin_op_sr_uint32_t_uint6_t_c_l35_c55_7d1d_x)
  );
  const_sr_1_uint32_t_0clk_de264c78 const_sr_1_bin_op_sr_uint32_t_uint6_t_c_l31_c55_fb3c (
    .return_output(_02_),
    .x(const_sr_1_bin_op_sr_uint32_t_uint6_t_c_l31_c55_fb3c_x)
  );
  const_sr_2_uint32_t_0clk_de264c78 const_sr_2_bin_op_sr_uint32_t_uint6_t_c_l32_c55_285b (
    .return_output(_04_),
    .x(const_sr_2_bin_op_sr_uint32_t_uint6_t_c_l32_c55_285b_x)
  );
  const_sr_4_uint32_t_0clk_de264c78 const_sr_4_bin_op_sr_uint32_t_uint6_t_c_l33_c55_cfa4 (
    .return_output(_06_),
    .x(const_sr_4_bin_op_sr_uint32_t_uint6_t_c_l33_c55_cfa4_x)
  );
  const_sr_8_uint32_t_0clk_de264c78 const_sr_8_bin_op_sr_uint32_t_uint6_t_c_l34_c55_17f7 (
    .return_output(_08_),
    .x(const_sr_8_bin_op_sr_uint32_t_uint6_t_c_l34_c55_17f7_x)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_aeb3 (
    .cond(mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_aeb3_cond),
    .iffalse(mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_aeb3_iffalse),
    .iftrue(mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_aeb3_iftrue),
    .return_output(_03_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_1cc9 (
    .cond(mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_1cc9_cond),
    .iffalse(mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_1cc9_iffalse),
    .iftrue(mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_1cc9_iftrue),
    .return_output(_05_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_25db (
    .cond(mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_25db_cond),
    .iffalse(mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_25db_iffalse),
    .iftrue(mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_25db_iftrue),
    .return_output(_07_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_4e1f (
    .cond(mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_4e1f_cond),
    .iffalse(mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_4e1f_iffalse),
    .iftrue(mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_4e1f_iftrue),
    .return_output(_09_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_2294 (
    .cond(mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_2294_cond),
    .iffalse(mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_2294_iffalse),
    .iftrue(mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_2294_iftrue),
    .return_output(_11_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_d345 (
    .cond(rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_d345_cond),
    .iffalse(rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_d345_iffalse),
    .iftrue(rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_d345_iftrue),
    .return_output(_01_)
  );
  assign bin_op_gt_bin_op_sr_uint32_t_uint6_t_c_l17_c6_aafb_left = right;
  assign bin_op_gt_bin_op_sr_uint32_t_uint6_t_c_l17_c6_aafb_right = 5'h1f;
  assign bin_op_gt_bin_op_sr_uint32_t_uint6_t_c_l17_c6_aafb_return_output = _00_;
  assign rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_d345_cond = bin_op_gt_bin_op_sr_uint32_t_uint6_t_c_l17_c6_aafb_return_output;
  assign rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_d345_iftrue = 32'd0;
  assign rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_d345_iffalse = mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_2294_return_output;
  assign rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_d345_return_output = _01_;
  assign const_sr_1_bin_op_sr_uint32_t_uint6_t_c_l31_c55_fb3c_x = left;
  assign const_sr_1_bin_op_sr_uint32_t_uint6_t_c_l31_c55_fb3c_return_output = _02_;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_aeb3_cond = right[0];
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_aeb3_iftrue = const_sr_1_bin_op_sr_uint32_t_uint6_t_c_l31_c55_fb3c_return_output;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_aeb3_iffalse = left;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_aeb3_return_output = _03_;
  assign const_sr_2_bin_op_sr_uint32_t_uint6_t_c_l32_c55_285b_x = mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_aeb3_return_output;
  assign const_sr_2_bin_op_sr_uint32_t_uint6_t_c_l32_c55_285b_return_output = _04_;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_1cc9_cond = right[1];
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_1cc9_iftrue = const_sr_2_bin_op_sr_uint32_t_uint6_t_c_l32_c55_285b_return_output;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_1cc9_iffalse = mux_bin_op_sr_uint32_t_uint6_t_c_l31_c19_aeb3_return_output;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_1cc9_return_output = _05_;
  assign const_sr_4_bin_op_sr_uint32_t_uint6_t_c_l33_c55_cfa4_x = mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_1cc9_return_output;
  assign const_sr_4_bin_op_sr_uint32_t_uint6_t_c_l33_c55_cfa4_return_output = _06_;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_25db_cond = right[2];
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_25db_iftrue = const_sr_4_bin_op_sr_uint32_t_uint6_t_c_l33_c55_cfa4_return_output;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_25db_iffalse = mux_bin_op_sr_uint32_t_uint6_t_c_l32_c19_1cc9_return_output;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_25db_return_output = _07_;
  assign const_sr_8_bin_op_sr_uint32_t_uint6_t_c_l34_c55_17f7_x = mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_25db_return_output;
  assign const_sr_8_bin_op_sr_uint32_t_uint6_t_c_l34_c55_17f7_return_output = _08_;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_4e1f_cond = right[3];
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_4e1f_iftrue = const_sr_8_bin_op_sr_uint32_t_uint6_t_c_l34_c55_17f7_return_output;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_4e1f_iffalse = mux_bin_op_sr_uint32_t_uint6_t_c_l33_c19_25db_return_output;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_4e1f_return_output = _09_;
  assign const_sr_16_bin_op_sr_uint32_t_uint6_t_c_l35_c55_7d1d_x = mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_4e1f_return_output;
  assign const_sr_16_bin_op_sr_uint32_t_uint6_t_c_l35_c55_7d1d_return_output = _10_;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_2294_cond = right[4];
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_2294_iftrue = const_sr_16_bin_op_sr_uint32_t_uint6_t_c_l35_c55_7d1d_return_output;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_2294_iffalse = mux_bin_op_sr_uint32_t_uint6_t_c_l34_c19_4e1f_return_output;
  assign mux_bin_op_sr_uint32_t_uint6_t_c_l35_c19_2294_return_output = _11_;
  assign return_output = rv_mux_bin_op_sr_uint32_t_uint6_t_c_l17_c3_d345_return_output;
endmodule

module const_sl_16_uint32_t_0clk_de264c78(x, return_output);
  wire [31:0] _0_;
  wire [63:0] \:790.read_pipe ;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [31:0] x;
  wire [31:0] x;
  assign _0_ = x << 31'h00000010;
  assign \:790.read_pipe  = { 32'hxxxxxxxx, x };
  assign return_output = _0_;
endmodule

module const_sl_1_uint32_t_0clk_de264c78(x, return_output);
  wire [31:0] _0_;
  wire [63:0] \:714.read_pipe ;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [31:0] x;
  wire [31:0] x;
  assign _0_ = x << 31'h00000001;
  assign \:714.read_pipe  = { 32'hxxxxxxxx, x };
  assign return_output = _0_;
endmodule

module const_sl_2_uint32_t_0clk_de264c78(x, return_output);
  wire [31:0] _0_;
  wire [63:0] \:733.read_pipe ;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [31:0] x;
  wire [31:0] x;
  assign _0_ = x << 31'h00000002;
  assign \:733.read_pipe  = { 32'hxxxxxxxx, x };
  assign return_output = _0_;
endmodule

module const_sl_4_uint32_t_0clk_de264c78(x, return_output);
  wire [31:0] _0_;
  wire [63:0] \:752.read_pipe ;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [31:0] x;
  wire [31:0] x;
  assign _0_ = x << 31'h00000004;
  assign \:752.read_pipe  = { 32'hxxxxxxxx, x };
  assign return_output = _0_;
endmodule

module const_sl_8_uint32_t_0clk_de264c78(x, return_output);
  wire [31:0] _0_;
  wire [63:0] \:771.read_pipe ;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [31:0] x;
  wire [31:0] x;
  assign _0_ = x << 31'h00000008;
  assign \:771.read_pipe  = { 32'hxxxxxxxx, x };
  assign return_output = _0_;
endmodule

module const_sr_16_uint32_t_0clk_de264c78(x, return_output);
  wire [31:0] _0_;
  wire [63:0] \:885.read_pipe ;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [31:0] x;
  wire [31:0] x;
  assign _0_ = x >> 31'h00000010;
  assign \:885.read_pipe  = { 32'hxxxxxxxx, x };
  assign return_output = _0_;
endmodule

module const_sr_1_uint32_t_0clk_de264c78(x, return_output);
  wire [31:0] _0_;
  wire [63:0] \:809.read_pipe ;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [31:0] x;
  wire [31:0] x;
  assign _0_ = x >> 31'h00000001;
  assign \:809.read_pipe  = { 32'hxxxxxxxx, x };
  assign return_output = _0_;
endmodule

module const_sr_2_uint32_t_0clk_de264c78(x, return_output);
  wire [31:0] _0_;
  wire [63:0] \:828.read_pipe ;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [31:0] x;
  wire [31:0] x;
  assign _0_ = x >> 31'h00000002;
  assign \:828.read_pipe  = { 32'hxxxxxxxx, x };
  assign return_output = _0_;
endmodule

module const_sr_4_uint32_t_0clk_de264c78(x, return_output);
  wire [31:0] _0_;
  wire [63:0] \:847.read_pipe ;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [31:0] x;
  wire [31:0] x;
  assign _0_ = x >> 31'h00000004;
  assign \:847.read_pipe  = { 32'hxxxxxxxx, x };
  assign return_output = _0_;
endmodule

module const_sr_5_uint6_t_0clk_de264c78(x, return_output);
  wire [5:0] _0_;
  wire [11:0] \:963.read_pipe ;
  output [5:0] return_output;
  wire [5:0] return_output;
  input [5:0] x;
  wire [5:0] x;
  assign _0_ = x >> 31'h00000005;
  assign \:963.read_pipe  = { 6'hxx, x };
  assign return_output = _0_;
endmodule

module const_sr_8_uint32_t_0clk_de264c78(x, return_output);
  wire [31:0] _0_;
  wire [63:0] \:866.read_pipe ;
  output [31:0] return_output;
  wire [31:0] return_output;
  input [31:0] x;
  wire [31:0] x;
  assign _0_ = x >> 31'h00000008;
  assign \:866.read_pipe  = { 32'hxxxxxxxx, x };
  assign return_output = _0_;
endmodule

module latchup_rotate_0clk_1bbb502d(\i[data] , \i[shift_amount] , \i[direction] , \i[rotate] , return_output);
  wire [31:0] _0_;
  wire [31:0] _1_;
  wire [31:0] _2_;
  wire [31:0] _3_;
  wire [31:0] _4_;
  wire [31:0] _5_;
  wire [31:0] _6_;
  wire [31:0] bin_op_sl_solution_c_l59_c12_740d_left;
  wire [31:0] bin_op_sl_solution_c_l59_c12_740d_return_output;
  wire [4:0] bin_op_sl_solution_c_l59_c12_740d_right;
  wire [31:0] bin_op_sr_solution_c_l61_c12_5679_left;
  wire [31:0] bin_op_sr_solution_c_l61_c12_5679_return_output;
  wire [4:0] bin_op_sr_solution_c_l61_c12_5679_right;
  input [31:0] \i[data] ;
  wire [31:0] \i[data] ;
  input \i[direction] ;
  wire \i[direction] ;
  input \i[rotate] ;
  wire \i[rotate] ;
  input [4:0] \i[shift_amount] ;
  wire [4:0] \i[shift_amount] ;
  wire [4:0] leftrotate_solution_c_l53_c12_8b88_d;
  wire [31:0] leftrotate_solution_c_l53_c12_8b88_n;
  wire [31:0] leftrotate_solution_c_l53_c12_8b88_return_output;
  output [31:0] return_output;
  wire [31:0] return_output;
  wire [4:0] rightrotate_solution_c_l55_c12_0b58_d;
  wire [31:0] rightrotate_solution_c_l55_c12_0b58_n;
  wire [31:0] rightrotate_solution_c_l55_c12_0b58_return_output;
  wire rv_mux_solution_c_l51_c3_9bb8_cond;
  wire [31:0] rv_mux_solution_c_l51_c3_9bb8_iffalse;
  wire [31:0] rv_mux_solution_c_l51_c3_9bb8_iftrue;
  wire [31:0] rv_mux_solution_c_l51_c3_9bb8_return_output;
  wire rv_mux_solution_c_l52_c5_92c9_cond;
  wire [31:0] rv_mux_solution_c_l52_c5_92c9_iffalse;
  wire [31:0] rv_mux_solution_c_l52_c5_92c9_iftrue;
  wire [31:0] rv_mux_solution_c_l52_c5_92c9_return_output;
  wire rv_mux_solution_c_l58_c5_115e_cond;
  wire [31:0] rv_mux_solution_c_l58_c5_115e_iffalse;
  wire [31:0] rv_mux_solution_c_l58_c5_115e_iftrue;
  wire [31:0] rv_mux_solution_c_l58_c5_115e_return_output;
  bin_op_sl_uint32_t_uint5_t_0clk_295015b8 bin_op_sl_solution_c_l59_c12_740d (
    .left(bin_op_sl_solution_c_l59_c12_740d_left),
    .return_output(_6_),
    .right(bin_op_sl_solution_c_l59_c12_740d_right)
  );
  bin_op_sr_uint32_t_uint5_t_0clk_295015b8 bin_op_sr_solution_c_l61_c12_5679 (
    .left(bin_op_sr_solution_c_l61_c12_5679_left),
    .return_output(_0_),
    .right(bin_op_sr_solution_c_l61_c12_5679_right)
  );
  leftrotate_0clk_5bc0299e leftrotate_solution_c_l53_c12_8b88 (
    .d(leftrotate_solution_c_l53_c12_8b88_d),
    .n(leftrotate_solution_c_l53_c12_8b88_n),
    .return_output(_3_)
  );
  rightrotate_0clk_cbe809a7 rightrotate_solution_c_l55_c12_0b58 (
    .d(rightrotate_solution_c_l55_c12_0b58_d),
    .n(rightrotate_solution_c_l55_c12_0b58_n),
    .return_output(_4_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 rv_mux_solution_c_l51_c3_9bb8 (
    .cond(rv_mux_solution_c_l51_c3_9bb8_cond),
    .iffalse(rv_mux_solution_c_l51_c3_9bb8_iffalse),
    .iftrue(rv_mux_solution_c_l51_c3_9bb8_iftrue),
    .return_output(_1_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 rv_mux_solution_c_l52_c5_92c9 (
    .cond(rv_mux_solution_c_l52_c5_92c9_cond),
    .iffalse(rv_mux_solution_c_l52_c5_92c9_iffalse),
    .iftrue(rv_mux_solution_c_l52_c5_92c9_iftrue),
    .return_output(_2_)
  );
  mux_uint1_t_uint32_t_uint32_t_0clk_de264c78 rv_mux_solution_c_l58_c5_115e (
    .cond(rv_mux_solution_c_l58_c5_115e_cond),
    .iffalse(rv_mux_solution_c_l58_c5_115e_iffalse),
    .iftrue(rv_mux_solution_c_l58_c5_115e_iftrue),
    .return_output(_5_)
  );
  assign rv_mux_solution_c_l51_c3_9bb8_cond = \i[rotate] ;
  assign rv_mux_solution_c_l51_c3_9bb8_iftrue = rv_mux_solution_c_l52_c5_92c9_return_output;
  assign rv_mux_solution_c_l51_c3_9bb8_iffalse = rv_mux_solution_c_l58_c5_115e_return_output;
  assign rv_mux_solution_c_l51_c3_9bb8_return_output = _1_;
  assign rv_mux_solution_c_l52_c5_92c9_cond = \i[direction] ;
  assign rv_mux_solution_c_l52_c5_92c9_iftrue = leftrotate_solution_c_l53_c12_8b88_return_output;
  assign rv_mux_solution_c_l52_c5_92c9_iffalse = rightrotate_solution_c_l55_c12_0b58_return_output;
  assign rv_mux_solution_c_l52_c5_92c9_return_output = _2_;
  assign leftrotate_solution_c_l53_c12_8b88_n = \i[data] ;
  assign leftrotate_solution_c_l53_c12_8b88_d = \i[shift_amount] ;
  assign leftrotate_solution_c_l53_c12_8b88_return_output = _3_;
  assign rightrotate_solution_c_l55_c12_0b58_n = \i[data] ;
  assign rightrotate_solution_c_l55_c12_0b58_d = \i[shift_amount] ;
  assign rightrotate_solution_c_l55_c12_0b58_return_output = _4_;
  assign rv_mux_solution_c_l58_c5_115e_cond = \i[direction] ;
  assign rv_mux_solution_c_l58_c5_115e_iftrue = bin_op_sl_solution_c_l59_c12_740d_return_output;
  assign rv_mux_solution_c_l58_c5_115e_iffalse = bin_op_sr_solution_c_l61_c12_5679_return_output;
  assign rv_mux_solution_c_l58_c5_115e_return_output = _5_;
  assign bin_op_sl_solution_c_l59_c12_740d_left = \i[data] ;
  assign bin_op_sl_solution_c_l59_c12_740d_right = \i[shift_amount] ;
  assign bin_op_sl_solution_c_l59_c12_740d_return_output = _6_;
  assign bin_op_sr_solution_c_l61_c12_5679_left = \i[data] ;
  assign bin_op_sr_solution_c_l61_c12_5679_right = \i[shift_amount] ;
  assign bin_op_sr_solution_c_l61_c12_5679_return_output = _0_;
  assign return_output = rv_mux_solution_c_l51_c3_9bb8_return_output;
endmodule

module leftrotate_0clk_5bc0299e(n, d, return_output);
  wire [31:0] _0_;
  wire [5:0] _1_;
  wire [31:0] _2_;
  wire [31:0] _3_;
  wire [5:0] bin_op_minus_solution_c_l43_c30_270e_left;
  wire [5:0] bin_op_minus_solution_c_l43_c30_270e_return_output;
  wire [4:0] bin_op_minus_solution_c_l43_c30_270e_right;
  wire [31:0] bin_op_or_solution_c_l43_c13_555a_left;
  wire [31:0] bin_op_or_solution_c_l43_c13_555a_return_output;
  wire [31:0] bin_op_or_solution_c_l43_c13_555a_right;
  wire [31:0] bin_op_sl_solution_c_l43_c13_93d9_left;
  wire [31:0] bin_op_sl_solution_c_l43_c13_93d9_return_output;
  wire [4:0] bin_op_sl_solution_c_l43_c13_93d9_right;
  wire [31:0] bin_op_sr_solution_c_l43_c24_dcee_left;
  wire [31:0] bin_op_sr_solution_c_l43_c24_dcee_return_output;
  wire [5:0] bin_op_sr_solution_c_l43_c24_dcee_right;
  input [4:0] d;
  wire [4:0] d;
  input [31:0] n;
  wire [31:0] n;
  output [31:0] return_output;
  wire [31:0] return_output;
  bin_op_minus_uint6_t_uint5_t_0clk_de264c78 bin_op_minus_solution_c_l43_c30_270e (
    .left(bin_op_minus_solution_c_l43_c30_270e_left),
    .return_output(_1_),
    .right(bin_op_minus_solution_c_l43_c30_270e_right)
  );
  bin_op_or_uint32_t_uint32_t_0clk_de264c78 bin_op_or_solution_c_l43_c13_555a (
    .left(bin_op_or_solution_c_l43_c13_555a_left),
    .return_output(_3_),
    .right(bin_op_or_solution_c_l43_c13_555a_right)
  );
  bin_op_sl_uint32_t_uint5_t_0clk_295015b8 bin_op_sl_solution_c_l43_c13_93d9 (
    .left(bin_op_sl_solution_c_l43_c13_93d9_left),
    .return_output(_0_),
    .right(bin_op_sl_solution_c_l43_c13_93d9_right)
  );
  bin_op_sr_uint32_t_uint6_t_0clk_9f6ea3e6 bin_op_sr_solution_c_l43_c24_dcee (
    .left(bin_op_sr_solution_c_l43_c24_dcee_left),
    .return_output(_2_),
    .right(bin_op_sr_solution_c_l43_c24_dcee_right)
  );
  assign bin_op_sl_solution_c_l43_c13_93d9_left = n;
  assign bin_op_sl_solution_c_l43_c13_93d9_right = d;
  assign bin_op_sl_solution_c_l43_c13_93d9_return_output = _0_;
  assign bin_op_minus_solution_c_l43_c30_270e_left = 6'h20;
  assign bin_op_minus_solution_c_l43_c30_270e_right = d;
  assign bin_op_minus_solution_c_l43_c30_270e_return_output = _1_;
  assign bin_op_sr_solution_c_l43_c24_dcee_left = n;
  assign bin_op_sr_solution_c_l43_c24_dcee_right = bin_op_minus_solution_c_l43_c30_270e_return_output;
  assign bin_op_sr_solution_c_l43_c24_dcee_return_output = _2_;
  assign bin_op_or_solution_c_l43_c13_555a_left = bin_op_sl_solution_c_l43_c13_93d9_return_output;
  assign bin_op_or_solution_c_l43_c13_555a_right = bin_op_sr_solution_c_l43_c24_dcee_return_output;
  assign bin_op_or_solution_c_l43_c13_555a_return_output = _3_;
  assign return_output = bin_op_or_solution_c_l43_c13_555a_return_output;
endmodule

module mux_uint1_t_uint1_t_uint1_t_0clk_de264c78(cond, iftrue, iffalse, return_output);
  wire _0_;
  wire _1_;
  wire [3:0] \:1019.read_pipe ;
  input cond;
  wire cond;
  input iffalse;
  wire iffalse;
  input iftrue;
  wire iftrue;
  output return_output;
  wire return_output;
  assign _0_ = cond == 1'h1;
  assign _1_ = _0_ ? iftrue : iffalse;
  assign \:1019.read_pipe  = { iffalse, iftrue, cond, 1'hx };
  assign return_output = _1_;
endmodule

module mux_uint1_t_uint32_t_uint32_t_0clk_de264c78(cond, iftrue, iffalse, return_output);
  wire _0_;
  wire [31:0] _1_;
  wire [96:0] \:95.read_pipe ;
  input cond;
  wire cond;
  input [31:0] iffalse;
  wire [31:0] iffalse;
  input [31:0] iftrue;
  wire [31:0] iftrue;
  output [31:0] return_output;
  wire [31:0] return_output;
  assign _0_ = cond == 1'h1;
  assign _1_ = _0_ ? iftrue : iffalse;
  assign \:95.read_pipe  = { iffalse, iftrue, cond, 32'hxxxxxxxx };
  assign return_output = _1_;
endmodule

module rightrotate_0clk_cbe809a7(n, d, return_output);
  wire [31:0] _0_;
  wire [5:0] _1_;
  wire [31:0] _2_;
  wire [31:0] _3_;
  wire [5:0] bin_op_minus_solution_c_l46_c30_44d5_left;
  wire [5:0] bin_op_minus_solution_c_l46_c30_44d5_return_output;
  wire [4:0] bin_op_minus_solution_c_l46_c30_44d5_right;
  wire [31:0] bin_op_or_solution_c_l46_c13_3c51_left;
  wire [31:0] bin_op_or_solution_c_l46_c13_3c51_return_output;
  wire [31:0] bin_op_or_solution_c_l46_c13_3c51_right;
  wire [31:0] bin_op_sl_solution_c_l46_c24_0a9f_left;
  wire [31:0] bin_op_sl_solution_c_l46_c24_0a9f_return_output;
  wire [5:0] bin_op_sl_solution_c_l46_c24_0a9f_right;
  wire [31:0] bin_op_sr_solution_c_l46_c13_8357_left;
  wire [31:0] bin_op_sr_solution_c_l46_c13_8357_return_output;
  wire [4:0] bin_op_sr_solution_c_l46_c13_8357_right;
  input [4:0] d;
  wire [4:0] d;
  input [31:0] n;
  wire [31:0] n;
  output [31:0] return_output;
  wire [31:0] return_output;
  bin_op_minus_uint6_t_uint5_t_0clk_de264c78 bin_op_minus_solution_c_l46_c30_44d5 (
    .left(bin_op_minus_solution_c_l46_c30_44d5_left),
    .return_output(_1_),
    .right(bin_op_minus_solution_c_l46_c30_44d5_right)
  );
  bin_op_or_uint32_t_uint32_t_0clk_de264c78 bin_op_or_solution_c_l46_c13_3c51 (
    .left(bin_op_or_solution_c_l46_c13_3c51_left),
    .return_output(_3_),
    .right(bin_op_or_solution_c_l46_c13_3c51_right)
  );
  bin_op_sl_uint32_t_uint6_t_0clk_91f7f59e bin_op_sl_solution_c_l46_c24_0a9f (
    .left(bin_op_sl_solution_c_l46_c24_0a9f_left),
    .return_output(_2_),
    .right(bin_op_sl_solution_c_l46_c24_0a9f_right)
  );
  bin_op_sr_uint32_t_uint5_t_0clk_295015b8 bin_op_sr_solution_c_l46_c13_8357 (
    .left(bin_op_sr_solution_c_l46_c13_8357_left),
    .return_output(_0_),
    .right(bin_op_sr_solution_c_l46_c13_8357_right)
  );
  assign bin_op_sr_solution_c_l46_c13_8357_left = n;
  assign bin_op_sr_solution_c_l46_c13_8357_right = d;
  assign bin_op_sr_solution_c_l46_c13_8357_return_output = _0_;
  assign bin_op_minus_solution_c_l46_c30_44d5_left = 6'h20;
  assign bin_op_minus_solution_c_l46_c30_44d5_right = d;
  assign bin_op_minus_solution_c_l46_c30_44d5_return_output = _1_;
  assign bin_op_sl_solution_c_l46_c24_0a9f_left = n;
  assign bin_op_sl_solution_c_l46_c24_0a9f_right = bin_op_minus_solution_c_l46_c30_44d5_return_output;
  assign bin_op_sl_solution_c_l46_c24_0a9f_return_output = _2_;
  assign bin_op_or_solution_c_l46_c13_3c51_left = bin_op_sr_solution_c_l46_c13_8357_return_output;
  assign bin_op_or_solution_c_l46_c13_3c51_right = bin_op_sl_solution_c_l46_c24_0a9f_return_output;
  assign bin_op_or_solution_c_l46_c13_3c51_return_output = _3_;
  assign return_output = bin_op_or_solution_c_l46_c13_3c51_return_output;
endmodule

module solution(\input[data] , \input[valid] , clk, input_ready, \output[data] , \output[valid] );
  wire [32:0] _0_;
  wire _1_;
  input clk;
  wire clk;
  (* dont_touch = "true" *)
  (* keep = "true" *)
  (* syn_keep = 1'h1 *)
  wire clk_175p0;
  wire [39:0] global_to_module;
  input [38:0] \input[data] ;
  wire [38:0] \input[data] ;
  input \input[valid] ;
  wire \input[valid] ;
  output input_ready;
  wire input_ready;
  wire [33:0] module_to_global;
  output [31:0] \output[data] ;
  wire [31:0] \output[data] ;
  output \output[valid] ;
  wire \output[valid] ;
  solution_0clk_83914a8b solution_0clk_83914a8b (
    .\global_to_module[input] (global_to_module),
    .\module_to_global[input_ready] (_1_),
    .\module_to_global[output] (_0_)
  );
  assign clk_175p0 = clk;
  assign module_to_global = { _1_, _0_ };
  assign global_to_module = { \input[valid] , \input[data]  };
  assign input_ready = module_to_global[33];
  assign \output[data]  = module_to_global[31:0];
  assign \output[valid]  = module_to_global[32];
endmodule

module solution_0clk_83914a8b(\global_to_module[input] , \module_to_global[output] , \module_to_global[input_ready] );
  wire [31:0] _0_;
  input [39:0] \global_to_module[input] ;
  wire [39:0] \global_to_module[input] ;
  wire [38:0] latchup_rotate_solution_c_l70_c24_d51e_i;
  wire [31:0] latchup_rotate_solution_c_l70_c24_d51e_return_output;
  output \module_to_global[input_ready] ;
  wire \module_to_global[input_ready] ;
  output [32:0] \module_to_global[output] ;
  wire [32:0] \module_to_global[output] ;
  latchup_rotate_0clk_1bbb502d latchup_rotate_solution_c_l70_c24_d51e (
    .\i[data] (latchup_rotate_solution_c_l70_c24_d51e_i[31:0]),
    .\i[direction] (latchup_rotate_solution_c_l70_c24_d51e_i[37]),
    .\i[rotate] (latchup_rotate_solution_c_l70_c24_d51e_i[38]),
    .\i[shift_amount] (latchup_rotate_solution_c_l70_c24_d51e_i[36:32]),
    .return_output(_0_)
  );
  assign latchup_rotate_solution_c_l70_c24_d51e_i = \global_to_module[input] [38:0];
  assign latchup_rotate_solution_c_l70_c24_d51e_return_output = _0_;
  assign \module_to_global[output]  = { \global_to_module[input] [39], latchup_rotate_solution_c_l70_c24_d51e_return_output };
  assign \module_to_global[input_ready]  = 1'h1;
endmodule

Timing Analysis

Path 1-8.284 ns

From: i_payload_shift_amount[1]

To: o_payload[0]

Data Arrival: 8.285 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`i_payload_shift_amount[1]`
0.000	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$550/B`
0.249	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$550/Y`
0.249	sky130_fd_sc_hvl__o21a_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$551/B1`
0.561	sky130_fd_sc_hvl__o21a_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$551/X`
0.561	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$555/A2`
0.732	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$555/Y`
0.732	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$558/B1`
0.913	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$558/Y`
0.913	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$566/A1`
1.179	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$566/Y`
1.179	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$567/B`
4.001	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$567/Y`
4.001	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$515/A`
4.358	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$515/Y`
4.358	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$533/B`
4.559	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$533/Y`
4.559	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$537/B1`
4.789	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$537/Y`
4.789	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$540/A`
5.004	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$540/Y`
5.004	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_8843/$abc$620$auto$blifparse.cc:396:parse_blif$621/A1`
6.369	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_8843/$abc$620$auto$blifparse.cc:396:parse_blif$621/X`
6.369	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_2502/$abc$622$auto$blifparse.cc:396:parse_blif$623/S`
6.883	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_2502/$abc$622$auto$blifparse.cc:396:parse_blif$623/X`
6.883	sky130_fd_sc_hvl__or2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_or_solution_c_l46_c13_3c51/$abc$570$auto$blifparse.cc:396:parse_blif$571/A`
7.307	sky130_fd_sc_hvl__or2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_or_solution_c_l46_c13_3c51/$abc$570$auto$blifparse.cc:396:parse_blif$571/X`
7.307	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rv_mux_solution_c_l52_c5_92c9/$abc$622$auto$blifparse.cc:396:parse_blif$623/A0`
7.813	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rv_mux_solution_c_l52_c5_92c9/$abc$622$auto$blifparse.cc:396:parse_blif$623/X`
7.813	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rv_mux_solution_c_l51_c3_9bb8/$abc$622$auto$blifparse.cc:396:parse_blif$623/A1`
8.285	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rv_mux_solution_c_l51_c3_9bb8/$abc$622$auto$blifparse.cc:396:parse_blif$623/X`
8.285	Solution	`o_payload[0]`

Path 2-8.284 ns

From: i_payload_shift_amount[1]

To: o_payload[10]

Data Arrival: 8.285 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`i_payload_shift_amount[1]`
0.000	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$550/B`
0.249	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$550/Y`
0.249	sky130_fd_sc_hvl__o21a_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$551/B1`
0.561	sky130_fd_sc_hvl__o21a_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$551/X`
0.561	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$555/A2`
0.732	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$555/Y`
0.732	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$558/B1`
0.913	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$558/Y`
0.913	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$566/A1`
1.179	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$566/Y`
1.179	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$567/B`
4.001	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$567/Y`
4.001	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$515/A`
4.358	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$515/Y`
4.358	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$533/B`
4.559	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$533/Y`
4.559	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$537/B1`
4.789	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$537/Y`
4.789	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$540/A`
5.004	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$540/Y`
5.004	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_8843/$abc$620$auto$blifparse.cc:396:parse_blif$621/A1`
6.369	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_8843/$abc$620$auto$blifparse.cc:396:parse_blif$621/X`
6.369	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_2502/$abc$622$auto$blifparse.cc:396:parse_blif$633/S`
6.883	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_2502/$abc$622$auto$blifparse.cc:396:parse_blif$633/X`
6.883	sky130_fd_sc_hvl__or2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_or_solution_c_l46_c13_3c51/$abc$570$auto$blifparse.cc:396:parse_blif$581/A`
7.307	sky130_fd_sc_hvl__or2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_or_solution_c_l46_c13_3c51/$abc$570$auto$blifparse.cc:396:parse_blif$581/X`
7.307	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rv_mux_solution_c_l52_c5_92c9/$abc$622$auto$blifparse.cc:396:parse_blif$633/A0`
7.813	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rv_mux_solution_c_l52_c5_92c9/$abc$622$auto$blifparse.cc:396:parse_blif$633/X`
7.813	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rv_mux_solution_c_l51_c3_9bb8/$abc$622$auto$blifparse.cc:396:parse_blif$633/A1`
8.285	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rv_mux_solution_c_l51_c3_9bb8/$abc$622$auto$blifparse.cc:396:parse_blif$633/X`
8.285	Solution	`o_payload[10]`

Path 3-8.284 ns

From: i_payload_shift_amount[1]

To: o_payload[11]

Data Arrival: 8.285 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`i_payload_shift_amount[1]`
0.000	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$550/B`
0.249	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$550/Y`
0.249	sky130_fd_sc_hvl__o21a_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$551/B1`
0.561	sky130_fd_sc_hvl__o21a_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$551/X`
0.561	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$555/A2`
0.732	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$555/Y`
0.732	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$558/B1`
0.913	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$558/Y`
0.913	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$566/A1`
1.179	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$566/Y`
1.179	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$567/B`
4.001	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_minus_solution_c_l46_c30_44d5/$abc$542$auto$blifparse.cc:396:parse_blif$567/Y`
4.001	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$515/A`
4.358	sky130_fd_sc_hvl__inv_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$515/Y`
4.358	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$533/B`
4.559	sky130_fd_sc_hvl__nand2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$533/Y`
4.559	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$537/B1`
4.789	sky130_fd_sc_hvl__o21ai_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$537/Y`
4.789	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$540/A`
5.004	sky130_fd_sc_hvl__xnor2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/bin_op_minus_bin_op_gt_uint6_t_uint5_t_c_l17_c18_2db2/$abc$510$auto$blifparse.cc:396:parse_blif$540/Y`
5.004	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_8843/$abc$620$auto$blifparse.cc:396:parse_blif$621/A1`
6.369	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/bin_op_gt_bin_op_sl_uint32_t_uint6_t_c_l17_c6_3900/rv_mux_bin_op_gt_uint6_t_uint5_t_c_l15_c3_8843/$abc$620$auto$blifparse.cc:396:parse_blif$621/X`
6.369	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_2502/$abc$622$auto$blifparse.cc:396:parse_blif$634/S`
6.883	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_sl_solution_c_l46_c24_0a9f/rv_mux_bin_op_sl_uint32_t_uint6_t_c_l17_c3_2502/$abc$622$auto$blifparse.cc:396:parse_blif$634/X`
6.883	sky130_fd_sc_hvl__or2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_or_solution_c_l46_c13_3c51/$abc$570$auto$blifparse.cc:396:parse_blif$582/A`
7.307	sky130_fd_sc_hvl__or2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rightrotate_solution_c_l55_c12_0b58/bin_op_or_solution_c_l46_c13_3c51/$abc$570$auto$blifparse.cc:396:parse_blif$582/X`
7.307	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rv_mux_solution_c_l52_c5_92c9/$abc$622$auto$blifparse.cc:396:parse_blif$634/A0`
7.813	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rv_mux_solution_c_l52_c5_92c9/$abc$622$auto$blifparse.cc:396:parse_blif$634/X`
7.813	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rv_mux_solution_c_l51_c3_9bb8/$abc$622$auto$blifparse.cc:396:parse_blif$634/A1`
8.285	sky130_fd_sc_hvl__mux2_1	`inner/solution_0clk_83914a8b/latchup_rotate_solution_c_l70_c24_d51e/rv_mux_solution_c_l51_c3_9bb8/$abc$622$auto$blifparse.cc:396:parse_blif$634/X`
8.285	Solution	`o_payload[11]`

Post-Synthesis Verilog

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