Number of Inversions in Sliding Window

1 / 1

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Submission #1

PASSED

RankingPercentile

Latency

43.83 (7 cycles)ns

1st

top 1%

Max Frequency

159.72MHz

1st

top 1%

Area

60200μm²

1st

top 1%

Submitted Solution

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready,
  input wire i_valid,
  input wire [4-1:0] i_payload_k,
  input wire [32-1:0] i_payload_nums_fragment,
  input wire i_payload_nums_last,
  output wire [8-1:0] o_payload_fragment,
  output wire o_payload_last,
  output wire o_valid
);

// Define your design here
  // just for fun.  try not to stare directly at the code.

reg [32*14-1:0] srl = 0;
wire [32*15-1:0] ext = {srl, i_payload_nums_fragment};

reg inv1 = 0;

reg [1:0] inv2 = 0;
reg [1:0] inv3 = 0;

reg [2:0] inv4 = 0;
reg [2:0] inv5 = 0;
reg [2:0] inv6 = 0;
reg [2:0] inv7 = 0;

reg [3:0] inv8 = 0;
reg [3:0] inv9 = 0;
reg [3:0] inv10 = 0;
reg [3:0] inv11 = 0;
reg [3:0] inv12 = 0;
reg [3:0] inv13 = 0;
reg [3:0] inv14 = 0;

reg valid_d = 0;
reg last_d = 0;
reg [4-1:0] k_d = 0;
reg valid_2d = 0;
reg last_2d = 0;


// masked compares
wire       mi1  = (k_d >= 2) ? inv1 : 0;
wire [1:0] mi2  = (k_d >= 3) ? inv2 : 0;
wire [1:0] mi3  = (k_d >= 4) ? inv3 : 0;
wire [2:0] mi4  = (k_d >= 5) ? inv4 : 0;
wire [2:0] mi5  = (k_d >= 6) ? inv5 : 0; // 15
wire [2:0] mi6  = (k_d >= 7) ? inv6 : 0; // 21

wire [2:0] mi7  = (k_d >= 8) ? inv7 : 0;
wire [3:0] mi8  = (k_d >= 9) ? inv8 : 0;
wire [3:0] mi9  = (k_d >= 10) ? inv9 : 0;
wire [3:0] mi10 = (k_d >= 11) ? inv10 : 0; // 34
                                            
wire [3:0] mi11 = (k_d >= 12) ? inv11 : 0;
wire [3:0] mi12 = (k_d >= 13) ? inv12 : 0;
wire [3:0] mi13 = (k_d >= 14) ? inv13 : 0;
wire [3:0] mi14 = (k_d >= 15) ? inv14 : 0; // 50


reg [4:0] sum16 = 0;
reg [5:0] sum710 = 0;
reg [5:0] sum1114 = 0;
  
reg [4:0] count = 1;
reg gate_d = 0;
reg gate_2d = 0;

  //input wire i_valid,
  //input wire [4-1:0] i_payload_k, // probably stable?
  //input wire [32-1:0] i_payload_nums_fragment,
  //input wire i_payload_nums_last,
assign i_ready = ~reset;
assign o_payload_fragment = sum16 + sum710 + sum1114;
assign o_payload_last = last_2d && gate_2d;
assign o_valid = valid_2d && gate_2d;

always@(posedge clk) begin
  // pipeline stage 1
  valid_d <= i_valid;
  last_d <= i_payload_nums_last;
  k_d <= i_payload_k;
  if (i_valid) begin
    srl <= ext[32*14-1:0];

    inv1  <= (i_payload_nums_fragment < srl[32*1-1:32*(1-1)]) ? 1 : 0;
    inv2  <= (i_payload_nums_fragment < srl[32*2-1:32*(2-1)]) ? (inv1+1) : inv1;
    inv3  <= (i_payload_nums_fragment < srl[32*3-1:32*(3-1)]) ? (inv2+1) : inv2;
    inv4  <= (i_payload_nums_fragment < srl[32*4-1:32*(4-1)]) ? (inv3+1) : inv3;
    inv5  <= (i_payload_nums_fragment < srl[32*5-1:32*(5-1)]) ? (inv4+1) : inv4;
    inv6  <= (i_payload_nums_fragment < srl[32*6-1:32*(6-1)]) ? (inv5+1) : inv5;
    inv7  <= (i_payload_nums_fragment < srl[32*7-1:32*(7-1)]) ? (inv6+1) : inv6;
    inv7  <= (i_payload_nums_fragment < srl[32*7-1:32*(7-1)]) ? (inv6+1) : inv6;
    inv8  <= (i_payload_nums_fragment < srl[32*8-1:32*(8-1)]) ? (inv7+1) : inv7;
    inv9  <= (i_payload_nums_fragment < srl[32*9-1:32*(9-1)]) ? (inv8+1) : inv8;
    inv10 <= (i_payload_nums_fragment < srl[32*10-1:32*(10-1)]) ? (inv9+1) : inv9;
    inv11 <= (i_payload_nums_fragment < srl[32*11-1:32*(11-1)]) ? (inv10+1) : inv10;
    inv12 <= (i_payload_nums_fragment < srl[32*12-1:32*(12-1)]) ? (inv11+1) : inv11;
    inv13 <= (i_payload_nums_fragment < srl[32*13-1:32*(13-1)]) ? (inv12+1) : inv12;
    inv14 <= (i_payload_nums_fragment < srl[32*14-1:32*(14-1)]) ? (inv13+1) : inv13;
    
    if (i_payload_nums_last) begin
      count <= 1; // 1?
    end else if (!count[4]) begin // count to 16.
      count <= count + 1;
    end
    gate_d <= count >= i_payload_k;
  end

  // stage 2.  not sure optimal split for adder tree.
  sum16 <= mi1 + mi2 + mi3 + mi4 + mi5 + mi6;
  sum710 <= mi7 + mi8 + mi9 + mi10;
  sum1114 <= mi11 + mi12 + mi13 + mi14;
  valid_2d <= valid_d;
  last_2d <= last_d;
  gate_2d <= gate_d;

  if (reset) begin
    // last/gate are based on valids, so no need for extra resets.
    valid_d <= 0;
    valid_2d <= 0;
    count <= 1;
  end

end 


endmodule

Generated Verilog

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready,
  input wire i_valid,
  input wire [4-1:0] i_payload_k,
  input wire [32-1:0] i_payload_nums_fragment,
  input wire i_payload_nums_last,
  output wire [8-1:0] o_payload_fragment,
  output wire o_payload_last,
  output wire o_valid
);

// Define your design here
  // just for fun.  try not to stare directly at the code.

reg [32*14-1:0] srl = 0;
wire [32*15-1:0] ext = {srl, i_payload_nums_fragment};

reg inv1 = 0;

reg [1:0] inv2 = 0;
reg [1:0] inv3 = 0;

reg [2:0] inv4 = 0;
reg [2:0] inv5 = 0;
reg [2:0] inv6 = 0;
reg [2:0] inv7 = 0;

reg [3:0] inv8 = 0;
reg [3:0] inv9 = 0;
reg [3:0] inv10 = 0;
reg [3:0] inv11 = 0;
reg [3:0] inv12 = 0;
reg [3:0] inv13 = 0;
reg [3:0] inv14 = 0;

reg valid_d = 0;
reg last_d = 0;
reg [4-1:0] k_d = 0;
reg valid_2d = 0;
reg last_2d = 0;


// masked compares
wire       mi1  = (k_d >= 2) ? inv1 : 0;
wire [1:0] mi2  = (k_d >= 3) ? inv2 : 0;
wire [1:0] mi3  = (k_d >= 4) ? inv3 : 0;
wire [2:0] mi4  = (k_d >= 5) ? inv4 : 0;
wire [2:0] mi5  = (k_d >= 6) ? inv5 : 0; // 15
wire [2:0] mi6  = (k_d >= 7) ? inv6 : 0; // 21

wire [2:0] mi7  = (k_d >= 8) ? inv7 : 0;
wire [3:0] mi8  = (k_d >= 9) ? inv8 : 0;
wire [3:0] mi9  = (k_d >= 10) ? inv9 : 0;
wire [3:0] mi10 = (k_d >= 11) ? inv10 : 0; // 34
                                            
wire [3:0] mi11 = (k_d >= 12) ? inv11 : 0;
wire [3:0] mi12 = (k_d >= 13) ? inv12 : 0;
wire [3:0] mi13 = (k_d >= 14) ? inv13 : 0;
wire [3:0] mi14 = (k_d >= 15) ? inv14 : 0; // 50


reg [4:0] sum16 = 0;
reg [5:0] sum710 = 0;
reg [5:0] sum1114 = 0;
  
reg [4:0] count = 1;
reg gate_d = 0;
reg gate_2d = 0;

  //input wire i_valid,
  //input wire [4-1:0] i_payload_k, // probably stable?
  //input wire [32-1:0] i_payload_nums_fragment,
  //input wire i_payload_nums_last,
assign i_ready = ~reset;
assign o_payload_fragment = sum16 + sum710 + sum1114;
assign o_payload_last = last_2d && gate_2d;
assign o_valid = valid_2d && gate_2d;

always@(posedge clk) begin
  // pipeline stage 1
  valid_d <= i_valid;
  last_d <= i_payload_nums_last;
  k_d <= i_payload_k;
  if (i_valid) begin
    srl <= ext[32*14-1:0];

    inv1  <= (i_payload_nums_fragment < srl[32*1-1:32*(1-1)]) ? 1 : 0;
    inv2  <= (i_payload_nums_fragment < srl[32*2-1:32*(2-1)]) ? (inv1+1) : inv1;
    inv3  <= (i_payload_nums_fragment < srl[32*3-1:32*(3-1)]) ? (inv2+1) : inv2;
    inv4  <= (i_payload_nums_fragment < srl[32*4-1:32*(4-1)]) ? (inv3+1) : inv3;
    inv5  <= (i_payload_nums_fragment < srl[32*5-1:32*(5-1)]) ? (inv4+1) : inv4;
    inv6  <= (i_payload_nums_fragment < srl[32*6-1:32*(6-1)]) ? (inv5+1) : inv5;
    inv7  <= (i_payload_nums_fragment < srl[32*7-1:32*(7-1)]) ? (inv6+1) : inv6;
    inv7  <= (i_payload_nums_fragment < srl[32*7-1:32*(7-1)]) ? (inv6+1) : inv6;
    inv8  <= (i_payload_nums_fragment < srl[32*8-1:32*(8-1)]) ? (inv7+1) : inv7;
    inv9  <= (i_payload_nums_fragment < srl[32*9-1:32*(9-1)]) ? (inv8+1) : inv8;
    inv10 <= (i_payload_nums_fragment < srl[32*10-1:32*(10-1)]) ? (inv9+1) : inv9;
    inv11 <= (i_payload_nums_fragment < srl[32*11-1:32*(11-1)]) ? (inv10+1) : inv10;
    inv12 <= (i_payload_nums_fragment < srl[32*12-1:32*(12-1)]) ? (inv11+1) : inv11;
    inv13 <= (i_payload_nums_fragment < srl[32*13-1:32*(13-1)]) ? (inv12+1) : inv12;
    inv14 <= (i_payload_nums_fragment < srl[32*14-1:32*(14-1)]) ? (inv13+1) : inv13;
    
    if (i_payload_nums_last) begin
      count <= 1; // 1?
    end else if (!count[4]) begin // count to 16.
      count <= count + 1;
    end
    gate_d <= count >= i_payload_k;
  end

  // stage 2.  not sure optimal split for adder tree.
  sum16 <= mi1 + mi2 + mi3 + mi4 + mi5 + mi6;
  sum710 <= mi7 + mi8 + mi9 + mi10;
  sum1114 <= mi11 + mi12 + mi13 + mi14;
  valid_2d <= valid_d;
  last_2d <= last_d;
  gate_2d <= gate_d;

  if (reset) begin
    // last/gate are based on valids, so no need for extra resets.
    valid_d <= 0;
    valid_2d <= 0;
    count <= 1;
  end

end 


endmodule

Timing Analysis

Path 1-6.264 ns

From: k_d[3]$_DFF_P_/Q

To: sum16[4]$_DFF_P_/D

Data Arrival: 6.082 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`k_d[3]$_DFF_P_/CLK`
0.944	sky130_fd_sc_hvl__dfxtp_1	`k_d[3]$_DFF_P_/Q`
0.944	sky130_fd_sc_hvl__or2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11527/B`
1.696	sky130_fd_sc_hvl__or2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11527/X`
1.696	sky130_fd_sc_hvl__and3_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11550/C`
2.210	sky130_fd_sc_hvl__and3_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11550/X`
2.210	sky130_fd_sc_hvl__nor3_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11552/B`
2.593	sky130_fd_sc_hvl__nor3_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11552/Y`
2.593	sky130_fd_sc_hvl__xor2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11555/A`
2.817	sky130_fd_sc_hvl__xor2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11555/X`
2.817	sky130_fd_sc_hvl__and3_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11556/C`
3.256	sky130_fd_sc_hvl__and3_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11556/X`
3.256	sky130_fd_sc_hvl__nor2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11558/A`
3.467	sky130_fd_sc_hvl__nor2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11558/Y`
3.467	sky130_fd_sc_hvl__xor2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11561/A`
3.850	sky130_fd_sc_hvl__xor2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11561/X`
3.850	sky130_fd_sc_hvl__xor2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11563/B`
4.235	sky130_fd_sc_hvl__xor2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11563/X`
4.235	sky130_fd_sc_hvl__nor2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11565/A`
4.414	sky130_fd_sc_hvl__nor2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11565/Y`
4.414	sky130_fd_sc_hvl__or3_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11584/B`
5.095	sky130_fd_sc_hvl__or3_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11584/X`
5.095	sky130_fd_sc_hvl__nand2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11585/B`
5.261	sky130_fd_sc_hvl__nand2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11585/Y`
5.261	sky130_fd_sc_hvl__or2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11586/B`
5.461	sky130_fd_sc_hvl__or2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11586/X`
5.461	sky130_fd_sc_hvl__a21oi_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11592/A2`
5.647	sky130_fd_sc_hvl__a21oi_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11592/Y`
5.647	sky130_fd_sc_hvl__or2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11596/A`
6.082	sky130_fd_sc_hvl__or2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11596/X`
6.082	sky130_fd_sc_hvl__dfxtp_1	`sum16[4]$_DFF_P_/D`

Path 2-6.234 ns

From: k_d[3]$_DFF_P_/Q

To: sum710[4]$_DFF_P_/D

Data Arrival: 6.063 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`k_d[3]$_DFF_P_/CLK`
0.944	sky130_fd_sc_hvl__dfxtp_1	`k_d[3]$_DFF_P_/Q`
0.944	sky130_fd_sc_hvl__o21a_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11360/B1`
1.365	sky130_fd_sc_hvl__o21a_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11360/X`
1.365	sky130_fd_sc_hvl__a21o_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11362/B1`
1.826	sky130_fd_sc_hvl__a21o_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11362/X`
1.826	sky130_fd_sc_hvl__and3_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11369/C`
2.298	sky130_fd_sc_hvl__and3_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11369/X`
2.298	sky130_fd_sc_hvl__or2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11371/A`
2.849	sky130_fd_sc_hvl__or2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11371/X`
2.849	sky130_fd_sc_hvl__xor2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11374/A`
3.159	sky130_fd_sc_hvl__xor2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11374/X`
3.159	sky130_fd_sc_hvl__or3_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11375/C`
3.775	sky130_fd_sc_hvl__or3_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11375/X`
3.775	sky130_fd_sc_hvl__and2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11377/A`
4.147	sky130_fd_sc_hvl__and2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11377/X`
4.147	sky130_fd_sc_hvl__nand3_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11379/C`
4.284	sky130_fd_sc_hvl__nand3_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11379/Y`
4.284	sky130_fd_sc_hvl__nand2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11383/B`
4.508	sky130_fd_sc_hvl__nand2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11383/Y`
4.508	sky130_fd_sc_hvl__xnor2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11397/A`
4.894	sky130_fd_sc_hvl__xnor2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11397/Y`
4.894	sky130_fd_sc_hvl__o21ai_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11399/A2`
5.245	sky130_fd_sc_hvl__o21ai_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11399/Y`
5.245	sky130_fd_sc_hvl__nand2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11414/A`
5.473	sky130_fd_sc_hvl__nand2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11414/Y`
5.473	sky130_fd_sc_hvl__a21o_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11419/A2`
5.802	sky130_fd_sc_hvl__a21o_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11419/X`
5.802	sky130_fd_sc_hvl__and2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11421/A`
6.063	sky130_fd_sc_hvl__and2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11421/X`
6.063	sky130_fd_sc_hvl__dfxtp_1	`sum710[4]$_DFF_P_/D`

Path 3-6.029 ns

From: k_d[3]$_DFF_P_/Q

To: sum710[5]$_DFF_P_/D

Data Arrival: 5.882 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`k_d[3]$_DFF_P_/CLK`
0.944	sky130_fd_sc_hvl__dfxtp_1	`k_d[3]$_DFF_P_/Q`
0.944	sky130_fd_sc_hvl__o21a_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11360/B1`
1.365	sky130_fd_sc_hvl__o21a_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11360/X`
1.365	sky130_fd_sc_hvl__a21o_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11362/B1`
1.826	sky130_fd_sc_hvl__a21o_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11362/X`
1.826	sky130_fd_sc_hvl__and3_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11369/C`
2.298	sky130_fd_sc_hvl__and3_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11369/X`
2.298	sky130_fd_sc_hvl__or2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11371/A`
2.849	sky130_fd_sc_hvl__or2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11371/X`
2.849	sky130_fd_sc_hvl__xor2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11374/A`
3.159	sky130_fd_sc_hvl__xor2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11374/X`
3.159	sky130_fd_sc_hvl__or3_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11375/C`
3.775	sky130_fd_sc_hvl__or3_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11375/X`
3.775	sky130_fd_sc_hvl__and2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11377/A`
4.147	sky130_fd_sc_hvl__and2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11377/X`
4.147	sky130_fd_sc_hvl__nand3_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11379/C`
4.284	sky130_fd_sc_hvl__nand3_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11379/Y`
4.284	sky130_fd_sc_hvl__nand2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11383/B`
4.508	sky130_fd_sc_hvl__nand2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11383/Y`
4.508	sky130_fd_sc_hvl__xnor2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11397/A`
4.894	sky130_fd_sc_hvl__xnor2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11397/Y`
4.894	sky130_fd_sc_hvl__o21ai_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11399/A2`
5.245	sky130_fd_sc_hvl__o21ai_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11399/Y`
5.245	sky130_fd_sc_hvl__nand2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11414/A`
5.473	sky130_fd_sc_hvl__nand2_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11414/Y`
5.473	sky130_fd_sc_hvl__a21o_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11419/A2`
5.802	sky130_fd_sc_hvl__a21o_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11419/X`
5.802	sky130_fd_sc_hvl__o21ai_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11524/B1`
5.882	sky130_fd_sc_hvl__o21ai_1	`$abc$11069$auto$blifparse.cc:396:parse_blif$11524/Y`
5.882	sky130_fd_sc_hvl__dfxtp_1	`sum710[5]$_DFF_P_/D`

Post-Synthesis Verilog

Download synth.v