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SpinalHDL
Amaranth
Bluespec Classic
Bluespec SV
Chisel
Clash
HardCaml
PipelineC
ROHD
Spade
SpinalHDL
TL-Verilog
Veryl
Verilog
VHDL
Reset from template
import spinal.core._ import spinal.lib._ // Stream-based solution component // // Input stream interface: // io.i.ready (output): Assert when ready to accept input // io.i.valid (input): Asserted when input data is valid // io.i.payload.* (input): Input payload fields // // Output interface: // io.o.valid (output): Assert when output data is valid // io.o.payload* (output): Output payload fields // // Handshaking: Data transfers when both ready and valid are high case class Solution() extends Component { val io = new Bundle { val i = slave Stream(new Bundle { val k = UInt(4 bits) val nums = Fragment(SInt(32 bits)) }) val o = master Flow(Fragment(UInt(8 bits))) } // Your code here }
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ns
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μm²
1
piasa-dev
Verilog
43.83 (7 cycles)
159.72
60200
2
fayalalebrun
SpinalHDL
68.11 (5 cycles)
73.42
171766
3
Ivan Buda Mandura
Verilog
155.36 (5 cycles)
32.18
98753
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