Number of Inversions in Sliding Window

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Submitted Solution

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

// I updated the comments on the site, so the formatting is different in places.

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready,
  input wire i_valid,
  input wire [4-1:0] i_payload_k,
  input wire [32-1:0] i_payload_nums_fragment,
  input wire i_payload_nums_last,
  output wire [8-1:0] o_payload_fragment,
  output wire o_payload_last,
  output wire o_valid
);

// Define your design here
  // just for fun.  try not to stare directly at the code.

  // design is based on a data shift register
reg [32*14-1:0] srl = 0;
wire [32*15-1:0] ext = {srl, i_payload_nums_fragment};

  // inversion counts fancy shift register.
  // size increases as more inversions become possible.
reg inv1 = 0;

reg [1:0] inv2 = 0;
reg [1:0] inv3 = 0;

reg [2:0] inv4 = 0;
reg [2:0] inv5 = 0;
reg [2:0] inv6 = 0;
reg [2:0] inv7 = 0;

reg [3:0] inv8 = 0;
reg [3:0] inv9 = 0;
reg [3:0] inv10 = 0;
reg [3:0] inv11 = 0;
reg [3:0] inv12 = 0;
reg [3:0] inv13 = 0;
reg [3:0] inv14 = 0;

  // controls
reg valid_d = 0;
reg last_d = 0;
reg [4-1:0] k_d = 0;
reg valid_2d = 0;
reg last_2d = 0;


// masked compares
  // This is how the windowing is handled.  the inversion (shift) registers
  // are sized for the worst case and then masked for the actual case.
  // this also allow you to dynamically change i_payload_k if you're satan.
wire       mi1  = (k_d >= 2) ? inv1 : 0;
wire [1:0] mi2  = (k_d >= 3) ? inv2 : 0;
wire [1:0] mi3  = (k_d >= 4) ? inv3 : 0;
wire [2:0] mi4  = (k_d >= 5) ? inv4 : 0;
wire [2:0] mi5  = (k_d >= 6) ? inv5 : 0; // 15
wire [2:0] mi6  = (k_d >= 7) ? inv6 : 0; // 21

wire [2:0] mi7  = (k_d >= 8) ? inv7 : 0;
wire [3:0] mi8  = (k_d >= 9) ? inv8 : 0;
wire [3:0] mi9  = (k_d >= 10) ? inv9 : 0;
wire [3:0] mi10 = (k_d >= 11) ? inv10 : 0; // 34
                                            
wire [3:0] mi11 = (k_d >= 12) ? inv11 : 0;
wire [3:0] mi12 = (k_d >= 13) ? inv12 : 0;
wire [3:0] mi13 = (k_d >= 14) ? inv13 : 0;
wire [3:0] mi14 = (k_d >= 15) ? inv14 : 0; // 50

// adder tree attempt.  sumxy is the sum of mix to miy.
  // it makes enough sense in context.
reg [4:0] sum16 = 0;
reg [5:0] sum710 = 0;
reg [5:0] sum1114 = 0;
  
  // gate outputs if there haven't been k outputs.
  // (ok, i didn't test changing i_payload_k during a packet.  that was a joke)
reg [4:0] count = 1;
reg gate_d = 0;
reg gate_2d = 0;

// ready.  put reset here to be nice.
assign i_ready = ~reset;
  // final part of adder tree
assign o_payload_fragment = sum16 + sum710 + sum1114;
  // gated control outputs.
assign o_payload_last = last_2d && gate_2d;
assign o_valid = valid_2d && gate_2d;

always@(posedge clk) begin
  // pipeline stage 1
  valid_d <= i_valid;
  last_d <= i_payload_nums_last;
  k_d <= i_payload_k;
  if (i_valid) begin
    srl <= ext[32*14-1:0]; // data shift reg

    // if input < srl[n] then inv[n+1] = inv[n] + 1, else inv[n] + 0.
    // so a low valued input will increment multiple of these.
    // this avoids recomputing the entire problem.
    // inv[n] thus represents the number of inputs up to n samples in the past that
    // are less than srl[n].  (might have off-by-one in explanation, should double check)
    // the output then sums some number of these based on k.
    inv1  <= (i_payload_nums_fragment < srl[32*1-1:32*(1-1)]) ? 1 : 0;
    inv2  <= (i_payload_nums_fragment < srl[32*2-1:32*(2-1)]) ? (inv1+1) : inv1;
    inv3  <= (i_payload_nums_fragment < srl[32*3-1:32*(3-1)]) ? (inv2+1) : inv2;
    inv4  <= (i_payload_nums_fragment < srl[32*4-1:32*(4-1)]) ? (inv3+1) : inv3;
    inv5  <= (i_payload_nums_fragment < srl[32*5-1:32*(5-1)]) ? (inv4+1) : inv4;
    inv6  <= (i_payload_nums_fragment < srl[32*6-1:32*(6-1)]) ? (inv5+1) : inv5;
    inv7  <= (i_payload_nums_fragment < srl[32*7-1:32*(7-1)]) ? (inv6+1) : inv6;
    inv7  <= (i_payload_nums_fragment < srl[32*7-1:32*(7-1)]) ? (inv6+1) : inv6;
    inv8  <= (i_payload_nums_fragment < srl[32*8-1:32*(8-1)]) ? (inv7+1) : inv7;
    inv9  <= (i_payload_nums_fragment < srl[32*9-1:32*(9-1)]) ? (inv8+1) : inv8;
    inv10 <= (i_payload_nums_fragment < srl[32*10-1:32*(10-1)]) ? (inv9+1) : inv9;
    inv11 <= (i_payload_nums_fragment < srl[32*11-1:32*(11-1)]) ? (inv10+1) : inv10;
    inv12 <= (i_payload_nums_fragment < srl[32*12-1:32*(12-1)]) ? (inv11+1) : inv11;
    inv13 <= (i_payload_nums_fragment < srl[32*13-1:32*(13-1)]) ? (inv12+1) : inv12;
    inv14 <= (i_payload_nums_fragment < srl[32*14-1:32*(14-1)]) ? (inv13+1) : inv13;
    
    // gating
    if (i_payload_nums_last) begin
      count <= 1; // 1?
    end else if (!count[4]) begin // count to 16.
      count <= count + 1;
    end
    gate_d <= count >= i_payload_k;
  end

  // stage 2.  not sure optimal split for adder tree.
  sum16 <= mi1 + mi2 + mi3 + mi4 + mi5 + mi6;
  sum710 <= mi7 + mi8 + mi9 + mi10;
  sum1114 <= mi11 + mi12 + mi13 + mi14;
  valid_2d <= valid_d;
  last_2d <= last_d;
  gate_2d <= gate_d;
  
  // I was lazy and left out the resets for inv.  these need to be reset after each problem.
  // also handle the case where last is set without valid.  just to be nice.
  if (last_d && valid_d) begin
    {inv1, inv2, inv3, inv4, inv5, inv6, inv7, inv8, inv9, inv10, inv11, inv12, inv13, inv14} <= '0;
  end

  if (reset) begin
    // last/gate are based on valids, so no need for extra resets.
    valid_d <= 0;
    valid_2d <= 0;
    count <= 1;
  end

end 

endmodule

Generated Verilog

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

// I updated the comments on the site, so the formatting is different in places.

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready,
  input wire i_valid,
  input wire [4-1:0] i_payload_k,
  input wire [32-1:0] i_payload_nums_fragment,
  input wire i_payload_nums_last,
  output wire [8-1:0] o_payload_fragment,
  output wire o_payload_last,
  output wire o_valid
);

// Define your design here
  // just for fun.  try not to stare directly at the code.

  // design is based on a data shift register
reg [32*14-1:0] srl = 0;
wire [32*15-1:0] ext = {srl, i_payload_nums_fragment};

  // inversion counts fancy shift register.
  // size increases as more inversions become possible.
reg inv1 = 0;

reg [1:0] inv2 = 0;
reg [1:0] inv3 = 0;

reg [2:0] inv4 = 0;
reg [2:0] inv5 = 0;
reg [2:0] inv6 = 0;
reg [2:0] inv7 = 0;

reg [3:0] inv8 = 0;
reg [3:0] inv9 = 0;
reg [3:0] inv10 = 0;
reg [3:0] inv11 = 0;
reg [3:0] inv12 = 0;
reg [3:0] inv13 = 0;
reg [3:0] inv14 = 0;

  // controls
reg valid_d = 0;
reg last_d = 0;
reg [4-1:0] k_d = 0;
reg valid_2d = 0;
reg last_2d = 0;


// masked compares
  // This is how the windowing is handled.  the inversion (shift) registers
  // are sized for the worst case and then masked for the actual case.
  // this also allow you to dynamically change i_payload_k if you're satan.
wire       mi1  = (k_d >= 2) ? inv1 : 0;
wire [1:0] mi2  = (k_d >= 3) ? inv2 : 0;
wire [1:0] mi3  = (k_d >= 4) ? inv3 : 0;
wire [2:0] mi4  = (k_d >= 5) ? inv4 : 0;
wire [2:0] mi5  = (k_d >= 6) ? inv5 : 0; // 15
wire [2:0] mi6  = (k_d >= 7) ? inv6 : 0; // 21

wire [2:0] mi7  = (k_d >= 8) ? inv7 : 0;
wire [3:0] mi8  = (k_d >= 9) ? inv8 : 0;
wire [3:0] mi9  = (k_d >= 10) ? inv9 : 0;
wire [3:0] mi10 = (k_d >= 11) ? inv10 : 0; // 34
                                            
wire [3:0] mi11 = (k_d >= 12) ? inv11 : 0;
wire [3:0] mi12 = (k_d >= 13) ? inv12 : 0;
wire [3:0] mi13 = (k_d >= 14) ? inv13 : 0;
wire [3:0] mi14 = (k_d >= 15) ? inv14 : 0; // 50

// adder tree attempt.  sumxy is the sum of mix to miy.
  // it makes enough sense in context.
reg [4:0] sum16 = 0;
reg [5:0] sum710 = 0;
reg [5:0] sum1114 = 0;
  
  // gate outputs if there haven't been k outputs.
  // (ok, i didn't test changing i_payload_k during a packet.  that was a joke)
reg [4:0] count = 1;
reg gate_d = 0;
reg gate_2d = 0;

// ready.  put reset here to be nice.
assign i_ready = ~reset;
  // final part of adder tree
assign o_payload_fragment = sum16 + sum710 + sum1114;
  // gated control outputs.
assign o_payload_last = last_2d && gate_2d;
assign o_valid = valid_2d && gate_2d;

always@(posedge clk) begin
  // pipeline stage 1
  valid_d <= i_valid;
  last_d <= i_payload_nums_last;
  k_d <= i_payload_k;
  if (i_valid) begin
    srl <= ext[32*14-1:0]; // data shift reg

    // if input < srl[n] then inv[n+1] = inv[n] + 1, else inv[n] + 0.
    // so a low valued input will increment multiple of these.
    // this avoids recomputing the entire problem.
    // inv[n] thus represents the number of inputs up to n samples in the past that
    // are less than srl[n].  (might have off-by-one in explanation, should double check)
    // the output then sums some number of these based on k.
    inv1  <= (i_payload_nums_fragment < srl[32*1-1:32*(1-1)]) ? 1 : 0;
    inv2  <= (i_payload_nums_fragment < srl[32*2-1:32*(2-1)]) ? (inv1+1) : inv1;
    inv3  <= (i_payload_nums_fragment < srl[32*3-1:32*(3-1)]) ? (inv2+1) : inv2;
    inv4  <= (i_payload_nums_fragment < srl[32*4-1:32*(4-1)]) ? (inv3+1) : inv3;
    inv5  <= (i_payload_nums_fragment < srl[32*5-1:32*(5-1)]) ? (inv4+1) : inv4;
    inv6  <= (i_payload_nums_fragment < srl[32*6-1:32*(6-1)]) ? (inv5+1) : inv5;
    inv7  <= (i_payload_nums_fragment < srl[32*7-1:32*(7-1)]) ? (inv6+1) : inv6;
    inv7  <= (i_payload_nums_fragment < srl[32*7-1:32*(7-1)]) ? (inv6+1) : inv6;
    inv8  <= (i_payload_nums_fragment < srl[32*8-1:32*(8-1)]) ? (inv7+1) : inv7;
    inv9  <= (i_payload_nums_fragment < srl[32*9-1:32*(9-1)]) ? (inv8+1) : inv8;
    inv10 <= (i_payload_nums_fragment < srl[32*10-1:32*(10-1)]) ? (inv9+1) : inv9;
    inv11 <= (i_payload_nums_fragment < srl[32*11-1:32*(11-1)]) ? (inv10+1) : inv10;
    inv12 <= (i_payload_nums_fragment < srl[32*12-1:32*(12-1)]) ? (inv11+1) : inv11;
    inv13 <= (i_payload_nums_fragment < srl[32*13-1:32*(13-1)]) ? (inv12+1) : inv12;
    inv14 <= (i_payload_nums_fragment < srl[32*14-1:32*(14-1)]) ? (inv13+1) : inv13;
    
    // gating
    if (i_payload_nums_last) begin
      count <= 1; // 1?
    end else if (!count[4]) begin // count to 16.
      count <= count + 1;
    end
    gate_d <= count >= i_payload_k;
  end

  // stage 2.  not sure optimal split for adder tree.
  sum16 <= mi1 + mi2 + mi3 + mi4 + mi5 + mi6;
  sum710 <= mi7 + mi8 + mi9 + mi10;
  sum1114 <= mi11 + mi12 + mi13 + mi14;
  valid_2d <= valid_d;
  last_2d <= last_d;
  gate_2d <= gate_d;
  
  // I was lazy and left out the resets for inv.  these need to be reset after each problem.
  // also handle the case where last is set without valid.  just to be nice.
  if (last_d && valid_d) begin
    {inv1, inv2, inv3, inv4, inv5, inv6, inv7, inv8, inv9, inv10, inv11, inv12, inv13, inv14} <= '0;
  end

  if (reset) begin
    // last/gate are based on valids, so no need for extra resets.
    valid_d <= 0;
    valid_2d <= 0;
    count <= 1;
  end

end 

endmodule

Timing Analysis

Path 1-6.530 ns

From: k_d[3]$_DFF_P_/Q

To: sum16[3]$_DFF_P_/D

Data Arrival: 6.359 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`k_d[3]$_DFF_P_/CLK`
0.862	sky130_fd_sc_hvl__dfxtp_1	`k_d[3]$_DFF_P_/Q`
0.862	sky130_fd_sc_hvl__or2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11366/B`
1.580	sky130_fd_sc_hvl__or2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11366/X`
1.580	sky130_fd_sc_hvl__and3_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11389/C`
2.025	sky130_fd_sc_hvl__and3_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11389/X`
2.025	sky130_fd_sc_hvl__or2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11392/A`
2.525	sky130_fd_sc_hvl__or2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11392/X`
2.525	sky130_fd_sc_hvl__xor2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11394/A`
2.826	sky130_fd_sc_hvl__xor2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11394/X`
2.826	sky130_fd_sc_hvl__or3_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11395/C`
3.442	sky130_fd_sc_hvl__or3_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11395/X`
3.442	sky130_fd_sc_hvl__and2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11397/A`
3.814	sky130_fd_sc_hvl__and2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11397/X`
3.814	sky130_fd_sc_hvl__xor2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11400/A`
4.144	sky130_fd_sc_hvl__xor2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11400/X`
4.144	sky130_fd_sc_hvl__xor2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11402/B`
4.529	sky130_fd_sc_hvl__xor2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11402/X`
4.529	sky130_fd_sc_hvl__nor2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11404/A`
4.675	sky130_fd_sc_hvl__nor2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11404/Y`
4.675	sky130_fd_sc_hvl__nor2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11407/B`
4.933	sky130_fd_sc_hvl__nor2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11407/Y`
4.933	sky130_fd_sc_hvl__xnor2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11421/A`
5.253	sky130_fd_sc_hvl__xnor2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11421/Y`
5.253	sky130_fd_sc_hvl__nor2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11422/B`
5.412	sky130_fd_sc_hvl__nor2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11422/Y`
5.412	sky130_fd_sc_hvl__or3_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11429/B`
6.060	sky130_fd_sc_hvl__or3_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11429/X`
6.060	sky130_fd_sc_hvl__and2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11430/B`
6.359	sky130_fd_sc_hvl__and2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11430/X`
6.359	sky130_fd_sc_hvl__dfxtp_1	`sum16[3]$_DFF_P_/D`

Path 2-6.426 ns

From: k_d[1]$_DFF_P_/Q

To: sum710[4]$_DFF_P_/D

Data Arrival: 6.255 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`k_d[1]$_DFF_P_/CLK`
0.731	sky130_fd_sc_hvl__dfxtp_1	`k_d[1]$_DFF_P_/Q`
0.731	sky130_fd_sc_hvl__or2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11373/B`
1.275	sky130_fd_sc_hvl__or2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11373/X`
1.275	sky130_fd_sc_hvl__o21a_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11436/A2`
1.760	sky130_fd_sc_hvl__o21a_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11436/X`
1.760	sky130_fd_sc_hvl__and3_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11437/C`
2.217	sky130_fd_sc_hvl__and3_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11437/X`
2.217	sky130_fd_sc_hvl__or2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11440/A`
2.761	sky130_fd_sc_hvl__or2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11440/X`
2.761	sky130_fd_sc_hvl__xor2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11454/B`
3.064	sky130_fd_sc_hvl__xor2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11454/X`
3.064	sky130_fd_sc_hvl__or3_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11457/C`
3.679	sky130_fd_sc_hvl__or3_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11457/X`
3.679	sky130_fd_sc_hvl__and2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11458/B`
4.072	sky130_fd_sc_hvl__and2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11458/X`
4.072	sky130_fd_sc_hvl__xnor2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11475/B`
4.365	sky130_fd_sc_hvl__xnor2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11475/Y`
4.365	sky130_fd_sc_hvl__o21ai_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11476/B1`
4.561	sky130_fd_sc_hvl__o21ai_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11476/Y`
4.561	sky130_fd_sc_hvl__nand2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11483/A`
4.807	sky130_fd_sc_hvl__nand2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11483/Y`
4.807	sky130_fd_sc_hvl__or2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11484/B`
5.321	sky130_fd_sc_hvl__or2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11484/X`
5.321	sky130_fd_sc_hvl__a21o_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11485/A2`
5.679	sky130_fd_sc_hvl__a21o_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11485/X`
5.679	sky130_fd_sc_hvl__a21o_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11488/A2`
5.995	sky130_fd_sc_hvl__a21o_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11488/X`
5.995	sky130_fd_sc_hvl__and2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11598/A`
6.255	sky130_fd_sc_hvl__and2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11598/X`
6.255	sky130_fd_sc_hvl__dfxtp_1	`sum710[4]$_DFF_P_/D`

Path 3-6.350 ns

From: k_d[3]$_DFF_P_/Q

To: sum1114[4]$_DFF_P_/D

Data Arrival: 6.179 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`k_d[3]$_DFF_P_/CLK`
0.862	sky130_fd_sc_hvl__dfxtp_1	`k_d[3]$_DFF_P_/Q`
0.862	sky130_fd_sc_hvl__and2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11442/B`
1.453	sky130_fd_sc_hvl__and2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11442/X`
1.453	sky130_fd_sc_hvl__o21a_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11491/B1`
1.884	sky130_fd_sc_hvl__o21a_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11491/X`
1.884	sky130_fd_sc_hvl__and3_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11509/C`
2.324	sky130_fd_sc_hvl__and3_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11509/X`
2.324	sky130_fd_sc_hvl__or2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11513/A`
2.819	sky130_fd_sc_hvl__or2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11513/X`
2.819	sky130_fd_sc_hvl__xor2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11531/B`
3.043	sky130_fd_sc_hvl__xor2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11531/X`
3.043	sky130_fd_sc_hvl__and2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11532/B`
3.343	sky130_fd_sc_hvl__and2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11532/X`
3.343	sky130_fd_sc_hvl__nor2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11534/A`
3.480	sky130_fd_sc_hvl__nor2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11534/Y`
3.480	sky130_fd_sc_hvl__and3_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11535/C`
3.914	sky130_fd_sc_hvl__and3_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11535/X`
3.914	sky130_fd_sc_hvl__or3_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11544/B`
4.596	sky130_fd_sc_hvl__or3_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11544/X`
4.596	sky130_fd_sc_hvl__nand2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11545/B`
4.762	sky130_fd_sc_hvl__nand2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11545/Y`
4.762	sky130_fd_sc_hvl__or2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11546/B`
4.964	sky130_fd_sc_hvl__or2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11546/X`
4.964	sky130_fd_sc_hvl__a21oi_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11547/A2`
5.211	sky130_fd_sc_hvl__a21oi_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11547/Y`
5.211	sky130_fd_sc_hvl__or3_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11606/B`
5.881	sky130_fd_sc_hvl__or3_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11606/X`
5.881	sky130_fd_sc_hvl__and2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11607/B`
6.179	sky130_fd_sc_hvl__and2_1	`$abc$11194$auto$blifparse.cc:396:parse_blif$11607/X`
6.179	sky130_fd_sc_hvl__dfxtp_1	`sum1114[4]$_DFF_P_/D`

Post-Synthesis Verilog

Download synth.v