Roulette - Latchup

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Submission #7

PASSED

RankingPercentile

Latency

9367.60 (1005 cycles)ns

1st

top 1%

Max Frequency

107.28MHz

1st

top 1%

Area

16119μm²

6th

top 100%

Submitted Solution

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready,
  input wire i_valid,
  input wire [16-1:0] i_payload_spins_fragment,
  input wire i_payload_spins_last,
  output wire [16-1:0] o_payload,
  output wire o_valid
);

// Define your design here
  
reg [14:0] abs_1d = 0;
reg sign_1d = 0;
reg valid_1d = 0;
reg last_1d = 0;

reg [14:0] abs_2d = 0;
reg [9:0] spins_2d = 0;
reg sign_2d = 0;
reg valid_2d = 0;
reg last_2d = 0;

reg [6:0] rem_3d = 0;
reg [9:0] spins_3d = 0;
reg sign_3d = 0;
reg valid_3d = 0;
reg last_3d = 0;

reg signed [7:0] pos_4d;
reg [9:0] spins_4d = 0;
reg valid_4d = 0;
reg last_4d = 0;

reg [15:0] result_5d = 0;
reg first_5d = 0;
reg valid_5d = 0;
reg last_5d = 0;

wire [15+16-1:0] mult_1d = (14'sh147B * abs_1d); // multiplies are usually pretty cheap at small size

always@(posedge clk) begin
    // absolute value
    abs_1d <= (i_payload_spins_fragment[15]) ? (~i_payload_spins_fragment[14:0] + 1) : i_payload_spins_fragment[14:0];
    sign_1d <= i_payload_spins_fragment[15];
    valid_1d <= i_valid;
    last_1d <= i_payload_spins_last;

    // division by multiplication
    spins_2d <= mult_1d >> 19;
    abs_2d <= abs_1d;
    sign_2d <= sign_1d;
    valid_2d <= valid_1d;
    last_2d <= last_1d;

    // multiply and subtract for modulo.
    spins_3d <= spins_2d;
    rem_3d <= abs_2d - (spins_2d << 6) - (spins_2d << 5) - (spins_2d << 2);
    sign_3d <= sign_2d;
    valid_3d <= valid_2d;
    last_3d <= last_2d;

    // check for wrap.
    if (valid_3d) begin
        if (sign_3d) begin
            if (pos_4d < rem_3d) begin // not sure where the wrap happens.
                pos_4d <= last_3d ? 50 : (pos_4d - rem_3d + 100);
            end else begin
                pos_4d <= last_3d ? 50 : (pos_4d - rem_3d);
            end
          
            // "crossing" 0 has some complex logic
            if (pos_4d == 0 || rem_3d == 0) begin
                spins_4d <= spins_3d;
            //end else if (pos_4d - $signed(rem_3d) <= 0) begin
            end else if (pos_4d <= rem_3d) begin
                spins_4d <= spins_3d + 1;
            end else begin
                spins_4d <= spins_3d;
            end
          
        end else begin
            if (pos_4d + rem_3d >= 100) begin // correct?
                pos_4d <= last_3d ? 50 : (pos_4d + rem_3d - 100);
            end else begin
                pos_4d <= last_3d ? 50 : (pos_4d + rem_3d);
            end
            spins_4d <= spins_3d + (pos_4d + rem_3d >= 100);
        end
    end
    valid_4d <= valid_3d;
    last_4d <= last_3d;

    // final accumulation
    if (valid_4d) begin
        if (first_5d) begin
            result_5d <= spins_4d;
        end else begin
            result_5d <= result_5d + spins_4d;
        end
        first_5d <= last_4d;
    end
    valid_5d <= valid_4d && last_4d; // only output the total.

    // only reset important state
    if (reset) begin
        first_5d <= 1;
        pos_4d <= 50;
        valid_1d <= 0;
        valid_2d <= 0;
        valid_3d <= 0;
        valid_4d <= 0;
        valid_5d <= 0;
    end
end

assign i_ready = !reset;
assign o_payload = result_5d;
assign o_valid = valid_5d;

endmodule

Generated Verilog

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready,
  input wire i_valid,
  input wire [16-1:0] i_payload_spins_fragment,
  input wire i_payload_spins_last,
  output wire [16-1:0] o_payload,
  output wire o_valid
);

// Define your design here
  
reg [14:0] abs_1d = 0;
reg sign_1d = 0;
reg valid_1d = 0;
reg last_1d = 0;

reg [14:0] abs_2d = 0;
reg [9:0] spins_2d = 0;
reg sign_2d = 0;
reg valid_2d = 0;
reg last_2d = 0;

reg [6:0] rem_3d = 0;
reg [9:0] spins_3d = 0;
reg sign_3d = 0;
reg valid_3d = 0;
reg last_3d = 0;

reg signed [7:0] pos_4d;
reg [9:0] spins_4d = 0;
reg valid_4d = 0;
reg last_4d = 0;

reg [15:0] result_5d = 0;
reg first_5d = 0;
reg valid_5d = 0;
reg last_5d = 0;

wire [15+16-1:0] mult_1d = (14'sh147B * abs_1d); // multiplies are usually pretty cheap at small size

always@(posedge clk) begin
    // absolute value
    abs_1d <= (i_payload_spins_fragment[15]) ? (~i_payload_spins_fragment[14:0] + 1) : i_payload_spins_fragment[14:0];
    sign_1d <= i_payload_spins_fragment[15];
    valid_1d <= i_valid;
    last_1d <= i_payload_spins_last;

    // division by multiplication
    spins_2d <= mult_1d >> 19;
    abs_2d <= abs_1d;
    sign_2d <= sign_1d;
    valid_2d <= valid_1d;
    last_2d <= last_1d;

    // multiply and subtract for modulo.
    spins_3d <= spins_2d;
    rem_3d <= abs_2d - (spins_2d << 6) - (spins_2d << 5) - (spins_2d << 2);
    sign_3d <= sign_2d;
    valid_3d <= valid_2d;
    last_3d <= last_2d;

    // check for wrap.
    if (valid_3d) begin
        if (sign_3d) begin
            if (pos_4d < rem_3d) begin // not sure where the wrap happens.
                pos_4d <= last_3d ? 50 : (pos_4d - rem_3d + 100);
            end else begin
                pos_4d <= last_3d ? 50 : (pos_4d - rem_3d);
            end
          
            // "crossing" 0 has some complex logic
            if (pos_4d == 0 || rem_3d == 0) begin
                spins_4d <= spins_3d;
            //end else if (pos_4d - $signed(rem_3d) <= 0) begin
            end else if (pos_4d <= rem_3d) begin
                spins_4d <= spins_3d + 1;
            end else begin
                spins_4d <= spins_3d;
            end
          
        end else begin
            if (pos_4d + rem_3d >= 100) begin // correct?
                pos_4d <= last_3d ? 50 : (pos_4d + rem_3d - 100);
            end else begin
                pos_4d <= last_3d ? 50 : (pos_4d + rem_3d);
            end
            spins_4d <= spins_3d + (pos_4d + rem_3d >= 100);
        end
    end
    valid_4d <= valid_3d;
    last_4d <= last_3d;

    // final accumulation
    if (valid_4d) begin
        if (first_5d) begin
            result_5d <= spins_4d;
        end else begin
            result_5d <= result_5d + spins_4d;
        end
        first_5d <= last_4d;
    end
    valid_5d <= valid_4d && last_4d; // only output the total.

    // only reset important state
    if (reset) begin
        first_5d <= 1;
        pos_4d <= 50;
        valid_1d <= 0;
        valid_2d <= 0;
        valid_3d <= 0;
        valid_4d <= 0;
        valid_5d <= 0;
    end
end

assign i_ready = !reset;
assign o_payload = result_5d;
assign o_valid = valid_5d;

endmodule

Timing Analysis

Path 1-9.322 ns

From: abs_1d[11]$_DFF_P_/Q

To: spins_2d[7]$_DFF_P_/D

Data Arrival: 9.121 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`abs_1d[11]$_DFF_P_/CLK`
1.260	sky130_fd_sc_hvl__dfxtp_1	`abs_1d[11]$_DFF_P_/Q`
1.260	sky130_fd_sc_hvl__xor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5578/B`
1.845	sky130_fd_sc_hvl__xor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5578/X`
1.845	sky130_fd_sc_hvl__xor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5640/A`
2.362	sky130_fd_sc_hvl__xor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5640/X`
2.362	sky130_fd_sc_hvl__o21ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5643/A1`
2.683	sky130_fd_sc_hvl__o21ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5643/Y`
2.683	sky130_fd_sc_hvl__xnor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5646/A`
3.069	sky130_fd_sc_hvl__xnor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5646/Y`
3.069	sky130_fd_sc_hvl__o21ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5651/A1`
3.373	sky130_fd_sc_hvl__o21ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5651/Y`
3.373	sky130_fd_sc_hvl__xnor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5654/A`
3.779	sky130_fd_sc_hvl__xnor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5654/Y`
3.779	sky130_fd_sc_hvl__o21a_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5660/A1`
4.186	sky130_fd_sc_hvl__o21a_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5660/X`
4.186	sky130_fd_sc_hvl__xnor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5663/A`
4.555	sky130_fd_sc_hvl__xnor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5663/Y`
4.555	sky130_fd_sc_hvl__xor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5914/B`
4.901	sky130_fd_sc_hvl__xor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5914/X`
4.901	sky130_fd_sc_hvl__o21a_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5915/B1`
5.158	sky130_fd_sc_hvl__o21a_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5915/X`
5.158	sky130_fd_sc_hvl__or2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5921/A`
5.585	sky130_fd_sc_hvl__or2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5921/X`
5.585	sky130_fd_sc_hvl__or3_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5923/B`
6.265	sky130_fd_sc_hvl__or3_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5923/X`
6.265	sky130_fd_sc_hvl__a21oi_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5924/B1`
6.455	sky130_fd_sc_hvl__a21oi_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5924/Y`
6.455	sky130_fd_sc_hvl__o22ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5927/B1`
6.758	sky130_fd_sc_hvl__o22ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5927/Y`
6.758	sky130_fd_sc_hvl__o21a_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5929/A2`
7.179	sky130_fd_sc_hvl__o21a_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5929/X`
7.179	sky130_fd_sc_hvl__o21ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5949/A1`
7.501	sky130_fd_sc_hvl__o21ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5949/Y`
7.501	sky130_fd_sc_hvl__a21o_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5965/A1`
7.884	sky130_fd_sc_hvl__a21o_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5965/X`
7.884	sky130_fd_sc_hvl__a21oi_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5979/A2`
8.111	sky130_fd_sc_hvl__a21oi_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5979/Y`
8.111	sky130_fd_sc_hvl__nor3_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5980/C`
8.525	sky130_fd_sc_hvl__nor3_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5980/Y`
8.525	sky130_fd_sc_hvl__o21ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5992/A1`
8.838	sky130_fd_sc_hvl__o21ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5992/Y`
8.838	sky130_fd_sc_hvl__xor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5993/B`
9.121	sky130_fd_sc_hvl__xor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5993/X`
9.121	sky130_fd_sc_hvl__dfxtp_1	`spins_2d[7]$_DFF_P_/D`

Path 2-9.239 ns

From: abs_1d[11]$_DFF_P_/Q

To: spins_2d[8]$_DFF_P_/D

Data Arrival: 9.075 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`abs_1d[11]$_DFF_P_/CLK`
1.260	sky130_fd_sc_hvl__dfxtp_1	`abs_1d[11]$_DFF_P_/Q`
1.260	sky130_fd_sc_hvl__xor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5578/B`
1.845	sky130_fd_sc_hvl__xor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5578/X`
1.845	sky130_fd_sc_hvl__xor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5640/A`
2.362	sky130_fd_sc_hvl__xor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5640/X`
2.362	sky130_fd_sc_hvl__o21ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5643/A1`
2.683	sky130_fd_sc_hvl__o21ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5643/Y`
2.683	sky130_fd_sc_hvl__xnor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5646/A`
3.069	sky130_fd_sc_hvl__xnor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5646/Y`
3.069	sky130_fd_sc_hvl__o21ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5651/A1`
3.373	sky130_fd_sc_hvl__o21ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5651/Y`
3.373	sky130_fd_sc_hvl__xnor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5654/A`
3.779	sky130_fd_sc_hvl__xnor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5654/Y`
3.779	sky130_fd_sc_hvl__o21a_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5660/A1`
4.186	sky130_fd_sc_hvl__o21a_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5660/X`
4.186	sky130_fd_sc_hvl__xnor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5663/A`
4.555	sky130_fd_sc_hvl__xnor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5663/Y`
4.555	sky130_fd_sc_hvl__xor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5914/B`
4.901	sky130_fd_sc_hvl__xor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5914/X`
4.901	sky130_fd_sc_hvl__o21a_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5915/B1`
5.158	sky130_fd_sc_hvl__o21a_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5915/X`
5.158	sky130_fd_sc_hvl__or2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5921/A`
5.585	sky130_fd_sc_hvl__or2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5921/X`
5.585	sky130_fd_sc_hvl__or3_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5923/B`
6.265	sky130_fd_sc_hvl__or3_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5923/X`
6.265	sky130_fd_sc_hvl__a21oi_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5924/B1`
6.455	sky130_fd_sc_hvl__a21oi_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5924/Y`
6.455	sky130_fd_sc_hvl__o22ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5927/B1`
6.758	sky130_fd_sc_hvl__o22ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5927/Y`
6.758	sky130_fd_sc_hvl__o21a_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5929/A2`
7.179	sky130_fd_sc_hvl__o21a_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5929/X`
7.179	sky130_fd_sc_hvl__o21ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5949/A1`
7.501	sky130_fd_sc_hvl__o21ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5949/Y`
7.501	sky130_fd_sc_hvl__a21o_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5965/A1`
7.884	sky130_fd_sc_hvl__a21o_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5965/X`
7.884	sky130_fd_sc_hvl__a21oi_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5979/A2`
8.111	sky130_fd_sc_hvl__a21oi_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5979/Y`
8.111	sky130_fd_sc_hvl__nor3_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5980/C`
8.525	sky130_fd_sc_hvl__nor3_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5980/Y`
8.525	sky130_fd_sc_hvl__o21ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5992/A1`
8.838	sky130_fd_sc_hvl__o21ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5992/Y`
8.838	sky130_fd_sc_hvl__o22ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5995/A2`
9.075	sky130_fd_sc_hvl__o22ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5995/Y`
9.075	sky130_fd_sc_hvl__dfxtp_1	`spins_2d[8]$_DFF_P_/D`

Path 3-9.166 ns

From: abs_1d[11]$_DFF_P_/Q

To: spins_2d[6]$_DFF_P_/D

Data Arrival: 8.974 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`clk`
0.000	sky130_fd_sc_hvl__dfxtp_1	`abs_1d[11]$_DFF_P_/CLK`
1.260	sky130_fd_sc_hvl__dfxtp_1	`abs_1d[11]$_DFF_P_/Q`
1.260	sky130_fd_sc_hvl__xor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5578/B`
1.845	sky130_fd_sc_hvl__xor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5578/X`
1.845	sky130_fd_sc_hvl__xor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5640/A`
2.362	sky130_fd_sc_hvl__xor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5640/X`
2.362	sky130_fd_sc_hvl__o21ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5643/A1`
2.683	sky130_fd_sc_hvl__o21ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5643/Y`
2.683	sky130_fd_sc_hvl__xnor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5646/A`
3.069	sky130_fd_sc_hvl__xnor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5646/Y`
3.069	sky130_fd_sc_hvl__o21ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5651/A1`
3.373	sky130_fd_sc_hvl__o21ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5651/Y`
3.373	sky130_fd_sc_hvl__xnor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5654/A`
3.779	sky130_fd_sc_hvl__xnor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5654/Y`
3.779	sky130_fd_sc_hvl__o21a_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5660/A1`
4.186	sky130_fd_sc_hvl__o21a_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5660/X`
4.186	sky130_fd_sc_hvl__xnor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5663/A`
4.555	sky130_fd_sc_hvl__xnor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5663/Y`
4.555	sky130_fd_sc_hvl__xor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5914/B`
4.901	sky130_fd_sc_hvl__xor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5914/X`
4.901	sky130_fd_sc_hvl__o21a_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5915/B1`
5.158	sky130_fd_sc_hvl__o21a_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5915/X`
5.158	sky130_fd_sc_hvl__or2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5921/A`
5.585	sky130_fd_sc_hvl__or2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5921/X`
5.585	sky130_fd_sc_hvl__or3_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5923/B`
6.265	sky130_fd_sc_hvl__or3_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5923/X`
6.265	sky130_fd_sc_hvl__a21oi_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5924/B1`
6.455	sky130_fd_sc_hvl__a21oi_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5924/Y`
6.455	sky130_fd_sc_hvl__o22ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5927/B1`
6.758	sky130_fd_sc_hvl__o22ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5927/Y`
6.758	sky130_fd_sc_hvl__o21a_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5929/A2`
7.179	sky130_fd_sc_hvl__o21a_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5929/X`
7.179	sky130_fd_sc_hvl__o21ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5949/A1`
7.501	sky130_fd_sc_hvl__o21ai_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5949/Y`
7.501	sky130_fd_sc_hvl__a21o_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5965/A1`
7.884	sky130_fd_sc_hvl__a21o_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5965/X`
7.884	sky130_fd_sc_hvl__a21oi_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5979/A2`
8.111	sky130_fd_sc_hvl__a21oi_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5979/Y`
8.111	sky130_fd_sc_hvl__nor3_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5980/C`
8.525	sky130_fd_sc_hvl__nor3_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5980/Y`
8.525	sky130_fd_sc_hvl__a21oi_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5983/B1`
8.709	sky130_fd_sc_hvl__a21oi_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5983/Y`
8.709	sky130_fd_sc_hvl__xnor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5989/A`
8.974	sky130_fd_sc_hvl__xnor2_1	`$abc$5481$auto$blifparse.cc:396:parse_blif$5989/Y`
8.974	sky130_fd_sc_hvl__dfxtp_1	`spins_2d[6]$_DFF_P_/D`

Post-Synthesis Verilog

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