Latchup
Problems
Leaderboards
Community
Help
SpinalHDL Docs
VHDL Tutorial
Verilog Tutorial
Login
Latchup
Problems
Leaderboards
Community
Help
SpinalHDL Docs
VHDL Tutorial
Verilog Tutorial
Login
SpinalHDL
Amaranth
(0.5)
Bluespec Classic
(2024.07)
Bluespec SV
(2024.07)
Chisel
(7.7.0)
Clash
(1.8)
HardCaml
(0.17.1)
PipelineC
(unstable-2026-03-15)
ROHD
(0.6.8)
Spade
(0.16.0)
SpinalHDL
(1.12.3)
TL-Verilog
(SandPiper API)
Veryl
(0.17.1)
Verilog
(yosys 0.55)
VHDL
(ghdl 5.1.1)
Reset from template
import spinal.core._ import spinal.lib._ // Stream-based solution component // // Input stream interface: // io.i.ready (output): Assert when ready to accept input // io.i.valid (input): Asserted when input data is valid // io.i.payload.* (input): Input payload fields // // Output interface: // io.o.valid (output): Assert when output data is valid // io.o.payload* (output): Output payload fields // // Handshaking: Data transfers when both ready and valid are high case class Solution() extends Component { val io = new Bundle { val i = slave Stream(new Bundle { val spins = Fragment(SInt(16 bits)) }) val o = master Flow(UInt(16 bits)) } // Your code here }
▶
Testcase
‹
1 / 1
›
+
−
>_
Edit locally
View past submissions
Leaderboard
Run
Submit
Back to problem
Leaderboard
#
User
Language
Latency
▼
ns
Throughput
MHz
Area
μm²
Score
1
piasa-dev
Verilog
9367.60 (1005 cycles)
0.11 (0.1%)
16119
95.28
2
Ivan Buda Mandura
Verilog
24601.00 (1000 cycles)
—
10393
59.41
3
MichaelBell
Spade
38167.75 (2414 cycles)
—
6128
59.84
← Previous
Page 1
Next →