Latchup
Problems
Leaderboards
Community
Help
SpinalHDL Docs
VHDL Tutorial
Verilog Tutorial
Login
Latchup
Problems
Leaderboards
Community
Help
SpinalHDL Docs
VHDL Tutorial
Verilog Tutorial
Login
SpinalHDL
Amaranth
Bluespec Classic
Bluespec SV
Chisel
Clash
HardCaml
PipelineC
ROHD
Spade
SpinalHDL
TL-Verilog
Veryl
Verilog
VHDL
Reset from template
import spinal.core._ import spinal.lib._ // Stream-based solution component // // Input stream interface: // io.i.ready (output): Assert when ready to accept input // io.i.valid (input): Asserted when input data is valid // io.i.payload.* (input): Input payload fields // // Output interface: // io.o.valid (output): Assert when output data is valid // io.o.payload* (output): Output payload fields // // Handshaking: Data transfers when both ready and valid are high case class Solution() extends Component { val io = new Bundle { val i = slave Stream(new Bundle { val spins = Fragment(SInt(16 bits)) }) val o = master Flow(UInt(16 bits)) } // Your code here }
▶
Testcase
‹
1 / 1
›
+
−
>_
Edit locally
View past submissions
Leaderboard
Run
Submit
Back to problem
Leaderboard
#
User
Language
Latency
▼
ns
Max Frequency
MHz
Area
μm²
1
piasa-dev
Verilog
9367.60 (1005 cycles)
107.28
16119
2
Ivan Buda Mandura
Verilog
24601.00 (1000 cycles)
40.65
10393
3
MichaelBell
Spade
38167.75 (2414 cycles)
63.25
6128
← Previous
Page 1
Next →