Tidy Numbers - Latchup

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Submission #1

PASSED

RankingPercentile

Latency

2.75 (1 cycles)ns

1st

top 1%

Max Frequency

363.50MHz

1st

top 1%

Area

795μm²

1st

top 1%

Submitted Solution

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready,
  input wire i_valid,
  input wire [4-1:0] i_payload_n_0,
  input wire [4-1:0] i_payload_n_1,
  input wire [4-1:0] i_payload_n_2,
  input wire [4-1:0] i_payload_n_3,
  output wire [4-1:0] o_payload_0,
  output wire [4-1:0] o_payload_1,
  output wire [4-1:0] o_payload_2,
  output wire [4-1:0] o_payload_3,
  output wire o_valid
);

reg [3:0] gt;
reg [3:0] nt;
reg tidy;
reg [3:0] sub;
reg [3:0] load9;
reg [3:0] calc_0;
reg [3:0] calc_1;
reg [3:0] calc_2;
reg [3:0] calc_3;
reg [3:0] result_0;
reg [3:0] result_1;
reg [3:0] result_2;
reg [3:0] result_3;
// Define your design here
//
// input is 1000*x[0] + 100*x[1] + 10*x[2] + x[3].
//
// make gt vector of (x[1] > x[0]), (x[2] > x[1]), (x[3] > x[2])
// this can be any value.
// generate a 1-hot version with the leftmost 1 set.  (if any)
// this 1-hot vector represens if x[0],x[1], or x[2] should have a subtraction
// note that this will never happen if the digit is 0, so no need to worry about 0->15 vs 0->9.
//
// this gives four cases:
// 000 -- already tidy.
// 100 -- subtract1 from msb, set 3 to the right to 9
// 010 -- sub from 2nd, set 3rd/4th to 9
// 001 -- sub from 3rd, set 4th to 9
//
// in terms of sub/load signals:
// 000 -> 0000 0000
// 100 -> 1000 0111
// 010 -> 0100 0011
// 001 -> 0010 0001
//
// this suggests using subtraction to get loads from sub.
// 

always@(*) begin
    // input is x[0:3]
    // bitscan find leftmost.  gt needs to be flipped.
    // bitscan normally takes an input like 1100 and finds the RIGHTMOST 1
    // as a 1-hot vector, or 0.  in this case 1100 -> 0100.  and 0000 -> 0000
    //
    // this flips the vector to allow the rightmost in the operation to
    // represent the leftmost in the original.
    // 
    // a 1 is added to this vector as a msb.  it will only be rightmost
    // when the input is 000.  this allows this msb to be used as a check
    // that tidy = (sub[2:0] == 0);
    gt[0] = i_payload_n_0 > i_payload_n_1;
    gt[1] = i_payload_n_1 > i_payload_n_2;
    gt[2] = i_payload_n_2 > i_payload_n_3;
    gt[3] = 1'b1;
    nt = ~gt + 1;
    // bitscan.  output flipped back.  "tidy" is set only when already tidy.
    // note that sub[2] means the msb gets the subtraction, sub[1] the next
    // sub[0] the third.  there's no case where the last digit has a subtract.
    sub = 0;
    {tidy,sub[1],sub[2],sub[3]} = gt & nt;
    // digits right of subtract are set to 9.
    // this also gets optimized.
    // 0>0>0 : 1000 -> 1 000x x000
    // 1>x>y : 1001 -> 0 100x x111
    // 0>1>x : 1010 -> 0 010x x011
    // 0>0>1 : 1100 -> 0 001x x001
    //
    load9 = {1'b0, sub[3], (sub[3] | sub[2]), !tidy};

    // output sub and load logic.
    calc_0 = i_payload_n_0 - sub[3];
    calc_1 = i_payload_n_1 - sub[2];
    calc_2 = i_payload_n_2 - sub[1];
    calc_3 = i_payload_n_3 - sub[0];
    result_0 = calc_0;
    result_1 = load9[2] ? 4'd9 : calc_1;
    result_2 = load9[1] ? 4'd9 : calc_2;
    result_3 = load9[0] ? 4'd9 : calc_3;

end

assign o_payload_0 = result_0;
assign o_payload_1 = result_1;
assign o_payload_2 = result_2;
assign o_payload_3 = result_3;
assign o_valid = i_valid;
assign i_ready = !reset;

endmodule

Generated Verilog

// Stream-based solution component
//
// Input stream interface:
//   i_ready (output): Assert when ready to accept input
//   i_valid (input): Asserted when input data is valid
//   i_payload_* (input): Input payload fields
//
// Output interface:
//   o_valid (output): Assert when output data is valid
//   o_payload* (output): Output payload fields
//
// Handshaking: Data transfers when both ready and valid are high

module Solution (
  input wire clk,
  input wire reset,
  output wire i_ready,
  input wire i_valid,
  input wire [4-1:0] i_payload_n_0,
  input wire [4-1:0] i_payload_n_1,
  input wire [4-1:0] i_payload_n_2,
  input wire [4-1:0] i_payload_n_3,
  output wire [4-1:0] o_payload_0,
  output wire [4-1:0] o_payload_1,
  output wire [4-1:0] o_payload_2,
  output wire [4-1:0] o_payload_3,
  output wire o_valid
);

reg [3:0] gt;
reg [3:0] nt;
reg tidy;
reg [3:0] sub;
reg [3:0] load9;
reg [3:0] calc_0;
reg [3:0] calc_1;
reg [3:0] calc_2;
reg [3:0] calc_3;
reg [3:0] result_0;
reg [3:0] result_1;
reg [3:0] result_2;
reg [3:0] result_3;
// Define your design here
//
// input is 1000*x[0] + 100*x[1] + 10*x[2] + x[3].
//
// make gt vector of (x[1] > x[0]), (x[2] > x[1]), (x[3] > x[2])
// this can be any value.
// generate a 1-hot version with the leftmost 1 set.  (if any)
// this 1-hot vector represens if x[0],x[1], or x[2] should have a subtraction
// note that this will never happen if the digit is 0, so no need to worry about 0->15 vs 0->9.
//
// this gives four cases:
// 000 -- already tidy.
// 100 -- subtract1 from msb, set 3 to the right to 9
// 010 -- sub from 2nd, set 3rd/4th to 9
// 001 -- sub from 3rd, set 4th to 9
//
// in terms of sub/load signals:
// 000 -> 0000 0000
// 100 -> 1000 0111
// 010 -> 0100 0011
// 001 -> 0010 0001
//
// this suggests using subtraction to get loads from sub.
// 

always@(*) begin
    // input is x[0:3]
    // bitscan find leftmost.  gt needs to be flipped.
    // bitscan normally takes an input like 1100 and finds the RIGHTMOST 1
    // as a 1-hot vector, or 0.  in this case 1100 -> 0100.  and 0000 -> 0000
    //
    // this flips the vector to allow the rightmost in the operation to
    // represent the leftmost in the original.
    // 
    // a 1 is added to this vector as a msb.  it will only be rightmost
    // when the input is 000.  this allows this msb to be used as a check
    // that tidy = (sub[2:0] == 0);
    gt[0] = i_payload_n_0 > i_payload_n_1;
    gt[1] = i_payload_n_1 > i_payload_n_2;
    gt[2] = i_payload_n_2 > i_payload_n_3;
    gt[3] = 1'b1;
    nt = ~gt + 1;
    // bitscan.  output flipped back.  "tidy" is set only when already tidy.
    // note that sub[2] means the msb gets the subtraction, sub[1] the next
    // sub[0] the third.  there's no case where the last digit has a subtract.
    sub = 0;
    {tidy,sub[1],sub[2],sub[3]} = gt & nt;
    // digits right of subtract are set to 9.
    // this also gets optimized.
    // 0>0>0 : 1000 -> 1 000x x000
    // 1>x>y : 1001 -> 0 100x x111
    // 0>1>x : 1010 -> 0 010x x011
    // 0>0>1 : 1100 -> 0 001x x001
    //
    load9 = {1'b0, sub[3], (sub[3] | sub[2]), !tidy};

    // output sub and load logic.
    calc_0 = i_payload_n_0 - sub[3];
    calc_1 = i_payload_n_1 - sub[2];
    calc_2 = i_payload_n_2 - sub[1];
    calc_3 = i_payload_n_3 - sub[0];
    result_0 = calc_0;
    result_1 = load9[2] ? 4'd9 : calc_1;
    result_2 = load9[1] ? 4'd9 : calc_2;
    result_3 = load9[0] ? 4'd9 : calc_3;

end

assign o_payload_0 = result_0;
assign o_payload_1 = result_1;
assign o_payload_2 = result_2;
assign o_payload_3 = result_3;
assign o_valid = i_valid;
assign i_ready = !reset;

endmodule

Timing Analysis

Path 1-2.752 ns

From: i_payload_n_1[2]

To: o_payload_2[0]

Data Arrival: 2.753 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`i_payload_n_1[2]`
0.000	sky130_fd_sc_hvl__inv_1	`$abc$582$auto$blifparse.cc:396:parse_blif$585/A`
0.130	sky130_fd_sc_hvl__inv_1	`$abc$582$auto$blifparse.cc:396:parse_blif$585/Y`
0.130	sky130_fd_sc_hvl__o22ai_1	`$abc$582$auto$blifparse.cc:396:parse_blif$600/A1`
0.365	sky130_fd_sc_hvl__o22ai_1	`$abc$582$auto$blifparse.cc:396:parse_blif$600/Y`
0.365	sky130_fd_sc_hvl__o22ai_1	`$abc$582$auto$blifparse.cc:396:parse_blif$601/B2`
0.618	sky130_fd_sc_hvl__o22ai_1	`$abc$582$auto$blifparse.cc:396:parse_blif$601/Y`
0.618	sky130_fd_sc_hvl__o21ai_1	`$abc$582$auto$blifparse.cc:396:parse_blif$602/A2`
1.200	sky130_fd_sc_hvl__o21ai_1	`$abc$582$auto$blifparse.cc:396:parse_blif$602/Y`
1.200	sky130_fd_sc_hvl__nand2_1	`$abc$582$auto$blifparse.cc:396:parse_blif$612/A`
1.619	sky130_fd_sc_hvl__nand2_1	`$abc$582$auto$blifparse.cc:396:parse_blif$612/Y`
1.619	sky130_fd_sc_hvl__or2_1	`$abc$582$auto$blifparse.cc:396:parse_blif$628/A`
2.252	sky130_fd_sc_hvl__or2_1	`$abc$582$auto$blifparse.cc:396:parse_blif$628/X`
2.252	sky130_fd_sc_hvl__mux2_1	`$abc$582$auto$blifparse.cc:396:parse_blif$630/A0`
2.753	sky130_fd_sc_hvl__mux2_1	`$abc$582$auto$blifparse.cc:396:parse_blif$630/X`
2.753	Solution	`o_payload_2[0]`

Path 2-2.661 ns

From: i_payload_n_1[2]

To: o_payload_3[0]

Data Arrival: 2.662 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`i_payload_n_1[2]`
0.000	sky130_fd_sc_hvl__inv_1	`$abc$582$auto$blifparse.cc:396:parse_blif$585/A`
0.130	sky130_fd_sc_hvl__inv_1	`$abc$582$auto$blifparse.cc:396:parse_blif$585/Y`
0.130	sky130_fd_sc_hvl__o22ai_1	`$abc$582$auto$blifparse.cc:396:parse_blif$600/A1`
0.365	sky130_fd_sc_hvl__o22ai_1	`$abc$582$auto$blifparse.cc:396:parse_blif$600/Y`
0.365	sky130_fd_sc_hvl__o22ai_1	`$abc$582$auto$blifparse.cc:396:parse_blif$601/B2`
0.618	sky130_fd_sc_hvl__o22ai_1	`$abc$582$auto$blifparse.cc:396:parse_blif$601/Y`
0.618	sky130_fd_sc_hvl__o21ai_1	`$abc$582$auto$blifparse.cc:396:parse_blif$602/A2`
1.200	sky130_fd_sc_hvl__o21ai_1	`$abc$582$auto$blifparse.cc:396:parse_blif$602/Y`
1.200	sky130_fd_sc_hvl__nand2_1	`$abc$582$auto$blifparse.cc:396:parse_blif$612/A`
1.619	sky130_fd_sc_hvl__nand2_1	`$abc$582$auto$blifparse.cc:396:parse_blif$612/Y`
1.619	sky130_fd_sc_hvl__or2_1	`$abc$582$auto$blifparse.cc:396:parse_blif$628/A`
2.252	sky130_fd_sc_hvl__or2_1	`$abc$582$auto$blifparse.cc:396:parse_blif$628/X`
2.252	sky130_fd_sc_hvl__or2_1	`$abc$582$auto$blifparse.cc:396:parse_blif$639/B`
2.662	sky130_fd_sc_hvl__or2_1	`$abc$582$auto$blifparse.cc:396:parse_blif$639/X`
2.662	Solution	`o_payload_3[0]`

Path 3-2.661 ns

From: i_payload_n_1[2]

To: o_payload_3[3]

Data Arrival: 2.662 ns

Arrival (ns)	Cell	Pin
0.000	Solution	`i_payload_n_1[2]`
0.000	sky130_fd_sc_hvl__inv_1	`$abc$582$auto$blifparse.cc:396:parse_blif$585/A`
0.130	sky130_fd_sc_hvl__inv_1	`$abc$582$auto$blifparse.cc:396:parse_blif$585/Y`
0.130	sky130_fd_sc_hvl__o22ai_1	`$abc$582$auto$blifparse.cc:396:parse_blif$600/A1`
0.365	sky130_fd_sc_hvl__o22ai_1	`$abc$582$auto$blifparse.cc:396:parse_blif$600/Y`
0.365	sky130_fd_sc_hvl__o22ai_1	`$abc$582$auto$blifparse.cc:396:parse_blif$601/B2`
0.618	sky130_fd_sc_hvl__o22ai_1	`$abc$582$auto$blifparse.cc:396:parse_blif$601/Y`
0.618	sky130_fd_sc_hvl__o21ai_1	`$abc$582$auto$blifparse.cc:396:parse_blif$602/A2`
1.200	sky130_fd_sc_hvl__o21ai_1	`$abc$582$auto$blifparse.cc:396:parse_blif$602/Y`
1.200	sky130_fd_sc_hvl__nand2_1	`$abc$582$auto$blifparse.cc:396:parse_blif$612/A`
1.619	sky130_fd_sc_hvl__nand2_1	`$abc$582$auto$blifparse.cc:396:parse_blif$612/Y`
1.619	sky130_fd_sc_hvl__or2_1	`$abc$582$auto$blifparse.cc:396:parse_blif$628/A`
2.252	sky130_fd_sc_hvl__or2_1	`$abc$582$auto$blifparse.cc:396:parse_blif$628/X`
2.252	sky130_fd_sc_hvl__or2_1	`$abc$582$auto$blifparse.cc:396:parse_blif$642/B`
2.662	sky130_fd_sc_hvl__or2_1	`$abc$582$auto$blifparse.cc:396:parse_blif$642/X`
2.662	Solution	`o_payload_3[3]`

Post-Synthesis Verilog

Download synth.v