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SpinalHDL
Amaranth
(0.5)
Bluespec Classic
(2024.07)
Bluespec SV
(2024.07)
Chisel
(7.7.0)
Clash
(1.8)
HardCaml
(0.17.1)
PipelineC
(unstable-2026-03-15)
ROHD
(0.6.8)
Spade
(0.16.0)
SpinalHDL
(1.12.3)
TL-Verilog
(SandPiper API)
Veryl
(0.17.1)
Verilog
(yosys 0.55)
VHDL
(ghdl 5.1.1)
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import spinal.core._ import spinal.lib._ // Stream-based solution component // // Input stream interface: // io.i.ready (output): Assert when ready to accept input // io.i.valid (input): Asserted when input data is valid // io.i.payload.* (input): Input payload fields // // Output interface: // io.o.valid (output): Assert when output data is valid // io.o.payload* (output): Output payload fields // // Handshaking: Data transfers when both ready and valid are high case class Solution() extends Component { val io = new Bundle { val i = slave Stream(new Bundle { val n = Vec(UInt(4 bits), 4) }) val o = master Flow(Vec(UInt(4 bits), 4)) } // Your code here }
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#
User
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Latency
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ns
Throughput
MHz
Area
μm²
Score
1
psmears
Amaranth
2.49 (1 cycles)
401.45 (100.0%)
828
99.80
2
Vegard Eriksen
Amaranth
2.49 (1 cycles)
401.45 (100.0%)
1012
98.84
3
piasa-dev
Verilog
2.75 (1 cycles)
363.50 (100.0%)
795
99.05
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