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SpinalHDL
Amaranth
(0.5)
Bluespec Classic
(2024.07)
Bluespec SV
(2024.07)
Chisel
(7.7.0)
Clash
(1.8)
CoHDL
(0.2.4)
HardCaml
(0.17.1)
Logisim
(4.0.0)
PipelineC
(unstable-122eb8f)
Pypeline
(unstable-122eb8f)
ROHD
(0.6.8)
Spade
(0.16.0)
SpinalHDL
(1.12.3)
TL-Verilog
(SandPiper API)
VHDL
(ghdl 5.1.1)
Verilog
(yosys 0.55)
Veryl
(0.17.1)
XLS
(0.51.0)
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import spinal.core._ import spinal.lib._ // Stream-based solution component // // Input stream interface: // io.i.ready (output): Assert when ready to accept input // io.i.valid (input): Asserted when input data is valid // io.i.payload.* (input): Input payload fields // // Output interface: // io.o.valid (output): Assert when output data is valid // io.o.payload* (output): Output payload fields // // Handshaking: Data transfers when both ready and valid are high case class Solution() extends Component { val io = new Bundle { val i = slave Stream(new Bundle { val stream = Fragment(UInt(16 bits)) val k = UInt(4 bits) }) val o = master Flow(Fragment(Fragment(UInt(16 bits)))) } // Your code here }
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#
User
Language
Latency
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ns
Throughput
MHz
Area
μm²
Score
1
piasa-dev
Verilog
4099.37 (728 cycles)
23.68 (13.3%)
23404
100.00
2
merlijn
Verilog
9229.87 (729 cycles)
10.53 (13.3%)
37374
89.95
3
psmears
Amaranth
23800.96 (819 cycles)
4.05 (11.8%)
61114
78.43
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